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[/] [or1200_hp/] [trunk/] [ise/] [ise_cm3/] [or1200_top_cm3.twr] - Blame information for rev 2

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--------------------------------------------------------------------------------
Release 11.1 Trace  (nt)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
C:\Xilinx\11.1\ISE\bin\nt\unwrapped\trce.exe -ise
C:/EDAptability/coremultiplier/reference/or1200_new/ise/ise_or1200_cm3/ise_or1200_cm3/ise_or1200_cm3.ise
-intstyle ise -v 3 -s 1 -fastpaths -xml or1200_top_cm3.twx or1200_top_cm3.ncd
-o or1200_top_cm3.twr or1200_top_cm3.pcf -ucf or1200_top_cm3.ucf
 
Design file:              or1200_top_cm3.ncd
Physical constraint file: or1200_top_cm3.pcf
Device,package,speed:     xc5vlx50,ff676,-1 (PRODUCTION 1.64 2009-03-03, STEPPING level 0)
Report level:             verbose report
 
Environment Variable      Effect
--------------------      ------
NONE                      No environment variables were set
--------------------------------------------------------------------------------
 
WARNING:Timing:3223 - Timing constraint TS_clk_i_clk_i_cml_2_ERROR = MAXDELAY
   FROM TIMEGRP "clk_i" TO TIMEGRP        "clk_i_cml_2" 1 ns DATAPATHONLY;
   ignored during timing analysis.
WARNING:Timing:3223 - Timing constraint TS_clk_i_cml_1_clk_i_ERROR = MAXDELAY
   FROM TIMEGRP "clk_i_cml_1" TO TIMEGRP        "clk_i" 1 ns DATAPATHONLY;
   ignored during timing analysis.
WARNING:Timing:3223 - Timing constraint TS_clk_i_cml_2_clk_i_cml_1_ERROR =
   MAXDELAY FROM TIMEGRP "clk_i_cml_2" TO        TIMEGRP "clk_i_cml_1" 1 ns
   DATAPATHONLY; ignored during timing analysis.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
   a 50 Ohm transmission line loading model.  For the details of this model,
   and for more information on accounting for different loading conditions,
   please see the device datasheet.
 
================================================================================
Timing constraint: TS_clk_i_ERROR = PERIOD TIMEGRP "clk_i" 1 ns HIGH 50%;
 
 
 3242 timing errors detected. (3242 component switching limit errors)
 Minimum period is   2.400ns.
--------------------------------------------------------------------------------
 
Component Switching Limit Checks: TS_clk_i_ERROR = PERIOD TIMEGRP "clk_i" 1 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: -1.400ns (period - (min high pulse limit / (high pulse / period)))
  Period: 1.000ns
  High pulse: 0.500ns
  High pulse limit: 1.200ns (Tospwh)
  Physical resource: or1200_du/dbg_ack_o/SR
  Logical resource: or1200_du/dbg_ack_o/SR
  Location pin: OLOGIC_X1Y67.SR
  Clock network: rst_i_IBUF
--------------------------------------------------------------------------------
Slack: -1.400ns (period - (min high pulse limit / (high pulse / period)))
  Period: 1.000ns
  High pulse: 0.500ns
  High pulse limit: 1.200ns (Tospwh)
  Physical resource: dwb_biu/wb_adr_o_10_1/SR
  Logical resource: dwb_biu/wb_adr_o_10_1/SR
  Location pin: OLOGIC_X1Y141.SR
  Clock network: rst_i_IBUF
--------------------------------------------------------------------------------
Slack: -1.400ns (period - (min high pulse limit / (high pulse / period)))
  Period: 1.000ns
  High pulse: 0.500ns
  High pulse limit: 1.200ns (Tospwh)
  Physical resource: dwb_biu/wb_adr_o_11_1/SR
  Logical resource: dwb_biu/wb_adr_o_11_1/SR
  Location pin: OLOGIC_X1Y162.SR
  Clock network: rst_i_IBUF
--------------------------------------------------------------------------------
 
================================================================================
Timing constraint: TS_clk_i_cml_1_ERROR = PERIOD TIMEGRP "clk_i_cml_1" 1 ns
HIGH 50%;
 
 
 
 Minimum period is   0.818ns.
--------------------------------------------------------------------------------
 
Component Switching Limit Checks: TS_clk_i_cml_1_ERROR = PERIOD TIMEGRP "clk_i_cml_1" 1 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 0.182ns (period - (min low pulse limit / (low pulse / period)))
  Period: 1.000ns
  Low pulse: 0.500ns
  Low pulse limit: 0.409ns (Tcl)
  Physical resource: or1200_cpu/or1200_alu/result_sum_cml_1<3>/CLK
  Logical resource: or1200_cpu/or1200_alu/result_sum_cml_1_0/CK
  Location pin: SLICE_X47Y61.CLK
  Clock network: clk_i_cml_1_BUFGP
--------------------------------------------------------------------------------
Slack: 0.182ns (period - (min high pulse limit / (high pulse / period)))
  Period: 1.000ns
  High pulse: 0.500ns
  High pulse limit: 0.409ns (Tch)
  Physical resource: or1200_cpu/or1200_alu/result_sum_cml_1<3>/CLK
  Logical resource: or1200_cpu/or1200_alu/result_sum_cml_1_0/CK
  Location pin: SLICE_X47Y61.CLK
  Clock network: clk_i_cml_1_BUFGP
--------------------------------------------------------------------------------
Slack: 0.182ns (period - (min low pulse limit / (low pulse / period)))
  Period: 1.000ns
  Low pulse: 0.500ns
  Low pulse limit: 0.409ns (Tcl)
  Physical resource: or1200_cpu/or1200_alu/result_sum_cml_1<3>/CLK
  Logical resource: or1200_cpu/or1200_alu/result_sum_cml_1_1/CK
  Location pin: SLICE_X47Y61.CLK
  Clock network: clk_i_cml_1_BUFGP
--------------------------------------------------------------------------------
 
================================================================================
Timing constraint: TS_clk_i_cml_2_ERROR = PERIOD TIMEGRP "clk_i_cml_2" 1 ns
HIGH 50%;
 
 
 
 Minimum period is   1.000ns.
--------------------------------------------------------------------------------
 
Component Switching Limit Checks: TS_clk_i_cml_2_ERROR = PERIOD TIMEGRP "clk_i_cml_2" 1 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 0.000ns (period - (min low pulse limit / (low pulse / period)))
  Period: 1.000ns
  Low pulse: 0.500ns
  Low pulse limit: 0.500ns (Tockpwl)
  Physical resource: or1200_pm/pm_cpu_gate_cml_2_4/CLK
  Logical resource: or1200_pm/pm_cpu_gate_cml_2_4/CK
  Location pin: OLOGIC_X2Y162.CLK
  Clock network: clk_i_cml_2_BUFGP
--------------------------------------------------------------------------------
Slack: 0.000ns (period - (min high pulse limit / (high pulse / period)))
  Period: 1.000ns
  High pulse: 0.500ns
  High pulse limit: 0.500ns (Tockpwh)
  Physical resource: or1200_pm/pm_cpu_gate_cml_2_4/CLK
  Logical resource: or1200_pm/pm_cpu_gate_cml_2_4/CK
  Location pin: OLOGIC_X2Y162.CLK
  Clock network: clk_i_cml_2_BUFGP
--------------------------------------------------------------------------------
Slack: 0.000ns (period - min period limit)
  Period: 1.000ns
  Min period limit: 1.000ns (1000.000MHz) (Tockper)
  Physical resource: or1200_pm/pm_cpu_gate_cml_2_4/CLK
  Logical resource: or1200_pm/pm_cpu_gate_cml_2_4/CK
  Location pin: OLOGIC_X2Y162.CLK
  Clock network: clk_i_cml_2_BUFGP
--------------------------------------------------------------------------------
 
================================================================================
Timing constraint: TS_clk_i_clk_i_cml_2_ERROR = MAXDELAY FROM TIMEGRP "clk_i"
TO TIMEGRP         "clk_i_cml_2" 1 ns DATAPATHONLY;
 
 
 
--------------------------------------------------------------------------------
 
================================================================================
Timing constraint: TS_clk_i_cml_1_clk_i_ERROR = MAXDELAY FROM TIMEGRP
"clk_i_cml_1" TO TIMEGRP         "clk_i" 1 ns DATAPATHONLY;
 
 
 
--------------------------------------------------------------------------------
 
================================================================================
Timing constraint: TS_clk_i_cml_2_clk_i_cml_1_ERROR = MAXDELAY FROM TIMEGRP
"clk_i_cml_2" TO         TIMEGRP "clk_i_cml_1" 1 ns DATAPATHONLY;
 
 
 
--------------------------------------------------------------------------------
 
 
1 constraint not met.
 
 
Data Sheet report:
-----------------
No constraints were found to generate data for the Data Sheet Report section.
Use the Advanced Analysis (-a) option or generate global constraints for each
clock, its pad to setup and clock to pad paths, and a pad to pad constraint.
 
Timing summary:
---------------
 
Timing errors: 3242  Score: 923522  (Setup/Max: 0, Hold: 0, Component Switching Limit: 923522)
 
Constraints cover 0 paths, 0 nets, and 0 connections
 
Design statistics:
   Minimum period:   2.400ns{1}   (Maximum frequency: 416.667MHz)
 
 
------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.
 
Analysis completed Thu Oct 21 15:32:58 2010
--------------------------------------------------------------------------------
 
Trace Settings:
-------------------------
Trace Settings
 
Peak Memory Usage: 317 MB
 
 
 

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[/] [or1200_hp/] [trunk/] [ise/] [ise_cm3/] [or1200_top_cm3.twr] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	tobil	`--------------------------------------------------------------------------------`
2			`Release 11.1 Trace (nt)`
3			`Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.`
4
5			`C:\Xilinx\11.1\ISE\bin\nt\unwrapped\trce.exe -ise`
6			`C:/EDAptability/coremultiplier/reference/or1200_new/ise/ise_or1200_cm3/ise_or1200_cm3/ise_or1200_cm3.ise`
7			`-intstyle ise -v 3 -s 1 -fastpaths -xml or1200_top_cm3.twx or1200_top_cm3.ncd`
8			`-o or1200_top_cm3.twr or1200_top_cm3.pcf -ucf or1200_top_cm3.ucf`
9
10			`Design file: or1200_top_cm3.ncd`
11			`Physical constraint file: or1200_top_cm3.pcf`
12			`Device,package,speed: xc5vlx50,ff676,-1 (PRODUCTION 1.64 2009-03-03, STEPPING level 0)`
13			`Report level: verbose report`
14
15			`Environment Variable Effect`
16			`-------------------- ------`
17			`NONE No environment variables were set`
18			`--------------------------------------------------------------------------------`
19
20			`WARNING:Timing:3223 - Timing constraint TS_clk_i_clk_i_cml_2_ERROR = MAXDELAY`
21			`FROM TIMEGRP "clk_i" TO TIMEGRP "clk_i_cml_2" 1 ns DATAPATHONLY;`
22			`ignored during timing analysis.`
23			`WARNING:Timing:3223 - Timing constraint TS_clk_i_cml_1_clk_i_ERROR = MAXDELAY`
24			`FROM TIMEGRP "clk_i_cml_1" TO TIMEGRP "clk_i" 1 ns DATAPATHONLY;`
25			`ignored during timing analysis.`
26			`WARNING:Timing:3223 - Timing constraint TS_clk_i_cml_2_clk_i_cml_1_ERROR =`
27			`MAXDELAY FROM TIMEGRP "clk_i_cml_2" TO TIMEGRP "clk_i_cml_1" 1 ns`
28			`DATAPATHONLY; ignored during timing analysis.`
29			`INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths`
30			`option. All paths that are not constrained will be reported in the`
31			`unconstrained paths section(s) of the report.`
32			`INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on`
33			`a 50 Ohm transmission line loading model. For the details of this model,`
34			`and for more information on accounting for different loading conditions,`
35			`please see the device datasheet.`
36
37			`================================================================================`
38			`Timing constraint: TS_clk_i_ERROR = PERIOD TIMEGRP "clk_i" 1 ns HIGH 50%;`
39
40
41			`3242 timing errors detected. (3242 component switching limit errors)`
42			`Minimum period is 2.400ns.`
43			`--------------------------------------------------------------------------------`
44
45			`Component Switching Limit Checks: TS_clk_i_ERROR = PERIOD TIMEGRP "clk_i" 1 ns HIGH 50%;`
46			`--------------------------------------------------------------------------------`
47			`Slack: -1.400ns (period - (min high pulse limit / (high pulse / period)))`
48			`Period: 1.000ns`
49			`High pulse: 0.500ns`
50			`High pulse limit: 1.200ns (Tospwh)`
51			`Physical resource: or1200_du/dbg_ack_o/SR`
52			`Logical resource: or1200_du/dbg_ack_o/SR`
53			`Location pin: OLOGIC_X1Y67.SR`
54			`Clock network: rst_i_IBUF`
55			`--------------------------------------------------------------------------------`
56			`Slack: -1.400ns (period - (min high pulse limit / (high pulse / period)))`
57			`Period: 1.000ns`
58			`High pulse: 0.500ns`
59			`High pulse limit: 1.200ns (Tospwh)`
60			`Physical resource: dwb_biu/wb_adr_o_10_1/SR`
61			`Logical resource: dwb_biu/wb_adr_o_10_1/SR`
62			`Location pin: OLOGIC_X1Y141.SR`
63			`Clock network: rst_i_IBUF`
64			`--------------------------------------------------------------------------------`
65			`Slack: -1.400ns (period - (min high pulse limit / (high pulse / period)))`
66			`Period: 1.000ns`
67			`High pulse: 0.500ns`
68			`High pulse limit: 1.200ns (Tospwh)`
69			`Physical resource: dwb_biu/wb_adr_o_11_1/SR`
70			`Logical resource: dwb_biu/wb_adr_o_11_1/SR`
71			`Location pin: OLOGIC_X1Y162.SR`
72			`Clock network: rst_i_IBUF`
73			`--------------------------------------------------------------------------------`
74
75			`================================================================================`
76			`Timing constraint: TS_clk_i_cml_1_ERROR = PERIOD TIMEGRP "clk_i_cml_1" 1 ns`
77			`HIGH 50%;`
78
79
80
81			`Minimum period is 0.818ns.`
82			`--------------------------------------------------------------------------------`
83
84			`Component Switching Limit Checks: TS_clk_i_cml_1_ERROR = PERIOD TIMEGRP "clk_i_cml_1" 1 ns HIGH 50%;`
85			`--------------------------------------------------------------------------------`
86			`Slack: 0.182ns (period - (min low pulse limit / (low pulse / period)))`
87			`Period: 1.000ns`
88			`Low pulse: 0.500ns`
89			`Low pulse limit: 0.409ns (Tcl)`
90			`Physical resource: or1200_cpu/or1200_alu/result_sum_cml_1<3>/CLK`
91			`Logical resource: or1200_cpu/or1200_alu/result_sum_cml_1_0/CK`
92			`Location pin: SLICE_X47Y61.CLK`
93			`Clock network: clk_i_cml_1_BUFGP`
94			`--------------------------------------------------------------------------------`
95			`Slack: 0.182ns (period - (min high pulse limit / (high pulse / period)))`
96			`Period: 1.000ns`
97			`High pulse: 0.500ns`
98			`High pulse limit: 0.409ns (Tch)`
99			`Physical resource: or1200_cpu/or1200_alu/result_sum_cml_1<3>/CLK`
100			`Logical resource: or1200_cpu/or1200_alu/result_sum_cml_1_0/CK`
101			`Location pin: SLICE_X47Y61.CLK`
102			`Clock network: clk_i_cml_1_BUFGP`
103			`--------------------------------------------------------------------------------`
104			`Slack: 0.182ns (period - (min low pulse limit / (low pulse / period)))`
105			`Period: 1.000ns`
106			`Low pulse: 0.500ns`
107			`Low pulse limit: 0.409ns (Tcl)`
108			`Physical resource: or1200_cpu/or1200_alu/result_sum_cml_1<3>/CLK`
109			`Logical resource: or1200_cpu/or1200_alu/result_sum_cml_1_1/CK`
110			`Location pin: SLICE_X47Y61.CLK`
111			`Clock network: clk_i_cml_1_BUFGP`
112			`--------------------------------------------------------------------------------`
113
114			`================================================================================`
115			`Timing constraint: TS_clk_i_cml_2_ERROR = PERIOD TIMEGRP "clk_i_cml_2" 1 ns`
116			`HIGH 50%;`
117
118
119
120			`Minimum period is 1.000ns.`
121			`--------------------------------------------------------------------------------`
122
123			`Component Switching Limit Checks: TS_clk_i_cml_2_ERROR = PERIOD TIMEGRP "clk_i_cml_2" 1 ns HIGH 50%;`
124			`--------------------------------------------------------------------------------`
125			`Slack: 0.000ns (period - (min low pulse limit / (low pulse / period)))`
126			`Period: 1.000ns`
127			`Low pulse: 0.500ns`
128			`Low pulse limit: 0.500ns (Tockpwl)`
129			`Physical resource: or1200_pm/pm_cpu_gate_cml_2_4/CLK`
130			`Logical resource: or1200_pm/pm_cpu_gate_cml_2_4/CK`
131			`Location pin: OLOGIC_X2Y162.CLK`
132			`Clock network: clk_i_cml_2_BUFGP`
133			`--------------------------------------------------------------------------------`
134			`Slack: 0.000ns (period - (min high pulse limit / (high pulse / period)))`
135			`Period: 1.000ns`
136			`High pulse: 0.500ns`
137			`High pulse limit: 0.500ns (Tockpwh)`
138			`Physical resource: or1200_pm/pm_cpu_gate_cml_2_4/CLK`
139			`Logical resource: or1200_pm/pm_cpu_gate_cml_2_4/CK`
140			`Location pin: OLOGIC_X2Y162.CLK`
141			`Clock network: clk_i_cml_2_BUFGP`
142			`--------------------------------------------------------------------------------`
143			`Slack: 0.000ns (period - min period limit)`
144			`Period: 1.000ns`
145			`Min period limit: 1.000ns (1000.000MHz) (Tockper)`
146			`Physical resource: or1200_pm/pm_cpu_gate_cml_2_4/CLK`
147			`Logical resource: or1200_pm/pm_cpu_gate_cml_2_4/CK`
148			`Location pin: OLOGIC_X2Y162.CLK`
149			`Clock network: clk_i_cml_2_BUFGP`
150			`--------------------------------------------------------------------------------`
151
152			`================================================================================`
153			`Timing constraint: TS_clk_i_clk_i_cml_2_ERROR = MAXDELAY FROM TIMEGRP "clk_i"`
154			`TO TIMEGRP "clk_i_cml_2" 1 ns DATAPATHONLY;`
155
156
157
158			`--------------------------------------------------------------------------------`
159
160			`================================================================================`
161			`Timing constraint: TS_clk_i_cml_1_clk_i_ERROR = MAXDELAY FROM TIMEGRP`
162			`"clk_i_cml_1" TO TIMEGRP "clk_i" 1 ns DATAPATHONLY;`
163
164
165
166			`--------------------------------------------------------------------------------`
167
168			`================================================================================`
169			`Timing constraint: TS_clk_i_cml_2_clk_i_cml_1_ERROR = MAXDELAY FROM TIMEGRP`
170			`"clk_i_cml_2" TO TIMEGRP "clk_i_cml_1" 1 ns DATAPATHONLY;`
171
172
173
174			`--------------------------------------------------------------------------------`
175
176
177			`1 constraint not met.`
178
179
180			`Data Sheet report:`
181			`-----------------`
182			`No constraints were found to generate data for the Data Sheet Report section.`
183			`Use the Advanced Analysis (-a) option or generate global constraints for each`
184			`clock, its pad to setup and clock to pad paths, and a pad to pad constraint.`
185
186			`Timing summary:`
187			`---------------`
188
189			`Timing errors: 3242 Score: 923522 (Setup/Max: 0, Hold: 0, Component Switching Limit: 923522)`
190
191			`Constraints cover 0 paths, 0 nets, and 0 connections`
192
193			`Design statistics:`
194			`Minimum period: 2.400ns{1} (Maximum frequency: 416.667MHz)`
195
196
197			`------------------------------------Footnotes-----------------------------------`
198			`1) The minimum period statistic assumes all single cycle delays.`
199
200			`Analysis completed Thu Oct 21 15:32:58 2010`
201			`--------------------------------------------------------------------------------`
202
203			`Trace Settings:`
204			`-------------------------`
205			`Trace Settings`
206
207			`Peak Memory Usage: 317 MB`
208
209
210