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[/] [or1200_hp/] [trunk/] [ise/] [ise_cm3_top/] [or1200_top_cm3_top.twr] - Blame information for rev 2

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--------------------------------------------------------------------------------
Release 11.1 Trace  (nt)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
C:\Xilinx\11.1\ISE\bin\nt\unwrapped\trce.exe -ise
C:/EDAptability/coremultiplier/reference/or1200_new/ise/ise_or1200_cm3_top/ise_or1200_cm3_top/ise_or1200_cm3_top.ise
-intstyle ise -v 3 -s 1 -fastpaths -xml or1200_top_cm3_top.twx
or1200_top_cm3_top.ncd -o or1200_top_cm3_top.twr or1200_top_cm3_top.pcf -ucf
or1200_top_cm3_top.ucf
 
Design file:              or1200_top_cm3_top.ncd
Physical constraint file: or1200_top_cm3_top.pcf
Device,package,speed:     xc5vlx50,ff676,-1 (PRODUCTION 1.64 2009-03-03, STEPPING level 0)
Report level:             verbose report
 
Environment Variable      Effect
--------------------      ------
NONE                      No environment variables were set
--------------------------------------------------------------------------------
 
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
   a 50 Ohm transmission line loading model.  For the details of this model,
   and for more information on accounting for different loading conditions,
   please see the device datasheet.
 
================================================================================
Timing constraint: TS_clk_i = PERIOD TIMEGRP "clk_i" 4.88 ns HIGH 50%;
 
 115046 paths analyzed, 14528 endpoints analyzed, 715 failing endpoints
 715 timing errors detected. (715 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is   5.818ns.
--------------------------------------------------------------------------------
Slack (setup path):     -0.938ns (requirement - (data path - clock path skew + uncertainty))
  Source:               or1200_top_cm3i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM18.SDP (RAM)
  Destination:          or1200_top_cm3i/or1200_cpu/or1200_freeze/icpu_ack_i_cml_1 (FF)
  Requirement:          4.880ns
  Data Path Delay:      5.398ns (Levels of Logic = 3)
  Clock Path Skew:      -0.385ns (1.135 - 1.520)
  Source Clock:         clk_i_BUFGP rising at 0.000ns
  Destination Clock:    clk_i_BUFGP rising at 4.880ns
  Clock Uncertainty:    0.035ns
 
  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns
 
  Maximum Data Path: or1200_top_cm3i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM18.SDP to or1200_top_cm3i/or1200_cpu/or1200_freeze/icpu_ack_i_cml_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    RAMB36_X0Y16.DOBDOL3 Trcko_DORB            2.180   or1200_top_cm3i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM18.SDP
                                                       or1200_top_cm3i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM18.SDP
    SLICE_X10Y76.A4      net (fanout=1)        1.045   or1200_top_cm3i/or1200_ic_top/tag<2>
    SLICE_X10Y76.COUT    Topcya                0.499   or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>
                                                       or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_lut<0>
                                                       or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>
    SLICE_X10Y77.CIN     net (fanout=1)        0.000   or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>
    SLICE_X10Y77.CMUX    Tcinc                 0.358   or1200_top_cm3i/or1200_ic_top/tagcomp_miss
                                                       or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_cy<6>
    SLICE_X31Y76.C5      net (fanout=3)        1.287   or1200_top_cm3i/or1200_ic_top/tagcomp_miss
    SLICE_X31Y76.CLK     Tas                   0.029   or1200_top_cm3i/or1200_cpu/or1200_freeze/icpu_ack_i_cml_2
                                                       or1200_top_cm3i/or1200_ic_top/icqmem_ack_o
                                                       or1200_top_cm3i/or1200_cpu/or1200_freeze/icpu_ack_i_cml_1
    -------------------------------------------------  ---------------------------
    Total                                      5.398ns (3.066ns logic, 2.332ns route)
                                                       (56.8% logic, 43.2% route)
 
--------------------------------------------------------------------------------
Slack (setup path):     -0.884ns (requirement - (data path - clock path skew + uncertainty))
  Source:               or1200_top_cm3i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM18.SDP (RAM)
  Destination:          or1200_top_cm3i/or1200_cpu/or1200_genpc/icpu_rty_i_cml_1 (FF)
  Requirement:          4.880ns
  Data Path Delay:      5.343ns (Levels of Logic = 3)
  Clock Path Skew:      -0.386ns (1.134 - 1.520)
  Source Clock:         clk_i_BUFGP rising at 0.000ns
  Destination Clock:    clk_i_BUFGP rising at 4.880ns
  Clock Uncertainty:    0.035ns
 
  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns
 
  Maximum Data Path: or1200_top_cm3i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM18.SDP to or1200_top_cm3i/or1200_cpu/or1200_genpc/icpu_rty_i_cml_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    RAMB36_X0Y16.DOBDOL3 Trcko_DORB            2.180   or1200_top_cm3i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM18.SDP
                                                       or1200_top_cm3i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM18.SDP
    SLICE_X10Y76.A4      net (fanout=1)        1.045   or1200_top_cm3i/or1200_ic_top/tag<2>
    SLICE_X10Y76.COUT    Topcya                0.499   or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>
                                                       or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_lut<0>
                                                       or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>
    SLICE_X10Y77.CIN     net (fanout=1)        0.000   or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>
    SLICE_X10Y77.CMUX    Tcinc                 0.358   or1200_top_cm3i/or1200_ic_top/tagcomp_miss
                                                       or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_cy<6>
    SLICE_X32Y75.B6      net (fanout=3)        1.258   or1200_top_cm3i/or1200_ic_top/tagcomp_miss
    SLICE_X32Y75.CLK     Tas                   0.003   or1200_top_cm3i/or1200_ic_top/or1200_ic_fsm/biudata_error_cml_2
                                                       or1200_top_cm3i/or1200_immu_top/icpu_rty_o1
                                                       or1200_top_cm3i/or1200_cpu/or1200_genpc/icpu_rty_i_cml_1
    -------------------------------------------------  ---------------------------
    Total                                      5.343ns (3.040ns logic, 2.303ns route)
                                                       (56.9% logic, 43.1% route)
 
--------------------------------------------------------------------------------
Slack (setup path):     -0.776ns (requirement - (data path - clock path skew + uncertainty))
  Source:               or1200_top_cm3i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM18.SDP (RAM)
  Destination:          or1200_top_cm3i/or1200_cpu/or1200_freeze/icpu_ack_i_cml_1 (FF)
  Requirement:          4.880ns
  Data Path Delay:      5.236ns (Levels of Logic = 3)
  Clock Path Skew:      -0.385ns (1.135 - 1.520)
  Source Clock:         clk_i_BUFGP rising at 0.000ns
  Destination Clock:    clk_i_BUFGP rising at 4.880ns
  Clock Uncertainty:    0.035ns
 
  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns
 
  Maximum Data Path: or1200_top_cm3i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM18.SDP to or1200_top_cm3i/or1200_cpu/or1200_freeze/icpu_ack_i_cml_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    RAMB36_X0Y16.DOBDOL2 Trcko_DORB            2.180   or1200_top_cm3i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM18.SDP
                                                       or1200_top_cm3i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM18.SDP
    SLICE_X10Y76.A5      net (fanout=1)        0.883   or1200_top_cm3i/or1200_ic_top/tag<1>
    SLICE_X10Y76.COUT    Topcya                0.499   or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>
                                                       or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_lut<0>
                                                       or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>
    SLICE_X10Y77.CIN     net (fanout=1)        0.000   or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>
    SLICE_X10Y77.CMUX    Tcinc                 0.358   or1200_top_cm3i/or1200_ic_top/tagcomp_miss
                                                       or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_cy<6>
    SLICE_X31Y76.C5      net (fanout=3)        1.287   or1200_top_cm3i/or1200_ic_top/tagcomp_miss
    SLICE_X31Y76.CLK     Tas                   0.029   or1200_top_cm3i/or1200_cpu/or1200_freeze/icpu_ack_i_cml_2
                                                       or1200_top_cm3i/or1200_ic_top/icqmem_ack_o
                                                       or1200_top_cm3i/or1200_cpu/or1200_freeze/icpu_ack_i_cml_1
    -------------------------------------------------  ---------------------------
    Total                                      5.236ns (3.066ns logic, 2.170ns route)
                                                       (58.6% logic, 41.4% route)
 
--------------------------------------------------------------------------------
 
Hold Paths: TS_clk_i = PERIOD TIMEGRP "clk_i" 4.88 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack (hold path):      0.342ns (requirement - (clock path skew + uncertainty - data path))
  Source:               or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2_25 (FF)
  Destination:          or1200_top_cm3i/or1200_immu_top/icpu_vpn_r_25 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.353ns (Levels of Logic = 0)
  Clock Path Skew:      0.011ns (0.159 - 0.148)
  Source Clock:         clk_i_BUFGP rising at 4.880ns
  Destination Clock:    clk_i_BUFGP rising at 4.880ns
  Clock Uncertainty:    0.000ns
 
  Minimum Data Path: or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2_25 to or1200_top_cm3i/or1200_immu_top/icpu_vpn_r_25
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X40Y82.BQ      Tcko                  0.433   or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2<27>
                                                       or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2_25
    SLICE_X41Y82.AX      net (fanout=1)        0.149   or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2<25>
    SLICE_X41Y82.CLK     Tckdi       (-Th)     0.229   or1200_top_cm3i/or1200_immu_top/icpu_vpn_r<28>
                                                       or1200_top_cm3i/or1200_immu_top/icpu_vpn_r_25
    -------------------------------------------------  ---------------------------
    Total                                      0.353ns (0.204ns logic, 0.149ns route)
                                                       (57.8% logic, 42.2% route)
 
--------------------------------------------------------------------------------
Slack (hold path):      0.349ns (requirement - (clock path skew + uncertainty - data path))
  Source:               or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2_21 (FF)
  Destination:          or1200_top_cm3i/or1200_immu_top/icpu_vpn_r_21 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.474ns (Levels of Logic = 0)
  Clock Path Skew:      0.125ns (1.277 - 1.152)
  Source Clock:         clk_i_BUFGP rising at 4.880ns
  Destination Clock:    clk_i_BUFGP rising at 4.880ns
  Clock Uncertainty:    0.000ns
 
  Minimum Data Path: or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2_21 to or1200_top_cm3i/or1200_immu_top/icpu_vpn_r_21
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X41Y79.BQ      Tcko                  0.414   or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2<23>
                                                       or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2_21
    SLICE_X41Y81.AX      net (fanout=1)        0.289   or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2<21>
    SLICE_X41Y81.CLK     Tckdi       (-Th)     0.229   or1200_top_cm3i/or1200_immu_top/icpu_vpn_r<24>
                                                       or1200_top_cm3i/or1200_immu_top/icpu_vpn_r_21
    -------------------------------------------------  ---------------------------
    Total                                      0.474ns (0.185ns logic, 0.289ns route)
                                                       (39.0% logic, 61.0% route)
 
--------------------------------------------------------------------------------
Slack (hold path):      0.351ns (requirement - (clock path skew + uncertainty - data path))
  Source:               or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2_27 (FF)
  Destination:          or1200_top_cm3i/or1200_immu_top/icpu_vpn_r_27 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.362ns (Levels of Logic = 0)
  Clock Path Skew:      0.011ns (0.159 - 0.148)
  Source Clock:         clk_i_BUFGP rising at 4.880ns
  Destination Clock:    clk_i_BUFGP rising at 4.880ns
  Clock Uncertainty:    0.000ns
 
  Minimum Data Path: or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2_27 to or1200_top_cm3i/or1200_immu_top/icpu_vpn_r_27
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X40Y82.DQ      Tcko                  0.433   or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2<27>
                                                       or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2_27
    SLICE_X41Y82.CX      net (fanout=1)        0.147   or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2<27>
    SLICE_X41Y82.CLK     Tckdi       (-Th)     0.218   or1200_top_cm3i/or1200_immu_top/icpu_vpn_r<28>
                                                       or1200_top_cm3i/or1200_immu_top/icpu_vpn_r_27
    -------------------------------------------------  ---------------------------
    Total                                      0.362ns (0.215ns logic, 0.147ns route)
                                                       (59.4% logic, 40.6% route)
 
--------------------------------------------------------------------------------
 
Component Switching Limit Checks: TS_clk_i = PERIOD TIMEGRP "clk_i" 4.88 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 2.480ns (period - (min high pulse limit / (high pulse / period)))
  Period: 4.880ns
  High pulse: 2.440ns
  High pulse limit: 1.200ns (Tospwh)
  Physical resource: or1200_top_cm3i/iwb_biu/wb_sel_o<0>/SR
  Logical resource: or1200_top_cm3i/iwb_biu/wb_sel_o_0/SR
  Location pin: OLOGIC_X2Y54.SR
  Clock network: rst_i_IBUF
--------------------------------------------------------------------------------
Slack: 2.480ns (period - (min high pulse limit / (high pulse / period)))
  Period: 4.880ns
  High pulse: 2.440ns
  High pulse limit: 1.200ns (Tospwh)
  Physical resource: or1200_top_cm3i/iwb_biu/wb_sel_o_0_3/SR
  Logical resource: or1200_top_cm3i/iwb_biu/wb_sel_o_0_3/SR
  Location pin: OLOGIC_X0Y43.SR
  Clock network: rst_i_IBUF
--------------------------------------------------------------------------------
Slack: 2.480ns (period - (min high pulse limit / (high pulse / period)))
  Period: 4.880ns
  High pulse: 2.440ns
  High pulse limit: 1.200ns (Tospwh)
  Physical resource: or1200_top_cm3i/iwb_biu/wb_sel_o_0_2/SR
  Logical resource: or1200_top_cm3i/iwb_biu/wb_sel_o_0_2/SR
  Location pin: OLOGIC_X2Y64.SR
  Clock network: rst_i_IBUF
--------------------------------------------------------------------------------
 
 
1 constraint not met.
 
 
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
 
Clock to Setup on destination clock clk_i
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk_i          |    5.818|         |         |         |
---------------+---------+---------+---------+---------+
 
 
Timing summary:
---------------
 
Timing errors: 715  Score: 177497  (Setup/Max: 177497, Hold: 0)
 
Constraints cover 115046 paths, 0 nets, and 27301 connections
 
Design statistics:
   Minimum period:   5.818ns{1}   (Maximum frequency: 171.880MHz)
 
 
------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.
 
Analysis completed Thu Oct 21 15:44:55 2010
--------------------------------------------------------------------------------
 
Trace Settings:
-------------------------
Trace Settings
 
Peak Memory Usage: 336 MB
 
 
 

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[/] [or1200_hp/] [trunk/] [ise/] [ise_cm3_top/] [or1200_top_cm3_top.twr] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	tobil	`--------------------------------------------------------------------------------`
2			`Release 11.1 Trace (nt)`
3			`Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.`
4
5			`C:\Xilinx\11.1\ISE\bin\nt\unwrapped\trce.exe -ise`
6			`C:/EDAptability/coremultiplier/reference/or1200_new/ise/ise_or1200_cm3_top/ise_or1200_cm3_top/ise_or1200_cm3_top.ise`
7			`-intstyle ise -v 3 -s 1 -fastpaths -xml or1200_top_cm3_top.twx`
8			`or1200_top_cm3_top.ncd -o or1200_top_cm3_top.twr or1200_top_cm3_top.pcf -ucf`
9			`or1200_top_cm3_top.ucf`
10
11			`Design file: or1200_top_cm3_top.ncd`
12			`Physical constraint file: or1200_top_cm3_top.pcf`
13			`Device,package,speed: xc5vlx50,ff676,-1 (PRODUCTION 1.64 2009-03-03, STEPPING level 0)`
14			`Report level: verbose report`
15
16			`Environment Variable Effect`
17			`-------------------- ------`
18			`NONE No environment variables were set`
19			`--------------------------------------------------------------------------------`
20
21			`INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths`
22			`option. All paths that are not constrained will be reported in the`
23			`unconstrained paths section(s) of the report.`
24			`INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on`
25			`a 50 Ohm transmission line loading model. For the details of this model,`
26			`and for more information on accounting for different loading conditions,`
27			`please see the device datasheet.`
28
29			`================================================================================`
30			`Timing constraint: TS_clk_i = PERIOD TIMEGRP "clk_i" 4.88 ns HIGH 50%;`
31
32			`115046 paths analyzed, 14528 endpoints analyzed, 715 failing endpoints`
33			`715 timing errors detected. (715 setup errors, 0 hold errors, 0 component switching limit errors)`
34			`Minimum period is 5.818ns.`
35			`--------------------------------------------------------------------------------`
36			`Slack (setup path): -0.938ns (requirement - (data path - clock path skew + uncertainty))`
37			`Source: or1200_top_cm3i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM18.SDP (RAM)`
38			`Destination: or1200_top_cm3i/or1200_cpu/or1200_freeze/icpu_ack_i_cml_1 (FF)`
39			`Requirement: 4.880ns`
40			`Data Path Delay: 5.398ns (Levels of Logic = 3)`
41			`Clock Path Skew: -0.385ns (1.135 - 1.520)`
42			`Source Clock: clk_i_BUFGP rising at 0.000ns`
43			`Destination Clock: clk_i_BUFGP rising at 4.880ns`
44			`Clock Uncertainty: 0.035ns`
45
46			`Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE`
47			`Total System Jitter (TSJ): 0.070ns`
48			`Total Input Jitter (TIJ): 0.000ns`
49			`Discrete Jitter (DJ): 0.000ns`
50			`Phase Error (PE): 0.000ns`
51
52			`Maximum Data Path: or1200_top_cm3i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM18.SDP to or1200_top_cm3i/or1200_cpu/or1200_freeze/icpu_ack_i_cml_1`
53			`Location Delay type Delay(ns) Physical Resource`
54			`Logical Resource(s)`
55			`------------------------------------------------- -------------------`
56			`RAMB36_X0Y16.DOBDOL3 Trcko_DORB 2.180 or1200_top_cm3i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM18.SDP`
57			`or1200_top_cm3i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM18.SDP`
58			`SLICE_X10Y76.A4 net (fanout=1) 1.045 or1200_top_cm3i/or1200_ic_top/tag<2>`
59			`SLICE_X10Y76.COUT Topcya 0.499 or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>`
60			`or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_lut<0>`
61			`or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>`
62			`SLICE_X10Y77.CIN net (fanout=1) 0.000 or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>`
63			`SLICE_X10Y77.CMUX Tcinc 0.358 or1200_top_cm3i/or1200_ic_top/tagcomp_miss`
64			`or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_cy<6>`
65			`SLICE_X31Y76.C5 net (fanout=3) 1.287 or1200_top_cm3i/or1200_ic_top/tagcomp_miss`
66			`SLICE_X31Y76.CLK Tas 0.029 or1200_top_cm3i/or1200_cpu/or1200_freeze/icpu_ack_i_cml_2`
67			`or1200_top_cm3i/or1200_ic_top/icqmem_ack_o`
68			`or1200_top_cm3i/or1200_cpu/or1200_freeze/icpu_ack_i_cml_1`
69			`------------------------------------------------- ---------------------------`
70			`Total 5.398ns (3.066ns logic, 2.332ns route)`
71			`(56.8% logic, 43.2% route)`
72
73			`--------------------------------------------------------------------------------`
74			`Slack (setup path): -0.884ns (requirement - (data path - clock path skew + uncertainty))`
75			`Source: or1200_top_cm3i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM18.SDP (RAM)`
76			`Destination: or1200_top_cm3i/or1200_cpu/or1200_genpc/icpu_rty_i_cml_1 (FF)`
77			`Requirement: 4.880ns`
78			`Data Path Delay: 5.343ns (Levels of Logic = 3)`
79			`Clock Path Skew: -0.386ns (1.134 - 1.520)`
80			`Source Clock: clk_i_BUFGP rising at 0.000ns`
81			`Destination Clock: clk_i_BUFGP rising at 4.880ns`
82			`Clock Uncertainty: 0.035ns`
83
84			`Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE`
85			`Total System Jitter (TSJ): 0.070ns`
86			`Total Input Jitter (TIJ): 0.000ns`
87			`Discrete Jitter (DJ): 0.000ns`
88			`Phase Error (PE): 0.000ns`
89
90			`Maximum Data Path: or1200_top_cm3i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM18.SDP to or1200_top_cm3i/or1200_cpu/or1200_genpc/icpu_rty_i_cml_1`
91			`Location Delay type Delay(ns) Physical Resource`
92			`Logical Resource(s)`
93			`------------------------------------------------- -------------------`
94			`RAMB36_X0Y16.DOBDOL3 Trcko_DORB 2.180 or1200_top_cm3i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM18.SDP`
95			`or1200_top_cm3i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM18.SDP`
96			`SLICE_X10Y76.A4 net (fanout=1) 1.045 or1200_top_cm3i/or1200_ic_top/tag<2>`
97			`SLICE_X10Y76.COUT Topcya 0.499 or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>`
98			`or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_lut<0>`
99			`or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>`
100			`SLICE_X10Y77.CIN net (fanout=1) 0.000 or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>`
101			`SLICE_X10Y77.CMUX Tcinc 0.358 or1200_top_cm3i/or1200_ic_top/tagcomp_miss`
102			`or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_cy<6>`
103			`SLICE_X32Y75.B6 net (fanout=3) 1.258 or1200_top_cm3i/or1200_ic_top/tagcomp_miss`
104			`SLICE_X32Y75.CLK Tas 0.003 or1200_top_cm3i/or1200_ic_top/or1200_ic_fsm/biudata_error_cml_2`
105			`or1200_top_cm3i/or1200_immu_top/icpu_rty_o1`
106			`or1200_top_cm3i/or1200_cpu/or1200_genpc/icpu_rty_i_cml_1`
107			`------------------------------------------------- ---------------------------`
108			`Total 5.343ns (3.040ns logic, 2.303ns route)`
109			`(56.9% logic, 43.1% route)`
110
111			`--------------------------------------------------------------------------------`
112			`Slack (setup path): -0.776ns (requirement - (data path - clock path skew + uncertainty))`
113			`Source: or1200_top_cm3i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM18.SDP (RAM)`
114			`Destination: or1200_top_cm3i/or1200_cpu/or1200_freeze/icpu_ack_i_cml_1 (FF)`
115			`Requirement: 4.880ns`
116			`Data Path Delay: 5.236ns (Levels of Logic = 3)`
117			`Clock Path Skew: -0.385ns (1.135 - 1.520)`
118			`Source Clock: clk_i_BUFGP rising at 0.000ns`
119			`Destination Clock: clk_i_BUFGP rising at 4.880ns`
120			`Clock Uncertainty: 0.035ns`
121
122			`Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE`
123			`Total System Jitter (TSJ): 0.070ns`
124			`Total Input Jitter (TIJ): 0.000ns`
125			`Discrete Jitter (DJ): 0.000ns`
126			`Phase Error (PE): 0.000ns`
127
128			`Maximum Data Path: or1200_top_cm3i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM18.SDP to or1200_top_cm3i/or1200_cpu/or1200_freeze/icpu_ack_i_cml_1`
129			`Location Delay type Delay(ns) Physical Resource`
130			`Logical Resource(s)`
131			`------------------------------------------------- -------------------`
132			`RAMB36_X0Y16.DOBDOL2 Trcko_DORB 2.180 or1200_top_cm3i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM18.SDP`
133			`or1200_top_cm3i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM18.SDP`
134			`SLICE_X10Y76.A5 net (fanout=1) 0.883 or1200_top_cm3i/or1200_ic_top/tag<1>`
135			`SLICE_X10Y76.COUT Topcya 0.499 or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>`
136			`or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_lut<0>`
137			`or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>`
138			`SLICE_X10Y77.CIN net (fanout=1) 0.000 or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>`
139			`SLICE_X10Y77.CMUX Tcinc 0.358 or1200_top_cm3i/or1200_ic_top/tagcomp_miss`
140			`or1200_top_cm3i/or1200_ic_top/tagcomp_miss_or0000_wg_cy<6>`
141			`SLICE_X31Y76.C5 net (fanout=3) 1.287 or1200_top_cm3i/or1200_ic_top/tagcomp_miss`
142			`SLICE_X31Y76.CLK Tas 0.029 or1200_top_cm3i/or1200_cpu/or1200_freeze/icpu_ack_i_cml_2`
143			`or1200_top_cm3i/or1200_ic_top/icqmem_ack_o`
144			`or1200_top_cm3i/or1200_cpu/or1200_freeze/icpu_ack_i_cml_1`
145			`------------------------------------------------- ---------------------------`
146			`Total 5.236ns (3.066ns logic, 2.170ns route)`
147			`(58.6% logic, 41.4% route)`
148
149			`--------------------------------------------------------------------------------`
150
151			`Hold Paths: TS_clk_i = PERIOD TIMEGRP "clk_i" 4.88 ns HIGH 50%;`
152			`--------------------------------------------------------------------------------`
153			`Slack (hold path): 0.342ns (requirement - (clock path skew + uncertainty - data path))`
154			`Source: or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2_25 (FF)`
155			`Destination: or1200_top_cm3i/or1200_immu_top/icpu_vpn_r_25 (FF)`
156			`Requirement: 0.000ns`
157			`Data Path Delay: 0.353ns (Levels of Logic = 0)`
158			`Clock Path Skew: 0.011ns (0.159 - 0.148)`
159			`Source Clock: clk_i_BUFGP rising at 4.880ns`
160			`Destination Clock: clk_i_BUFGP rising at 4.880ns`
161			`Clock Uncertainty: 0.000ns`
162
163			`Minimum Data Path: or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2_25 to or1200_top_cm3i/or1200_immu_top/icpu_vpn_r_25`
164			`Location Delay type Delay(ns) Physical Resource`
165			`Logical Resource(s)`
166			`------------------------------------------------- -------------------`
167			`SLICE_X40Y82.BQ Tcko 0.433 or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2<27>`
168			`or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2_25`
169			`SLICE_X41Y82.AX net (fanout=1) 0.149 or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2<25>`
170			`SLICE_X41Y82.CLK Tckdi (-Th) 0.229 or1200_top_cm3i/or1200_immu_top/icpu_vpn_r<28>`
171			`or1200_top_cm3i/or1200_immu_top/icpu_vpn_r_25`
172			`------------------------------------------------- ---------------------------`
173			`Total 0.353ns (0.204ns logic, 0.149ns route)`
174			`(57.8% logic, 42.2% route)`
175
176			`--------------------------------------------------------------------------------`
177			`Slack (hold path): 0.349ns (requirement - (clock path skew + uncertainty - data path))`
178			`Source: or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2_21 (FF)`
179			`Destination: or1200_top_cm3i/or1200_immu_top/icpu_vpn_r_21 (FF)`
180			`Requirement: 0.000ns`
181			`Data Path Delay: 0.474ns (Levels of Logic = 0)`
182			`Clock Path Skew: 0.125ns (1.277 - 1.152)`
183			`Source Clock: clk_i_BUFGP rising at 4.880ns`
184			`Destination Clock: clk_i_BUFGP rising at 4.880ns`
185			`Clock Uncertainty: 0.000ns`
186
187			`Minimum Data Path: or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2_21 to or1200_top_cm3i/or1200_immu_top/icpu_vpn_r_21`
188			`Location Delay type Delay(ns) Physical Resource`
189			`Logical Resource(s)`
190			`------------------------------------------------- -------------------`
191			`SLICE_X41Y79.BQ Tcko 0.414 or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2<23>`
192			`or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2_21`
193			`SLICE_X41Y81.AX net (fanout=1) 0.289 or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2<21>`
194			`SLICE_X41Y81.CLK Tckdi (-Th) 0.229 or1200_top_cm3i/or1200_immu_top/icpu_vpn_r<24>`
195			`or1200_top_cm3i/or1200_immu_top/icpu_vpn_r_21`
196			`------------------------------------------------- ---------------------------`
197			`Total 0.474ns (0.185ns logic, 0.289ns route)`
198			`(39.0% logic, 61.0% route)`
199
200			`--------------------------------------------------------------------------------`
201			`Slack (hold path): 0.351ns (requirement - (clock path skew + uncertainty - data path))`
202			`Source: or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2_27 (FF)`
203			`Destination: or1200_top_cm3i/or1200_immu_top/icpu_vpn_r_27 (FF)`
204			`Requirement: 0.000ns`
205			`Data Path Delay: 0.362ns (Levels of Logic = 0)`
206			`Clock Path Skew: 0.011ns (0.159 - 0.148)`
207			`Source Clock: clk_i_BUFGP rising at 4.880ns`
208			`Destination Clock: clk_i_BUFGP rising at 4.880ns`
209			`Clock Uncertainty: 0.000ns`
210
211			`Minimum Data Path: or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2_27 to or1200_top_cm3i/or1200_immu_top/icpu_vpn_r_27`
212			`Location Delay type Delay(ns) Physical Resource`
213			`Logical Resource(s)`
214			`------------------------------------------------- -------------------`
215			`SLICE_X40Y82.DQ Tcko 0.433 or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2<27>`
216			`or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2_27`
217			`SLICE_X41Y82.CX net (fanout=1) 0.147 or1200_top_cm3i/or1200_immu_top/icpu_adr_i_cml_2<27>`
218			`SLICE_X41Y82.CLK Tckdi (-Th) 0.218 or1200_top_cm3i/or1200_immu_top/icpu_vpn_r<28>`
219			`or1200_top_cm3i/or1200_immu_top/icpu_vpn_r_27`
220			`------------------------------------------------- ---------------------------`
221			`Total 0.362ns (0.215ns logic, 0.147ns route)`
222			`(59.4% logic, 40.6% route)`
223
224			`--------------------------------------------------------------------------------`
225
226			`Component Switching Limit Checks: TS_clk_i = PERIOD TIMEGRP "clk_i" 4.88 ns HIGH 50%;`
227			`--------------------------------------------------------------------------------`
228			`Slack: 2.480ns (period - (min high pulse limit / (high pulse / period)))`
229			`Period: 4.880ns`
230			`High pulse: 2.440ns`
231			`High pulse limit: 1.200ns (Tospwh)`
232			`Physical resource: or1200_top_cm3i/iwb_biu/wb_sel_o<0>/SR`
233			`Logical resource: or1200_top_cm3i/iwb_biu/wb_sel_o_0/SR`
234			`Location pin: OLOGIC_X2Y54.SR`
235			`Clock network: rst_i_IBUF`
236			`--------------------------------------------------------------------------------`
237			`Slack: 2.480ns (period - (min high pulse limit / (high pulse / period)))`
238			`Period: 4.880ns`
239			`High pulse: 2.440ns`
240			`High pulse limit: 1.200ns (Tospwh)`
241			`Physical resource: or1200_top_cm3i/iwb_biu/wb_sel_o_0_3/SR`
242			`Logical resource: or1200_top_cm3i/iwb_biu/wb_sel_o_0_3/SR`
243			`Location pin: OLOGIC_X0Y43.SR`
244			`Clock network: rst_i_IBUF`
245			`--------------------------------------------------------------------------------`
246			`Slack: 2.480ns (period - (min high pulse limit / (high pulse / period)))`
247			`Period: 4.880ns`
248			`High pulse: 2.440ns`
249			`High pulse limit: 1.200ns (Tospwh)`
250			`Physical resource: or1200_top_cm3i/iwb_biu/wb_sel_o_0_2/SR`
251			`Logical resource: or1200_top_cm3i/iwb_biu/wb_sel_o_0_2/SR`
252			`Location pin: OLOGIC_X2Y64.SR`
253			`Clock network: rst_i_IBUF`
254			`--------------------------------------------------------------------------------`
255
256
257			`1 constraint not met.`
258
259
260			`Data Sheet report:`
261			`-----------------`
262			`All values displayed in nanoseconds (ns)`
263
264			`Clock to Setup on destination clock clk_i`
265			`---------------+---------+---------+---------+---------+`
266			`\| Src:Rise\| Src:Fall\| Src:Rise\| Src:Fall\|`
267			`Source Clock \|Dest:Rise\|Dest:Rise\|Dest:Fall\|Dest:Fall\|`
268			`---------------+---------+---------+---------+---------+`
269			`clk_i \| 5.818\| \| \| \|`
270			`---------------+---------+---------+---------+---------+`
271
272
273			`Timing summary:`
274			`---------------`
275
276			`Timing errors: 715 Score: 177497 (Setup/Max: 177497, Hold: 0)`
277
278			`Constraints cover 115046 paths, 0 nets, and 27301 connections`
279
280			`Design statistics:`
281			`Minimum period: 5.818ns{1} (Maximum frequency: 171.880MHz)`
282
283
284			`------------------------------------Footnotes-----------------------------------`
285			`1) The minimum period statistic assumes all single cycle delays.`
286
287			`Analysis completed Thu Oct 21 15:44:55 2010`
288			`--------------------------------------------------------------------------------`
289
290			`Trace Settings:`
291			`-------------------------`
292			`Trace Settings`
293
294			`Peak Memory Usage: 336 MB`
295
296
297