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tobil |
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Release 11.1 Trace (nt)
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Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
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C:\Xilinx\11.1\ISE\bin\nt\unwrapped\trce.exe -ise
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C:/EDAptability/coremultiplier/reference/or1200_new/ise/ise_or1200_cm4/ise_or1200_cm4/ise_or1200_cm4.ise
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-intstyle ise -v 3 -s 1 -fastpaths -xml or1200_top_cm4.twx or1200_top_cm4.ncd
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-o or1200_top_cm4.twr or1200_top_cm4.pcf -ucf or1200_top_cm4.ucf
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Design file: or1200_top_cm4.ncd
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Physical constraint file: or1200_top_cm4.pcf
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Device,package,speed: xc5vlx50,ff676,-1 (PRODUCTION 1.64 2009-03-03, STEPPING level 0)
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Report level: verbose report
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Environment Variable Effect
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-------------------- ------
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NONE No environment variables were set
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--------------------------------------------------------------------------------
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WARNING:Timing:3223 - Timing constraint TS_clk_i_clk_i_cml_2_ERROR = MAXDELAY
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FROM TIMEGRP "clk_i" TO TIMEGRP "clk_i_cml_2" 1 ns DATAPATHONLY;
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ignored during timing analysis.
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WARNING:Timing:3223 - Timing constraint TS_clk_i_cml_1_clk_i_cml_3_ERROR =
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MAXDELAY FROM TIMEGRP "clk_i_cml_1" TO TIMEGRP "clk_i_cml_3" 1 ns
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DATAPATHONLY; ignored during timing analysis.
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WARNING:Timing:3223 - Timing constraint TS_clk_i_cml_2_clk_i_ERROR = MAXDELAY
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FROM TIMEGRP "clk_i_cml_2" TO TIMEGRP "clk_i" 1 ns DATAPATHONLY;
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ignored during timing analysis.
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WARNING:Timing:3223 - Timing constraint TS_clk_i_cml_3_clk_i_cml_1_ERROR =
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MAXDELAY FROM TIMEGRP "clk_i_cml_3" TO TIMEGRP "clk_i_cml_1" 1 ns
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DATAPATHONLY; ignored during timing analysis.
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WARNING:Timing:3223 - Timing constraint TS_clk_i_clk_i_cml_3_ERROR = MAXDELAY
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FROM TIMEGRP "clk_i" TO TIMEGRP "clk_i_cml_3" 1 ns DATAPATHONLY;
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ignored during timing analysis.
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WARNING:Timing:3223 - Timing constraint TS_clk_i_cml_1_clk_i_ERROR = MAXDELAY
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FROM TIMEGRP "clk_i_cml_1" TO TIMEGRP "clk_i" 1 ns DATAPATHONLY;
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ignored during timing analysis.
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WARNING:Timing:3223 - Timing constraint TS_clk_i_cml_2_clk_i_cml_1_ERROR =
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MAXDELAY FROM TIMEGRP "clk_i_cml_2" TO TIMEGRP "clk_i_cml_1" 1 ns
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DATAPATHONLY; ignored during timing analysis.
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WARNING:Timing:3223 - Timing constraint TS_clk_i_cml_3_clk_i_cml_2_ERROR =
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MAXDELAY FROM TIMEGRP "clk_i_cml_3" TO TIMEGRP "clk_i_cml_2" 1 ns
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DATAPATHONLY; ignored during timing analysis.
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INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
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option. All paths that are not constrained will be reported in the
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unconstrained paths section(s) of the report.
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INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
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a 50 Ohm transmission line loading model. For the details of this model,
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and for more information on accounting for different loading conditions,
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please see the device datasheet.
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================================================================================
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Timing constraint: TS_clk_i_ERROR = PERIOD TIMEGRP "clk_i" 1 ns HIGH 50%;
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3242 timing errors detected. (3242 component switching limit errors)
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Minimum period is 2.400ns.
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--------------------------------------------------------------------------------
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Component Switching Limit Checks: TS_clk_i_ERROR = PERIOD TIMEGRP "clk_i" 1 ns HIGH 50%;
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--------------------------------------------------------------------------------
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Slack: -1.400ns (period - (min high pulse limit / (high pulse / period)))
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Period: 1.000ns
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High pulse: 0.500ns
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High pulse limit: 1.200ns (Tospwh)
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Physical resource: or1200_du/dbg_ack_o/SR
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Logical resource: or1200_du/dbg_ack_o/SR
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Location pin: OLOGIC_X1Y74.SR
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Clock network: rst_i_IBUF
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--------------------------------------------------------------------------------
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Slack: -1.400ns (period - (min high pulse limit / (high pulse / period)))
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Period: 1.000ns
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High pulse: 0.500ns
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High pulse limit: 1.200ns (Tospwh)
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Physical resource: dwb_biu/wb_adr_o_10_1/SR
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Logical resource: dwb_biu/wb_adr_o_10_1/SR
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Location pin: OLOGIC_X0Y89.SR
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Clock network: rst_i_IBUF
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--------------------------------------------------------------------------------
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Slack: -1.400ns (period - (min high pulse limit / (high pulse / period)))
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Period: 1.000ns
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High pulse: 0.500ns
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High pulse limit: 1.200ns (Tospwh)
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Physical resource: dwb_biu/wb_adr_o_11_1/SR
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Logical resource: dwb_biu/wb_adr_o_11_1/SR
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Location pin: OLOGIC_X0Y51.SR
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Clock network: rst_i_IBUF
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--------------------------------------------------------------------------------
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================================================================================
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Timing constraint: TS_clk_i_cml_1_ERROR = PERIOD TIMEGRP "clk_i_cml_1" 1 ns
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HIGH 50%;
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Minimum period is 0.818ns.
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--------------------------------------------------------------------------------
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Component Switching Limit Checks: TS_clk_i_cml_1_ERROR = PERIOD TIMEGRP "clk_i_cml_1" 1 ns HIGH 50%;
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--------------------------------------------------------------------------------
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Slack: 0.182ns (period - (min low pulse limit / (low pulse / period)))
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Period: 1.000ns
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Low pulse: 0.500ns
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Low pulse limit: 0.409ns (Tcl)
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Physical resource: or1200_cpu/or1200_alu/result_csum_cml_1<3>/CLK
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Logical resource: or1200_cpu/or1200_alu/result_csum_cml_1_0/CK
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Location pin: SLICE_X4Y41.CLK
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Clock network: clk_i_cml_1_BUFGP
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--------------------------------------------------------------------------------
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Slack: 0.182ns (period - (min high pulse limit / (high pulse / period)))
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Period: 1.000ns
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High pulse: 0.500ns
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High pulse limit: 0.409ns (Tch)
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Physical resource: or1200_cpu/or1200_alu/result_csum_cml_1<3>/CLK
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Logical resource: or1200_cpu/or1200_alu/result_csum_cml_1_0/CK
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Location pin: SLICE_X4Y41.CLK
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Clock network: clk_i_cml_1_BUFGP
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--------------------------------------------------------------------------------
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Slack: 0.182ns (period - (min low pulse limit / (low pulse / period)))
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Period: 1.000ns
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Low pulse: 0.500ns
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Low pulse limit: 0.409ns (Tcl)
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Physical resource: or1200_cpu/or1200_alu/result_csum_cml_1<3>/CLK
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Logical resource: or1200_cpu/or1200_alu/result_csum_cml_1_1/CK
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Location pin: SLICE_X4Y41.CLK
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Clock network: clk_i_cml_1_BUFGP
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--------------------------------------------------------------------------------
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================================================================================
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Timing constraint: TS_clk_i_cml_2_ERROR = PERIOD TIMEGRP "clk_i_cml_2" 1 ns
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HIGH 50%;
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Minimum period is 0.818ns.
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--------------------------------------------------------------------------------
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Component Switching Limit Checks: TS_clk_i_cml_2_ERROR = PERIOD TIMEGRP "clk_i_cml_2" 1 ns HIGH 50%;
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--------------------------------------------------------------------------------
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Slack: 0.182ns (period - (min low pulse limit / (low pulse / period)))
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Period: 1.000ns
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Low pulse: 0.500ns
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Low pulse limit: 0.409ns (Tcl)
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Physical resource: or1200_cpu/or1200_rf/datab_saved_cml_2<7>/CLK
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Logical resource: or1200_cpu/or1200_rf/datab_saved_cml_2_4/CK
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Location pin: SLICE_X0Y28.CLK
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Clock network: clk_i_cml_2_BUFGP
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--------------------------------------------------------------------------------
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Slack: 0.182ns (period - (min high pulse limit / (high pulse / period)))
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Period: 1.000ns
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High pulse: 0.500ns
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High pulse limit: 0.409ns (Tch)
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Physical resource: or1200_cpu/or1200_rf/datab_saved_cml_2<7>/CLK
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Logical resource: or1200_cpu/or1200_rf/datab_saved_cml_2_4/CK
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Location pin: SLICE_X0Y28.CLK
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Clock network: clk_i_cml_2_BUFGP
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--------------------------------------------------------------------------------
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Slack: 0.182ns (period - (min low pulse limit / (low pulse / period)))
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Period: 1.000ns
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Low pulse: 0.500ns
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Low pulse limit: 0.409ns (Tcl)
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Physical resource: or1200_cpu/or1200_rf/datab_saved_cml_2<7>/CLK
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Logical resource: or1200_cpu/or1200_rf/datab_saved_cml_2_5/CK
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Location pin: SLICE_X0Y28.CLK
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Clock network: clk_i_cml_2_BUFGP
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--------------------------------------------------------------------------------
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================================================================================
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Timing constraint: TS_clk_i_cml_3_ERROR = PERIOD TIMEGRP "clk_i_cml_3" 1 ns
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HIGH 50%;
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Minimum period is 1.000ns.
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--------------------------------------------------------------------------------
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Component Switching Limit Checks: TS_clk_i_cml_3_ERROR = PERIOD TIMEGRP "clk_i_cml_3" 1 ns HIGH 50%;
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--------------------------------------------------------------------------------
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Slack: 0.000ns (period - (min low pulse limit / (low pulse / period)))
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Period: 1.000ns
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Low pulse: 0.500ns
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Low pulse limit: 0.500ns (Tockpwl)
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Physical resource: or1200_pic/intr_cml_3_1/CLK
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Logical resource: or1200_pic/intr_cml_3_1/CK
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Location pin: OLOGIC_X2Y89.CLK
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Clock network: clk_i_cml_3_BUFGP
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--------------------------------------------------------------------------------
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Slack: 0.000ns (period - (min high pulse limit / (high pulse / period)))
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Period: 1.000ns
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High pulse: 0.500ns
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High pulse limit: 0.500ns (Tockpwh)
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Physical resource: or1200_pic/intr_cml_3_1/CLK
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Logical resource: or1200_pic/intr_cml_3_1/CK
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Location pin: OLOGIC_X2Y89.CLK
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Clock network: clk_i_cml_3_BUFGP
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--------------------------------------------------------------------------------
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Slack: 0.000ns (period - min period limit)
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Period: 1.000ns
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Min period limit: 1.000ns (1000.000MHz) (Tockper)
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Physical resource: or1200_pic/intr_cml_3_1/CLK
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Logical resource: or1200_pic/intr_cml_3_1/CK
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Location pin: OLOGIC_X2Y89.CLK
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Clock network: clk_i_cml_3_BUFGP
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--------------------------------------------------------------------------------
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================================================================================
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Timing constraint: TS_clk_i_clk_i_cml_2_ERROR = MAXDELAY FROM TIMEGRP "clk_i"
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TO TIMEGRP "clk_i_cml_2" 1 ns DATAPATHONLY;
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--------------------------------------------------------------------------------
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================================================================================
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Timing constraint: TS_clk_i_cml_1_clk_i_cml_3_ERROR = MAXDELAY FROM TIMEGRP
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"clk_i_cml_1" TO TIMEGRP "clk_i_cml_3" 1 ns DATAPATHONLY;
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--------------------------------------------------------------------------------
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================================================================================
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Timing constraint: TS_clk_i_cml_2_clk_i_ERROR = MAXDELAY FROM TIMEGRP
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"clk_i_cml_2" TO TIMEGRP "clk_i" 1 ns DATAPATHONLY;
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--------------------------------------------------------------------------------
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================================================================================
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Timing constraint: TS_clk_i_cml_3_clk_i_cml_1_ERROR = MAXDELAY FROM TIMEGRP
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"clk_i_cml_3" TO TIMEGRP "clk_i_cml_1" 1 ns DATAPATHONLY;
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| 233 |
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| 235 |
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--------------------------------------------------------------------------------
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| 237 |
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| 238 |
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================================================================================
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| 239 |
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Timing constraint: TS_clk_i_clk_i_cml_3_ERROR = MAXDELAY FROM TIMEGRP "clk_i"
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| 240 |
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TO TIMEGRP "clk_i_cml_3" 1 ns DATAPATHONLY;
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| 241 |
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| 242 |
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| 243 |
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| 244 |
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--------------------------------------------------------------------------------
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| 245 |
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| 246 |
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================================================================================
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| 247 |
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Timing constraint: TS_clk_i_cml_1_clk_i_ERROR = MAXDELAY FROM TIMEGRP
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| 248 |
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"clk_i_cml_1" TO TIMEGRP "clk_i" 1 ns DATAPATHONLY;
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| 249 |
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| 250 |
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| 251 |
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| 252 |
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--------------------------------------------------------------------------------
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| 253 |
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| 254 |
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================================================================================
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| 255 |
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Timing constraint: TS_clk_i_cml_2_clk_i_cml_1_ERROR = MAXDELAY FROM TIMEGRP
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| 256 |
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"clk_i_cml_2" TO TIMEGRP "clk_i_cml_1" 1 ns DATAPATHONLY;
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| 257 |
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| 258 |
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| 259 |
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| 260 |
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--------------------------------------------------------------------------------
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| 261 |
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| 262 |
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================================================================================
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| 263 |
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Timing constraint: TS_clk_i_cml_3_clk_i_cml_2_ERROR = MAXDELAY FROM TIMEGRP
|
| 264 |
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"clk_i_cml_3" TO TIMEGRP "clk_i_cml_2" 1 ns DATAPATHONLY;
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| 265 |
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| 266 |
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| 267 |
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| 268 |
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--------------------------------------------------------------------------------
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| 269 |
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| 270 |
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| 271 |
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1 constraint not met.
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| 272 |
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| 273 |
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| 274 |
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Data Sheet report:
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| 275 |
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-----------------
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| 276 |
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No constraints were found to generate data for the Data Sheet Report section.
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| 277 |
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Use the Advanced Analysis (-a) option or generate global constraints for each
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| 278 |
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clock, its pad to setup and clock to pad paths, and a pad to pad constraint.
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| 279 |
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| 280 |
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Timing summary:
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| 281 |
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---------------
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| 282 |
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| 283 |
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Timing errors: 3242 Score: 922706 (Setup/Max: 0, Hold: 0, Component Switching Limit: 922706)
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| 284 |
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| 285 |
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Constraints cover 0 paths, 0 nets, and 0 connections
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| 286 |
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| 287 |
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Design statistics:
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| 288 |
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Minimum period: 2.400ns{1} (Maximum frequency: 416.667MHz)
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| 289 |
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| 290 |
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| 291 |
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------------------------------------Footnotes-----------------------------------
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| 292 |
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1) The minimum period statistic assumes all single cycle delays.
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| 293 |
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| 294 |
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Analysis completed Thu Oct 21 17:06:02 2010
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| 295 |
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--------------------------------------------------------------------------------
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| 296 |
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| 297 |
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Trace Settings:
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| 298 |
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-------------------------
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| 299 |
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Trace Settings
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| 300 |
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| 301 |
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Peak Memory Usage: 327 MB
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| 302 |
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