| 1 |
2 |
tobil |
--------------------------------------------------------------------------------
|
| 2 |
|
|
Release 11.1 Trace (nt)
|
| 3 |
|
|
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
|
| 4 |
|
|
|
| 5 |
|
|
C:\Xilinx\11.1\ISE\bin\nt\unwrapped\trce.exe -ise
|
| 6 |
|
|
C:/EDAptability/coremultiplier/reference/or1200_new/ise/ise_or1200_orig/ise_or1200_orig/ise_or1200_orig.ise
|
| 7 |
|
|
-intstyle ise -v 3 -s 1 -fastpaths -xml or1200_top.twx or1200_top.ncd -o
|
| 8 |
|
|
or1200_top.twr or1200_top.pcf -ucf or1200_top.ucf
|
| 9 |
|
|
|
| 10 |
|
|
Design file: or1200_top.ncd
|
| 11 |
|
|
Physical constraint file: or1200_top.pcf
|
| 12 |
|
|
Device,package,speed: xc5vlx50,ff676,-1 (PRODUCTION 1.64 2009-03-03, STEPPING level 0)
|
| 13 |
|
|
Report level: verbose report
|
| 14 |
|
|
|
| 15 |
|
|
Environment Variable Effect
|
| 16 |
|
|
-------------------- ------
|
| 17 |
|
|
NONE No environment variables were set
|
| 18 |
|
|
--------------------------------------------------------------------------------
|
| 19 |
|
|
|
| 20 |
|
|
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
|
| 21 |
|
|
option. All paths that are not constrained will be reported in the
|
| 22 |
|
|
unconstrained paths section(s) of the report.
|
| 23 |
|
|
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
|
| 24 |
|
|
a 50 Ohm transmission line loading model. For the details of this model,
|
| 25 |
|
|
and for more information on accounting for different loading conditions,
|
| 26 |
|
|
please see the device datasheet.
|
| 27 |
|
|
|
| 28 |
|
|
================================================================================
|
| 29 |
|
|
Timing constraint: TS_clk_i = PERIOD TIMEGRP "clk_i" 13.5 ns HIGH 50%;
|
| 30 |
|
|
|
| 31 |
|
|
82773042 paths analyzed, 7275 endpoints analyzed, 218 failing endpoints
|
| 32 |
|
|
218 timing errors detected. (218 setup errors, 0 hold errors, 0 component switching limit errors)
|
| 33 |
|
|
Minimum period is 14.169ns.
|
| 34 |
|
|
--------------------------------------------------------------------------------
|
| 35 |
|
|
Slack (setup path): -0.669ns (requirement - (data path - clock path skew + uncertainty))
|
| 36 |
|
|
Source: or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM18.TDP (RAM)
|
| 37 |
|
|
Destination: or1200_cpu/or1200_ctrl/spr_addrimm_6_1 (FF)
|
| 38 |
|
|
Requirement: 13.500ns
|
| 39 |
|
|
Data Path Delay: 13.853ns (Levels of Logic = 12)
|
| 40 |
|
|
Clock Path Skew: -0.281ns (1.109 - 1.390)
|
| 41 |
|
|
Source Clock: clk_i_BUFGP rising at 0.000ns
|
| 42 |
|
|
Destination Clock: clk_i_BUFGP rising at 13.500ns
|
| 43 |
|
|
Clock Uncertainty: 0.035ns
|
| 44 |
|
|
|
| 45 |
|
|
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
| 46 |
|
|
Total System Jitter (TSJ): 0.070ns
|
| 47 |
|
|
Total Input Jitter (TIJ): 0.000ns
|
| 48 |
|
|
Discrete Jitter (DJ): 0.000ns
|
| 49 |
|
|
Phase Error (PE): 0.000ns
|
| 50 |
|
|
|
| 51 |
|
|
Maximum Data Path: or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM18.TDP to or1200_cpu/or1200_ctrl/spr_addrimm_6_1
|
| 52 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 53 |
|
|
Logical Resource(s)
|
| 54 |
|
|
------------------------------------------------- -------------------
|
| 55 |
|
|
RAMB36_X1Y6.DOADOL8 Trcko_DO 2.180 or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM18.TDP
|
| 56 |
|
|
or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM18.TDP
|
| 57 |
|
|
SLICE_X42Y29.B4 net (fanout=1) 0.915 or1200_ic_top/tag<4>
|
| 58 |
|
|
SLICE_X42Y29.COUT Topcyb 0.501 or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>
|
| 59 |
|
|
or1200_ic_top/tagcomp_miss_or0000_wg_lut<1>
|
| 60 |
|
|
or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>
|
| 61 |
|
|
SLICE_X42Y30.CIN net (fanout=1) 0.010 or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>
|
| 62 |
|
|
SLICE_X42Y30.CMUX Tcinc 0.352 or1200_ic_top/tagcomp_miss
|
| 63 |
|
|
or1200_ic_top/tagcomp_miss_or0000_wg_cy<6>
|
| 64 |
|
|
SLICE_X43Y47.A6 net (fanout=22) 1.376 or1200_ic_top/tagcomp_miss
|
| 65 |
|
|
SLICE_X43Y47.A Tilo 0.094 iwb_biu/aborted_r
|
| 66 |
|
|
or1200_ic_top/icqmem_ack_o1
|
| 67 |
|
|
SLICE_X41Y52.C6 net (fanout=71) 0.653 icqmem_ack_ic
|
| 68 |
|
|
SLICE_X41Y52.C Tilo 0.094 or1200_immu_top/dis_spr_access
|
| 69 |
|
|
or1200_cpu/or1200_genpc/icpu_adr_o_and00001
|
| 70 |
|
|
SLICE_X45Y50.D6 net (fanout=64) 0.791 or1200_cpu/or1200_genpc/icpu_adr_o_and0000
|
| 71 |
|
|
SLICE_X45Y50.D Tilo 0.094 or1200_immu_top/icpu_vpn_r<16>
|
| 72 |
|
|
or1200_cpu/or1200_genpc/icpu_adr_o<16>1
|
| 73 |
|
|
SLICE_X44Y45.B4 net (fanout=1) 0.869 icpu_adr_cpu<16>
|
| 74 |
|
|
SLICE_X44Y45.COUT Topcyb 0.483 or1200_immu_top/Mcompar_page_cross_cy<3>
|
| 75 |
|
|
or1200_immu_top/Mcompar_page_cross_lut<1>
|
| 76 |
|
|
or1200_immu_top/Mcompar_page_cross_cy<3>
|
| 77 |
|
|
SLICE_X44Y46.CIN net (fanout=1) 0.000 or1200_immu_top/Mcompar_page_cross_cy<3>
|
| 78 |
|
|
SLICE_X44Y46.CMUX Tcinc 0.358 or1200_immu_top/page_cross
|
| 79 |
|
|
or1200_immu_top/Mcompar_page_cross_cy<6>
|
| 80 |
|
|
SLICE_X45Y63.A6 net (fanout=46) 1.258 or1200_immu_top/page_cross
|
| 81 |
|
|
SLICE_X45Y63.A Tilo 0.094 N912
|
| 82 |
|
|
or1200_cpu/or1200_if/if_stall1
|
| 83 |
|
|
SLICE_X45Y63.C6 net (fanout=12) 0.353 or1200_cpu/if_stall
|
| 84 |
|
|
SLICE_X45Y63.C Tilo 0.094 N912
|
| 85 |
|
|
or1200_cpu/or1200_freeze/wb_freeze1
|
| 86 |
|
|
SLICE_X45Y65.C6 net (fanout=112) 0.408 ex_freeze
|
| 87 |
|
|
SLICE_X45Y65.C Tilo 0.094 or1200_cpu/or1200_ctrl/alu_op_2_1
|
| 88 |
|
|
or1200_cpu/or1200_except/epcr_mux0000<0>3
|
| 89 |
|
|
SLICE_X46Y59.B6 net (fanout=342) 1.101 or1200_cpu/or1200_except/N01
|
| 90 |
|
|
SLICE_X46Y59.B Tilo 0.094 or1200_cpu/or1200_ctrl/id_insn<23>
|
| 91 |
|
|
or1200_cpu/or1200_except/flushpipe1
|
| 92 |
|
|
SLICE_X40Y61.C6 net (fanout=98) 0.999 or1200_cpu/flushpipe
|
| 93 |
|
|
SLICE_X40Y61.C Tilo 0.094 or1200_cpu/or1200_ctrl/spr_addrimm<7>
|
| 94 |
|
|
or1200_cpu/or1200_ctrl/spr_addrimm_6_rstpot
|
| 95 |
|
|
SLICE_X32Y61.AX net (fanout=1) 0.506 or1200_cpu/or1200_ctrl/spr_addrimm_6_rstpot
|
| 96 |
|
|
SLICE_X32Y61.CLK Tdick -0.012 or1200_cpu/or1200_ctrl/spr_addrimm_6_1
|
| 97 |
|
|
or1200_cpu/or1200_ctrl/spr_addrimm_6_1
|
| 98 |
|
|
------------------------------------------------- ---------------------------
|
| 99 |
|
|
Total 13.853ns (4.614ns logic, 9.239ns route)
|
| 100 |
|
|
(33.3% logic, 66.7% route)
|
| 101 |
|
|
|
| 102 |
|
|
--------------------------------------------------------------------------------
|
| 103 |
|
|
Slack (setup path): -0.632ns (requirement - (data path - clock path skew + uncertainty))
|
| 104 |
|
|
Source: or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM18.TDP (RAM)
|
| 105 |
|
|
Destination: or1200_cpu/or1200_ctrl/alu_op_1_1 (FF)
|
| 106 |
|
|
Requirement: 13.500ns
|
| 107 |
|
|
Data Path Delay: 13.852ns (Levels of Logic = 12)
|
| 108 |
|
|
Clock Path Skew: -0.245ns (1.145 - 1.390)
|
| 109 |
|
|
Source Clock: clk_i_BUFGP rising at 0.000ns
|
| 110 |
|
|
Destination Clock: clk_i_BUFGP rising at 13.500ns
|
| 111 |
|
|
Clock Uncertainty: 0.035ns
|
| 112 |
|
|
|
| 113 |
|
|
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
| 114 |
|
|
Total System Jitter (TSJ): 0.070ns
|
| 115 |
|
|
Total Input Jitter (TIJ): 0.000ns
|
| 116 |
|
|
Discrete Jitter (DJ): 0.000ns
|
| 117 |
|
|
Phase Error (PE): 0.000ns
|
| 118 |
|
|
|
| 119 |
|
|
Maximum Data Path: or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM18.TDP to or1200_cpu/or1200_ctrl/alu_op_1_1
|
| 120 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 121 |
|
|
Logical Resource(s)
|
| 122 |
|
|
------------------------------------------------- -------------------
|
| 123 |
|
|
RAMB36_X1Y6.DOADOL8 Trcko_DO 2.180 or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM18.TDP
|
| 124 |
|
|
or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM18.TDP
|
| 125 |
|
|
SLICE_X42Y29.B4 net (fanout=1) 0.915 or1200_ic_top/tag<4>
|
| 126 |
|
|
SLICE_X42Y29.COUT Topcyb 0.501 or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>
|
| 127 |
|
|
or1200_ic_top/tagcomp_miss_or0000_wg_lut<1>
|
| 128 |
|
|
or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>
|
| 129 |
|
|
SLICE_X42Y30.CIN net (fanout=1) 0.010 or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>
|
| 130 |
|
|
SLICE_X42Y30.CMUX Tcinc 0.352 or1200_ic_top/tagcomp_miss
|
| 131 |
|
|
or1200_ic_top/tagcomp_miss_or0000_wg_cy<6>
|
| 132 |
|
|
SLICE_X43Y47.A6 net (fanout=22) 1.376 or1200_ic_top/tagcomp_miss
|
| 133 |
|
|
SLICE_X43Y47.A Tilo 0.094 iwb_biu/aborted_r
|
| 134 |
|
|
or1200_ic_top/icqmem_ack_o1
|
| 135 |
|
|
SLICE_X41Y52.C6 net (fanout=71) 0.653 icqmem_ack_ic
|
| 136 |
|
|
SLICE_X41Y52.C Tilo 0.094 or1200_immu_top/dis_spr_access
|
| 137 |
|
|
or1200_cpu/or1200_genpc/icpu_adr_o_and00001
|
| 138 |
|
|
SLICE_X45Y50.D6 net (fanout=64) 0.791 or1200_cpu/or1200_genpc/icpu_adr_o_and0000
|
| 139 |
|
|
SLICE_X45Y50.D Tilo 0.094 or1200_immu_top/icpu_vpn_r<16>
|
| 140 |
|
|
or1200_cpu/or1200_genpc/icpu_adr_o<16>1
|
| 141 |
|
|
SLICE_X44Y45.B4 net (fanout=1) 0.869 icpu_adr_cpu<16>
|
| 142 |
|
|
SLICE_X44Y45.COUT Topcyb 0.483 or1200_immu_top/Mcompar_page_cross_cy<3>
|
| 143 |
|
|
or1200_immu_top/Mcompar_page_cross_lut<1>
|
| 144 |
|
|
or1200_immu_top/Mcompar_page_cross_cy<3>
|
| 145 |
|
|
SLICE_X44Y46.CIN net (fanout=1) 0.000 or1200_immu_top/Mcompar_page_cross_cy<3>
|
| 146 |
|
|
SLICE_X44Y46.CMUX Tcinc 0.358 or1200_immu_top/page_cross
|
| 147 |
|
|
or1200_immu_top/Mcompar_page_cross_cy<6>
|
| 148 |
|
|
SLICE_X45Y63.A6 net (fanout=46) 1.258 or1200_immu_top/page_cross
|
| 149 |
|
|
SLICE_X45Y63.A Tilo 0.094 N912
|
| 150 |
|
|
or1200_cpu/or1200_if/if_stall1
|
| 151 |
|
|
SLICE_X45Y63.C6 net (fanout=12) 0.353 or1200_cpu/if_stall
|
| 152 |
|
|
SLICE_X45Y63.C Tilo 0.094 N912
|
| 153 |
|
|
or1200_cpu/or1200_freeze/wb_freeze1
|
| 154 |
|
|
SLICE_X45Y65.C6 net (fanout=112) 0.408 ex_freeze
|
| 155 |
|
|
SLICE_X45Y65.C Tilo 0.094 or1200_cpu/or1200_ctrl/alu_op_2_1
|
| 156 |
|
|
or1200_cpu/or1200_except/epcr_mux0000<0>3
|
| 157 |
|
|
SLICE_X46Y59.B6 net (fanout=342) 1.101 or1200_cpu/or1200_except/N01
|
| 158 |
|
|
SLICE_X46Y59.B Tilo 0.094 or1200_cpu/or1200_ctrl/id_insn<23>
|
| 159 |
|
|
or1200_cpu/or1200_except/flushpipe1
|
| 160 |
|
|
SLICE_X34Y63.A6 net (fanout=98) 1.153 or1200_cpu/flushpipe
|
| 161 |
|
|
SLICE_X34Y63.A Tilo 0.094 or1200_cpu/or1200_ctrl/alu_op<1>
|
| 162 |
|
|
or1200_cpu/or1200_ctrl/alu_op_1_rstpot
|
| 163 |
|
|
SLICE_X34Y61.DX net (fanout=1) 0.337 or1200_cpu/or1200_ctrl/alu_op_1_rstpot
|
| 164 |
|
|
SLICE_X34Y61.CLK Tdick 0.002 or1200_cpu/or1200_ctrl/alu_op_1_1
|
| 165 |
|
|
or1200_cpu/or1200_ctrl/alu_op_1_1
|
| 166 |
|
|
------------------------------------------------- ---------------------------
|
| 167 |
|
|
Total 13.852ns (4.628ns logic, 9.224ns route)
|
| 168 |
|
|
(33.4% logic, 66.6% route)
|
| 169 |
|
|
|
| 170 |
|
|
--------------------------------------------------------------------------------
|
| 171 |
|
|
Slack (setup path): -0.590ns (requirement - (data path - clock path skew + uncertainty))
|
| 172 |
|
|
Source: or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM18.TDP (RAM)
|
| 173 |
|
|
Destination: or1200_cpu/or1200_ctrl/spr_addrimm_5_1 (FF)
|
| 174 |
|
|
Requirement: 13.500ns
|
| 175 |
|
|
Data Path Delay: 13.810ns (Levels of Logic = 12)
|
| 176 |
|
|
Clock Path Skew: -0.245ns (1.145 - 1.390)
|
| 177 |
|
|
Source Clock: clk_i_BUFGP rising at 0.000ns
|
| 178 |
|
|
Destination Clock: clk_i_BUFGP rising at 13.500ns
|
| 179 |
|
|
Clock Uncertainty: 0.035ns
|
| 180 |
|
|
|
| 181 |
|
|
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
| 182 |
|
|
Total System Jitter (TSJ): 0.070ns
|
| 183 |
|
|
Total Input Jitter (TIJ): 0.000ns
|
| 184 |
|
|
Discrete Jitter (DJ): 0.000ns
|
| 185 |
|
|
Phase Error (PE): 0.000ns
|
| 186 |
|
|
|
| 187 |
|
|
Maximum Data Path: or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM18.TDP to or1200_cpu/or1200_ctrl/spr_addrimm_5_1
|
| 188 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 189 |
|
|
Logical Resource(s)
|
| 190 |
|
|
------------------------------------------------- -------------------
|
| 191 |
|
|
RAMB36_X1Y6.DOADOL8 Trcko_DO 2.180 or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM18.TDP
|
| 192 |
|
|
or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM18.TDP
|
| 193 |
|
|
SLICE_X42Y29.B4 net (fanout=1) 0.915 or1200_ic_top/tag<4>
|
| 194 |
|
|
SLICE_X42Y29.COUT Topcyb 0.501 or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>
|
| 195 |
|
|
or1200_ic_top/tagcomp_miss_or0000_wg_lut<1>
|
| 196 |
|
|
or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>
|
| 197 |
|
|
SLICE_X42Y30.CIN net (fanout=1) 0.010 or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>
|
| 198 |
|
|
SLICE_X42Y30.CMUX Tcinc 0.352 or1200_ic_top/tagcomp_miss
|
| 199 |
|
|
or1200_ic_top/tagcomp_miss_or0000_wg_cy<6>
|
| 200 |
|
|
SLICE_X43Y47.A6 net (fanout=22) 1.376 or1200_ic_top/tagcomp_miss
|
| 201 |
|
|
SLICE_X43Y47.A Tilo 0.094 iwb_biu/aborted_r
|
| 202 |
|
|
or1200_ic_top/icqmem_ack_o1
|
| 203 |
|
|
SLICE_X41Y52.C6 net (fanout=71) 0.653 icqmem_ack_ic
|
| 204 |
|
|
SLICE_X41Y52.C Tilo 0.094 or1200_immu_top/dis_spr_access
|
| 205 |
|
|
or1200_cpu/or1200_genpc/icpu_adr_o_and00001
|
| 206 |
|
|
SLICE_X45Y50.D6 net (fanout=64) 0.791 or1200_cpu/or1200_genpc/icpu_adr_o_and0000
|
| 207 |
|
|
SLICE_X45Y50.D Tilo 0.094 or1200_immu_top/icpu_vpn_r<16>
|
| 208 |
|
|
or1200_cpu/or1200_genpc/icpu_adr_o<16>1
|
| 209 |
|
|
SLICE_X44Y45.B4 net (fanout=1) 0.869 icpu_adr_cpu<16>
|
| 210 |
|
|
SLICE_X44Y45.COUT Topcyb 0.483 or1200_immu_top/Mcompar_page_cross_cy<3>
|
| 211 |
|
|
or1200_immu_top/Mcompar_page_cross_lut<1>
|
| 212 |
|
|
or1200_immu_top/Mcompar_page_cross_cy<3>
|
| 213 |
|
|
SLICE_X44Y46.CIN net (fanout=1) 0.000 or1200_immu_top/Mcompar_page_cross_cy<3>
|
| 214 |
|
|
SLICE_X44Y46.CMUX Tcinc 0.358 or1200_immu_top/page_cross
|
| 215 |
|
|
or1200_immu_top/Mcompar_page_cross_cy<6>
|
| 216 |
|
|
SLICE_X45Y63.A6 net (fanout=46) 1.258 or1200_immu_top/page_cross
|
| 217 |
|
|
SLICE_X45Y63.A Tilo 0.094 N912
|
| 218 |
|
|
or1200_cpu/or1200_if/if_stall1
|
| 219 |
|
|
SLICE_X45Y63.C6 net (fanout=12) 0.353 or1200_cpu/if_stall
|
| 220 |
|
|
SLICE_X45Y63.C Tilo 0.094 N912
|
| 221 |
|
|
or1200_cpu/or1200_freeze/wb_freeze1
|
| 222 |
|
|
SLICE_X45Y65.C6 net (fanout=112) 0.408 ex_freeze
|
| 223 |
|
|
SLICE_X45Y65.C Tilo 0.094 or1200_cpu/or1200_ctrl/alu_op_2_1
|
| 224 |
|
|
or1200_cpu/or1200_except/epcr_mux0000<0>3
|
| 225 |
|
|
SLICE_X46Y59.B6 net (fanout=342) 1.101 or1200_cpu/or1200_except/N01
|
| 226 |
|
|
SLICE_X46Y59.B Tilo 0.094 or1200_cpu/or1200_ctrl/id_insn<23>
|
| 227 |
|
|
or1200_cpu/or1200_except/flushpipe1
|
| 228 |
|
|
SLICE_X40Y61.B5 net (fanout=98) 0.918 or1200_cpu/flushpipe
|
| 229 |
|
|
SLICE_X40Y61.B Tilo 0.094 or1200_cpu/or1200_ctrl/spr_addrimm<7>
|
| 230 |
|
|
or1200_cpu/or1200_ctrl/spr_addrimm_5_rstpot
|
| 231 |
|
|
SLICE_X34Y61.AX net (fanout=1) 0.540 or1200_cpu/or1200_ctrl/spr_addrimm_5_rstpot
|
| 232 |
|
|
SLICE_X34Y61.CLK Tdick -0.008 or1200_cpu/or1200_ctrl/alu_op_1_1
|
| 233 |
|
|
or1200_cpu/or1200_ctrl/spr_addrimm_5_1
|
| 234 |
|
|
------------------------------------------------- ---------------------------
|
| 235 |
|
|
Total 13.810ns (4.618ns logic, 9.192ns route)
|
| 236 |
|
|
(33.4% logic, 66.6% route)
|
| 237 |
|
|
|
| 238 |
|
|
--------------------------------------------------------------------------------
|
| 239 |
|
|
|
| 240 |
|
|
Hold Paths: TS_clk_i = PERIOD TIMEGRP "clk_i" 13.5 ns HIGH 50%;
|
| 241 |
|
|
--------------------------------------------------------------------------------
|
| 242 |
|
|
Slack (hold path): 0.309ns (requirement - (clock path skew + uncertainty - data path))
|
| 243 |
|
|
Source: or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/Mmult_p0_mult00005_0 (FF)
|
| 244 |
|
|
Destination: or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/p1_33 (FF)
|
| 245 |
|
|
Requirement: 0.000ns
|
| 246 |
|
|
Data Path Delay: 0.318ns (Levels of Logic = 0)
|
| 247 |
|
|
Clock Path Skew: 0.009ns (0.150 - 0.141)
|
| 248 |
|
|
Source Clock: clk_i_BUFGP rising at 13.500ns
|
| 249 |
|
|
Destination Clock: clk_i_BUFGP rising at 13.500ns
|
| 250 |
|
|
Clock Uncertainty: 0.000ns
|
| 251 |
|
|
|
| 252 |
|
|
Minimum Data Path: or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/Mmult_p0_mult00005_0 to or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/p1_33
|
| 253 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 254 |
|
|
Logical Resource(s)
|
| 255 |
|
|
------------------------------------------------- -------------------
|
| 256 |
|
|
SLICE_X13Y105.AQ Tcko 0.414 or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/Mmult_p0_mult00005_3
|
| 257 |
|
|
or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/Mmult_p0_mult00005_0
|
| 258 |
|
|
SLICE_X12Y105.BX net (fanout=1) 0.146 or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/Mmult_p0_mult00005_0
|
| 259 |
|
|
SLICE_X12Y105.CLK Tckdi (-Th) 0.242 or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/p1<35>
|
| 260 |
|
|
or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/p1_33
|
| 261 |
|
|
------------------------------------------------- ---------------------------
|
| 262 |
|
|
Total 0.318ns (0.172ns logic, 0.146ns route)
|
| 263 |
|
|
(54.1% logic, 45.9% route)
|
| 264 |
|
|
|
| 265 |
|
|
--------------------------------------------------------------------------------
|
| 266 |
|
|
Slack (hold path): 0.312ns (requirement - (clock path skew + uncertainty - data path))
|
| 267 |
|
|
Source: or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/Mmult_p0_mult00005_7 (FF)
|
| 268 |
|
|
Destination: or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/p1_26 (FF)
|
| 269 |
|
|
Requirement: 0.000ns
|
| 270 |
|
|
Data Path Delay: 0.350ns (Levels of Logic = 0)
|
| 271 |
|
|
Clock Path Skew: 0.038ns (0.174 - 0.136)
|
| 272 |
|
|
Source Clock: clk_i_BUFGP rising at 13.500ns
|
| 273 |
|
|
Destination Clock: clk_i_BUFGP rising at 13.500ns
|
| 274 |
|
|
Clock Uncertainty: 0.000ns
|
| 275 |
|
|
|
| 276 |
|
|
Minimum Data Path: or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/Mmult_p0_mult00005_7 to or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/p1_26
|
| 277 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 278 |
|
|
Logical Resource(s)
|
| 279 |
|
|
------------------------------------------------- -------------------
|
| 280 |
|
|
SLICE_X19Y95.DQ Tcko 0.414 or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/Mmult_p0_mult00005_7
|
| 281 |
|
|
or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/Mmult_p0_mult00005_7
|
| 282 |
|
|
SLICE_X18Y95.CX net (fanout=1) 0.154 or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/Mmult_p0_mult00005_7
|
| 283 |
|
|
SLICE_X18Y95.CLK Tckdi (-Th) 0.218 or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/p1<27>
|
| 284 |
|
|
or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/p1_26
|
| 285 |
|
|
------------------------------------------------- ---------------------------
|
| 286 |
|
|
Total 0.350ns (0.196ns logic, 0.154ns route)
|
| 287 |
|
|
(56.0% logic, 44.0% route)
|
| 288 |
|
|
|
| 289 |
|
|
--------------------------------------------------------------------------------
|
| 290 |
|
|
Slack (hold path): 0.315ns (requirement - (clock path skew + uncertainty - data path))
|
| 291 |
|
|
Source: or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/Mmult_p0_mult00005_1 (FF)
|
| 292 |
|
|
Destination: or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/p1_32 (FF)
|
| 293 |
|
|
Requirement: 0.000ns
|
| 294 |
|
|
Data Path Delay: 0.324ns (Levels of Logic = 0)
|
| 295 |
|
|
Clock Path Skew: 0.009ns (0.150 - 0.141)
|
| 296 |
|
|
Source Clock: clk_i_BUFGP rising at 13.500ns
|
| 297 |
|
|
Destination Clock: clk_i_BUFGP rising at 13.500ns
|
| 298 |
|
|
Clock Uncertainty: 0.000ns
|
| 299 |
|
|
|
| 300 |
|
|
Minimum Data Path: or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/Mmult_p0_mult00005_1 to or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/p1_32
|
| 301 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 302 |
|
|
Logical Resource(s)
|
| 303 |
|
|
------------------------------------------------- -------------------
|
| 304 |
|
|
SLICE_X13Y105.BQ Tcko 0.414 or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/Mmult_p0_mult00005_3
|
| 305 |
|
|
or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/Mmult_p0_mult00005_1
|
| 306 |
|
|
SLICE_X12Y105.AX net (fanout=1) 0.146 or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/Mmult_p0_mult00005_1
|
| 307 |
|
|
SLICE_X12Y105.CLK Tckdi (-Th) 0.236 or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/p1<35>
|
| 308 |
|
|
or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/p1_32
|
| 309 |
|
|
------------------------------------------------- ---------------------------
|
| 310 |
|
|
Total 0.324ns (0.178ns logic, 0.146ns route)
|
| 311 |
|
|
(54.9% logic, 45.1% route)
|
| 312 |
|
|
|
| 313 |
|
|
--------------------------------------------------------------------------------
|
| 314 |
|
|
|
| 315 |
|
|
Component Switching Limit Checks: TS_clk_i = PERIOD TIMEGRP "clk_i" 13.5 ns HIGH 50%;
|
| 316 |
|
|
--------------------------------------------------------------------------------
|
| 317 |
|
|
Slack: 11.100ns (period - (min high pulse limit / (high pulse / period)))
|
| 318 |
|
|
Period: 13.500ns
|
| 319 |
|
|
High pulse: 6.750ns
|
| 320 |
|
|
High pulse limit: 1.200ns (Tospwh)
|
| 321 |
|
|
Physical resource: or1200_du/dbg_ack_o/SR
|
| 322 |
|
|
Logical resource: or1200_du/dbg_ack_o/SR
|
| 323 |
|
|
Location pin: OLOGIC_X2Y199.SR
|
| 324 |
|
|
Clock network: rst_i_IBUF
|
| 325 |
|
|
--------------------------------------------------------------------------------
|
| 326 |
|
|
Slack: 11.100ns (period - (min high pulse limit / (high pulse / period)))
|
| 327 |
|
|
Period: 13.500ns
|
| 328 |
|
|
High pulse: 6.750ns
|
| 329 |
|
|
High pulse limit: 1.200ns (Tospwh)
|
| 330 |
|
|
Physical resource: iwb_biu/wb_sel_o<3>/SR
|
| 331 |
|
|
Logical resource: iwb_biu/wb_sel_o_3/SR
|
| 332 |
|
|
Location pin: OLOGIC_X2Y164.SR
|
| 333 |
|
|
Clock network: rst_i_IBUF
|
| 334 |
|
|
--------------------------------------------------------------------------------
|
| 335 |
|
|
Slack: 11.100ns (period - (min high pulse limit / (high pulse / period)))
|
| 336 |
|
|
Period: 13.500ns
|
| 337 |
|
|
High pulse: 6.750ns
|
| 338 |
|
|
High pulse limit: 1.200ns (Tospwh)
|
| 339 |
|
|
Physical resource: iwb_biu/wb_sel_o_3_3/SR
|
| 340 |
|
|
Logical resource: iwb_biu/wb_sel_o_3_3/SR
|
| 341 |
|
|
Location pin: OLOGIC_X0Y62.SR
|
| 342 |
|
|
Clock network: rst_i_IBUF
|
| 343 |
|
|
--------------------------------------------------------------------------------
|
| 344 |
|
|
|
| 345 |
|
|
|
| 346 |
|
|
1 constraint not met.
|
| 347 |
|
|
|
| 348 |
|
|
|
| 349 |
|
|
Data Sheet report:
|
| 350 |
|
|
-----------------
|
| 351 |
|
|
All values displayed in nanoseconds (ns)
|
| 352 |
|
|
|
| 353 |
|
|
Clock to Setup on destination clock clk_i
|
| 354 |
|
|
---------------+---------+---------+---------+---------+
|
| 355 |
|
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
| 356 |
|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
| 357 |
|
|
---------------+---------+---------+---------+---------+
|
| 358 |
|
|
clk_i | 14.169| | | |
|
| 359 |
|
|
---------------+---------+---------+---------+---------+
|
| 360 |
|
|
|
| 361 |
|
|
|
| 362 |
|
|
Timing summary:
|
| 363 |
|
|
---------------
|
| 364 |
|
|
|
| 365 |
|
|
Timing errors: 218 Score: 38142 (Setup/Max: 38142, Hold: 0)
|
| 366 |
|
|
|
| 367 |
|
|
Constraints cover 82773042 paths, 0 nets, and 18525 connections
|
| 368 |
|
|
|
| 369 |
|
|
Design statistics:
|
| 370 |
|
|
Minimum period: 14.169ns{1} (Maximum frequency: 70.577MHz)
|
| 371 |
|
|
|
| 372 |
|
|
|
| 373 |
|
|
------------------------------------Footnotes-----------------------------------
|
| 374 |
|
|
1) The minimum period statistic assumes all single cycle delays.
|
| 375 |
|
|
|
| 376 |
|
|
Analysis completed Sun Oct 17 21:17:55 2010
|
| 377 |
|
|
--------------------------------------------------------------------------------
|
| 378 |
|
|
|
| 379 |
|
|
Trace Settings:
|
| 380 |
|
|
-------------------------
|
| 381 |
|
|
Trace Settings
|
| 382 |
|
|
|
| 383 |
|
|
Peak Memory Usage: 302 MB
|
| 384 |
|
|
|
| 385 |
|
|
|
| 386 |
|
|
|
