URL https://opencores.org/ocsvn/or1200_hp/or1200_hp/trunk

Subversion Repositories or1200_hp

[/] [or1200_hp/] [trunk/] [rtl/] [rtl_cm2/] [verilog/] [or1200_tt.v] - Blame information for rev 2

Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Tick Timer                                         ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  TT according to OR1K architectural specification.           ////
////                                                              ////
////  To Do:                                                      ////
////   None                                                       ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4  2002/03/29 15:16:56  lampret
// Some of the warnings fixed.
//
// Revision 1.3  2002/02/12 01:33:47  lampret
// No longer using async rst as sync reset for the counter.
//
// Revision 1.2  2002/01/28 01:16:00  lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10  2001/11/13 10:00:49  lampret
// Fixed tick timer interrupt reporting by using TTCR[IP] bit.
//
// Revision 1.9  2001/11/10 03:43:57  lampret
// Fixed exceptions.
//
// Revision 1.8  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7  2001/10/14 13:12:10  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:23  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_tt_cm2(
                clk_i_cml_1,
 
        // RISC Internal Interface
        clk, rst, du_stall,
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
        intr
);
 
 
input clk_i_cml_1;
reg  du_stall_cml_1;
reg  spr_write_cml_1;
reg [ 31 : 0 ] spr_addr_cml_1;
reg [ 31 : 0 ] spr_dat_i_cml_1;
reg [ 31 : 0 ] ttmr_cml_1;
reg [ 31 : 0 ] ttcr_cml_1;
 
 
 
//
// RISC Internal Interface
//
input           clk;            // Clock
input           rst;            // Reset
input           du_stall;       // DU stall
input           spr_cs;         // SPR CS
input           spr_write;      // SPR Write
input   [31:0]   spr_addr;       // SPR Address
input   [31:0]   spr_dat_i;      // SPR Write Data
output  [31:0]   spr_dat_o;      // SPR Read Data
output          intr;           // Interrupt output
 
`ifdef OR1200_TT_IMPLEMENTED
 
//
// TT Mode Register bits (or no register)
//
`ifdef OR1200_TT_TTMR
reg     [31:0]   ttmr;   // TTMR bits
`else
wire    [31:0]   ttmr;   // No TTMR register
`endif
 
//
// TT Count Register bits (or no register)
//
`ifdef OR1200_TT_TTCR
reg     [31:0]   ttcr;   // TTCR bits
`else
wire    [31:0]   ttcr;   // No TTCR register
`endif
 
//
// Internal wires & regs
//
wire            ttmr_sel;       // TTMR select
wire            ttcr_sel;       // TTCR select
wire            match;          // Asserted when TTMR[TP]
                                // is equal to TTCR[27:0]
wire            restart;        // Restart counter when asserted
wire            stop;           // Stop counter when asserted
reg     [31:0]   spr_dat_o;      // SPR data out
 
//
// TT registers address decoder
//
 
// SynEDA CoreMultiplier
// assignment(s): ttmr_sel
// replace(s): spr_addr
assign ttmr_sel = (spr_cs && (spr_addr_cml_1[`OR1200_TTOFS_BITS] == `OR1200_TT_OFS_TTMR)) ? 1'b1 : 1'b0;
 
// SynEDA CoreMultiplier
// assignment(s): ttcr_sel
// replace(s): spr_addr
assign ttcr_sel = (spr_cs && (spr_addr_cml_1[`OR1200_TTOFS_BITS] == `OR1200_TT_OFS_TTCR)) ? 1'b1 : 1'b0;
 
//
// Write to TTMR or update of TTMR[IP] bit
//
`ifdef OR1200_TT_TTMR
 
// SynEDA CoreMultiplier
// assignment(s): ttmr
// replace(s): spr_write, spr_dat_i, ttmr
always @(posedge clk or posedge rst)
        if (rst)
                ttmr <= 32'b0;
        else begin  ttmr <= ttmr_cml_1; if (ttmr_sel && spr_write_cml_1)
                ttmr <= #1 spr_dat_i_cml_1;
        else if (ttmr_cml_1[`OR1200_TT_TTMR_IE])
                ttmr[`OR1200_TT_TTMR_IP] <= #1 ttmr_cml_1[`OR1200_TT_TTMR_IP] | (match & ttmr_cml_1[`OR1200_TT_TTMR_IE]); end
`else
assign ttmr = {2'b11, 30'b0};    // TTMR[M] = 0x3
`endif
 
//
// Write to or increment of TTCR
//
`ifdef OR1200_TT_TTCR
 
// SynEDA CoreMultiplier
// assignment(s): ttcr
// replace(s): spr_write, spr_dat_i, ttcr
always @(posedge clk or posedge rst)
        if (rst)
                ttcr <= 32'b0;
        else begin  ttcr <= ttcr_cml_1; if (restart)
                ttcr <= #1 32'b0;
        else if (ttcr_sel && spr_write_cml_1)
                ttcr <= #1 spr_dat_i_cml_1;
        else if (!stop)
                ttcr <= #1 ttcr_cml_1 + 32'd1; end
`else
assign ttcr = 32'b0;
`endif
 
//
// Read TT registers
//
 
// SynEDA CoreMultiplier
// assignment(s): spr_dat_o
// replace(s): spr_addr, ttmr, ttcr
always @(spr_addr_cml_1 or ttmr_cml_1 or ttcr_cml_1)
        case (spr_addr_cml_1[`OR1200_TTOFS_BITS])       // synopsys parallel_case
`ifdef OR1200_TT_READREGS
                `OR1200_TT_OFS_TTMR: spr_dat_o = ttmr_cml_1;
`endif
                default: spr_dat_o = ttcr_cml_1;
        endcase
 
//
// A match when TTMR[TP] is equal to TTCR[27:0]
//
 
// SynEDA CoreMultiplier
// assignment(s): match
// replace(s): ttmr, ttcr
assign match = (ttmr_cml_1[`OR1200_TT_TTMR_TP] == ttcr_cml_1[27:0]) ? 1'b1 : 1'b0;
 
//
// Restart when match and TTMR[M]==0x1
//
 
// SynEDA CoreMultiplier
// assignment(s): restart
// replace(s): ttmr
assign restart = match && (ttmr_cml_1[`OR1200_TT_TTMR_M] == 2'b01);
 
//
// Stop when match and TTMR[M]==0x2 or when TTMR[M]==0x0 or when RISC is stalled by debug unit
//
 
// SynEDA CoreMultiplier
// assignment(s): stop
// replace(s): du_stall, ttmr
assign stop = match & (ttmr_cml_1[`OR1200_TT_TTMR_M] == 2'b10) | (ttmr_cml_1[`OR1200_TT_TTMR_M] == 2'b00) | du_stall_cml_1;
 
//
// Generate an interrupt request
//
assign intr = ttmr[`OR1200_TT_TTMR_IP];
 
`else
 
//
// When TT is not implemented, drive all outputs as would when TT is disabled
//
assign intr = 1'b0;
 
//
// Read TT registers
//
`ifdef OR1200_TT_READREGS
assign spr_dat_o = 32'b0;
`endif
 
`endif
 
 
always @ (posedge clk_i_cml_1) begin
du_stall_cml_1 <= du_stall;
spr_write_cml_1 <= spr_write;
spr_addr_cml_1 <= spr_addr;
spr_dat_i_cml_1 <= spr_dat_i;
ttmr_cml_1 <= ttmr;
ttcr_cml_1 <= ttcr;
end
endmodule
 

Browse

Tools

Subversion Repositories or1200_hp

[/] [or1200_hp/] [trunk/] [rtl/] [rtl_cm2/] [verilog/] [or1200_tt.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	tobil	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Tick Timer ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// TT according to OR1K architectural specification. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// None ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.4 2002/03/29 15:16:56 lampret`
48			`// Some of the warnings fixed.`
49			`//`
50			`// Revision 1.3 2002/02/12 01:33:47 lampret`
51			`// No longer using async rst as sync reset for the counter.`
52			`//`
53			`// Revision 1.2 2002/01/28 01:16:00 lampret`
54			`// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.`
55			`//`
56			`// Revision 1.1 2002/01/03 08:16:15 lampret`
57			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
58			`//`
59			`// Revision 1.10 2001/11/13 10:00:49 lampret`
60			`// Fixed tick timer interrupt reporting by using TTCR[IP] bit.`
61			`//`
62			`// Revision 1.9 2001/11/10 03:43:57 lampret`
63			`// Fixed exceptions.`
64			`//`
65			`// Revision 1.8 2001/10/21 17:57:16 lampret`
66			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
67			`//`
68			`// Revision 1.7 2001/10/14 13:12:10 lampret`
69			`// MP3 version.`
70			`//`
71			`// Revision 1.1.1.1 2001/10/06 10:18:35 igorm`
72			`// no message`
73			`//`
74			`// Revision 1.2 2001/08/09 13:39:33 lampret`
75			`// Major clean-up.`
76			`//`
77			`// Revision 1.1 2001/07/20 00:46:23 lampret`
78			`// Development version of RTL. Libraries are missing.`
79			`//`
80			`//`
81
82			`// synopsys translate_off`
83			`include "timescale.v"
84			`// synopsys translate_on`
85			`include "or1200_defines.v"
86
87			`module or1200_tt_cm2(`
88			`clk_i_cml_1,`
89
90			`// RISC Internal Interface`
91			`clk, rst, du_stall,`
92			`spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,`
93			`intr`
94			`);`
95
96
97			`input clk_i_cml_1;`
98			`reg du_stall_cml_1;`
99			`reg spr_write_cml_1;`
100			`reg [ 31 : 0 ] spr_addr_cml_1;`
101			`reg [ 31 : 0 ] spr_dat_i_cml_1;`
102			`reg [ 31 : 0 ] ttmr_cml_1;`
103			`reg [ 31 : 0 ] ttcr_cml_1;`
104
105
106
107			`//`
108			`// RISC Internal Interface`
109			`//`
110			`input clk; // Clock`
111			`input rst; // Reset`
112			`input du_stall; // DU stall`
113			`input spr_cs; // SPR CS`
114			`input spr_write; // SPR Write`
115			`input [31:0] spr_addr; // SPR Address`
116			`input [31:0] spr_dat_i; // SPR Write Data`
117			`output [31:0] spr_dat_o; // SPR Read Data`
118			`output intr; // Interrupt output`
119
120			`ifdef OR1200_TT_IMPLEMENTED
121
122			`//`
123			`// TT Mode Register bits (or no register)`
124			`//`
125			`ifdef OR1200_TT_TTMR
126			`reg [31:0] ttmr; // TTMR bits`
127			`else
128			`wire [31:0] ttmr; // No TTMR register`
129			`endif
130
131			`//`
132			`// TT Count Register bits (or no register)`
133			`//`
134			`ifdef OR1200_TT_TTCR
135			`reg [31:0] ttcr; // TTCR bits`
136			`else
137			`wire [31:0] ttcr; // No TTCR register`
138			`endif
139
140			`//`
141			`// Internal wires & regs`
142			`//`
143			`wire ttmr_sel; // TTMR select`
144			`wire ttcr_sel; // TTCR select`
145			`wire match; // Asserted when TTMR[TP]`
146			`// is equal to TTCR[27:0]`
147			`wire restart; // Restart counter when asserted`
148			`wire stop; // Stop counter when asserted`
149			`reg [31:0] spr_dat_o; // SPR data out`
150
151			`//`
152			`// TT registers address decoder`
153			`//`
154
155			`// SynEDA CoreMultiplier`
156			`// assignment(s): ttmr_sel`
157			`// replace(s): spr_addr`
158			assign ttmr_sel = (spr_cs && (spr_addr_cml_1[`OR1200_TTOFS_BITS] == `OR1200_TT_OFS_TTMR)) ? 1'b1 : 1'b0;
159
160			`// SynEDA CoreMultiplier`
161			`// assignment(s): ttcr_sel`
162			`// replace(s): spr_addr`
163			assign ttcr_sel = (spr_cs && (spr_addr_cml_1[`OR1200_TTOFS_BITS] == `OR1200_TT_OFS_TTCR)) ? 1'b1 : 1'b0;
164
165			`//`
166			`// Write to TTMR or update of TTMR[IP] bit`
167			`//`
168			`ifdef OR1200_TT_TTMR
169
170			`// SynEDA CoreMultiplier`
171			`// assignment(s): ttmr`
172			`// replace(s): spr_write, spr_dat_i, ttmr`
173			`always @(posedge clk or posedge rst)`
174			`if (rst)`
175			`ttmr <= 32'b0;`
176			`else begin ttmr <= ttmr_cml_1; if (ttmr_sel && spr_write_cml_1)`
177			`ttmr <= #1 spr_dat_i_cml_1;`
178			else if (ttmr_cml_1[`OR1200_TT_TTMR_IE])
179			ttmr[`OR1200_TT_TTMR_IP] <= #1 ttmr_cml_1[`OR1200_TT_TTMR_IP] \| (match & ttmr_cml_1[`OR1200_TT_TTMR_IE]); end
180			`else
181			`assign ttmr = {2'b11, 30'b0}; // TTMR[M] = 0x3`
182			`endif
183
184			`//`
185			`// Write to or increment of TTCR`
186			`//`
187			`ifdef OR1200_TT_TTCR
188
189			`// SynEDA CoreMultiplier`
190			`// assignment(s): ttcr`
191			`// replace(s): spr_write, spr_dat_i, ttcr`
192			`always @(posedge clk or posedge rst)`
193			`if (rst)`
194			`ttcr <= 32'b0;`
195			`else begin ttcr <= ttcr_cml_1; if (restart)`
196			`ttcr <= #1 32'b0;`
197			`else if (ttcr_sel && spr_write_cml_1)`
198			`ttcr <= #1 spr_dat_i_cml_1;`
199			`else if (!stop)`
200			`ttcr <= #1 ttcr_cml_1 + 32'd1; end`
201			`else
202			`assign ttcr = 32'b0;`
203			`endif
204
205			`//`
206			`// Read TT registers`
207			`//`
208
209			`// SynEDA CoreMultiplier`
210			`// assignment(s): spr_dat_o`
211			`// replace(s): spr_addr, ttmr, ttcr`
212			`always @(spr_addr_cml_1 or ttmr_cml_1 or ttcr_cml_1)`
213			case (spr_addr_cml_1[`OR1200_TTOFS_BITS]) // synopsys parallel_case
214			`ifdef OR1200_TT_READREGS
215			`OR1200_TT_OFS_TTMR: spr_dat_o = ttmr_cml_1;
216			`endif
217			`default: spr_dat_o = ttcr_cml_1;`
218			`endcase`
219
220			`//`
221			`// A match when TTMR[TP] is equal to TTCR[27:0]`
222			`//`
223
224			`// SynEDA CoreMultiplier`
225			`// assignment(s): match`
226			`// replace(s): ttmr, ttcr`
227			assign match = (ttmr_cml_1[`OR1200_TT_TTMR_TP] == ttcr_cml_1[27:0]) ? 1'b1 : 1'b0;
228
229			`//`
230			`// Restart when match and TTMR[M]==0x1`
231			`//`
232
233			`// SynEDA CoreMultiplier`
234			`// assignment(s): restart`
235			`// replace(s): ttmr`
236			assign restart = match && (ttmr_cml_1[`OR1200_TT_TTMR_M] == 2'b01);
237
238			`//`
239			`// Stop when match and TTMR[M]==0x2 or when TTMR[M]==0x0 or when RISC is stalled by debug unit`
240			`//`
241
242			`// SynEDA CoreMultiplier`
243			`// assignment(s): stop`
244			`// replace(s): du_stall, ttmr`
245			assign stop = match & (ttmr_cml_1[`OR1200_TT_TTMR_M] == 2'b10) \| (ttmr_cml_1[`OR1200_TT_TTMR_M] == 2'b00) \| du_stall_cml_1;
246
247			`//`
248			`// Generate an interrupt request`
249			`//`
250			assign intr = ttmr[`OR1200_TT_TTMR_IP];
251
252			`else
253
254			`//`
255			`// When TT is not implemented, drive all outputs as would when TT is disabled`
256			`//`
257			`assign intr = 1'b0;`
258
259			`//`
260			`// Read TT registers`
261			`//`
262			`ifdef OR1200_TT_READREGS
263			`assign spr_dat_o = 32'b0;`
264			`endif
265
266			`endif
267
268
269			`always @ (posedge clk_i_cml_1) begin`
270			`du_stall_cml_1 <= du_stall;`
271			`spr_write_cml_1 <= spr_write;`
272			`spr_addr_cml_1 <= spr_addr;`
273			`spr_dat_i_cml_1 <= spr_dat_i;`
274			`ttmr_cml_1 <= ttmr;`
275			`ttcr_cml_1 <= ttcr;`
276			`end`
277			`endmodule`
278