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[/] [or1200_hp/] [trunk/] [rtl/] [rtl_cm2/] [verilog/] [or1200_wbmux.v] - Blame information for rev 2

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Write-back Mux                                     ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  CPU's write-back stage of the pipeline                      ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2002/03/29 15:16:56  lampret
// Some of the warnings fixed.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7  2001/10/14 13:12:10  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:23  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_wbmux_cm2(
                clk_i_cml_1,
 
        // Clock and reset
        clk, rst,
 
        // Internal i/f
        wb_freeze, rfwb_op,
        muxin_a, muxin_b, muxin_c, muxin_d,
        muxout, muxreg, muxreg_valid
);
 
 
input clk_i_cml_1;
reg [ 3 - 1 : 0 ] rfwb_op_cml_1;
reg [ 32 - 1 : 0 ] muxin_a_cml_1;
reg [ 32 - 1 : 0 ] muxreg_cml_1;
reg  muxreg_valid_cml_1;
 
 
 
parameter width = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// Internal i/f
//
input                           wb_freeze;
input   [`OR1200_RFWBOP_WIDTH-1:0]       rfwb_op;
input   [width-1:0]              muxin_a;
input   [width-1:0]              muxin_b;
input   [width-1:0]              muxin_c;
input   [width-1:0]              muxin_d;
output  [width-1:0]              muxout;
output  [width-1:0]              muxreg;
output                          muxreg_valid;
 
//
// Internal wires and regs
//
reg     [width-1:0]              muxout;
reg     [width-1:0]              muxreg;
reg                             muxreg_valid;
 
//
// Registered output from the write-back multiplexer
//
 
// SynEDA CoreMultiplier
// assignment(s): muxreg, muxreg_valid
// replace(s): muxreg, rfwb_op, muxreg_valid
always @(posedge clk or posedge rst) begin
        if (rst) begin
                muxreg <= #1 32'd0;
                muxreg_valid <= #1 1'b0;
        end
        else begin  muxreg_valid <= muxreg_valid_cml_1; muxreg <= muxreg_cml_1; if (!wb_freeze) begin
                muxreg <= #1 muxout;
                muxreg_valid <= #1 rfwb_op_cml_1[0];
        end end
end
 
//
// Write-back multiplexer
//
 
// SynEDA CoreMultiplier
// assignment(s): muxout
// replace(s): rfwb_op, muxin_a
always @(muxin_a_cml_1 or muxin_b or muxin_c or muxin_d or rfwb_op_cml_1) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
        case(rfwb_op_cml_1[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case infer_mux
`else
        case(rfwb_op_cml_1[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case
`endif
                2'b00: muxout = muxin_a_cml_1;
                2'b01: begin
                        muxout = muxin_b;
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("  WBMUX: muxin_b %h", muxin_b);
// synopsys translate_on
`endif
                end
                2'b10: begin
                        muxout = muxin_c;
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("  WBMUX: muxin_c %h", muxin_c);
// synopsys translate_on
`endif
                end
                2'b11: begin
                        muxout = muxin_d + 32'h8;
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("  WBMUX: muxin_d %h", muxin_d + 4'h8);
// synopsys translate_on
`endif
                end
        endcase
end
 
 
always @ (posedge clk_i_cml_1) begin
rfwb_op_cml_1 <= rfwb_op;
muxin_a_cml_1 <= muxin_a;
muxreg_cml_1 <= muxreg;
muxreg_valid_cml_1 <= muxreg_valid;
end
endmodule
 

Line No.	Rev	Author	Line
1	2	tobil	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Write-back Mux ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// CPU's write-back stage of the pipeline ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.2 2002/03/29 15:16:56 lampret`
48			`// Some of the warnings fixed.`
49			`//`
50			`// Revision 1.1 2002/01/03 08:16:15 lampret`
51			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
52			`//`
53			`// Revision 1.8 2001/10/21 17:57:16 lampret`
54			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
55			`//`
56			`// Revision 1.7 2001/10/14 13:12:10 lampret`
57			`// MP3 version.`
58			`//`
59			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
60			`// no message`
61			`//`
62			`// Revision 1.2 2001/08/09 13:39:33 lampret`
63			`// Major clean-up.`
64			`//`
65			`// Revision 1.1 2001/07/20 00:46:23 lampret`
66			`// Development version of RTL. Libraries are missing.`
67			`//`
68			`//`
69
70			`// synopsys translate_off`
71			`include "timescale.v"
72			`// synopsys translate_on`
73			`include "or1200_defines.v"
74
75			`module or1200_wbmux_cm2(`
76			`clk_i_cml_1,`
77
78			`// Clock and reset`
79			`clk, rst,`
80
81			`// Internal i/f`
82			`wb_freeze, rfwb_op,`
83			`muxin_a, muxin_b, muxin_c, muxin_d,`
84			`muxout, muxreg, muxreg_valid`
85			`);`
86
87
88			`input clk_i_cml_1;`
89			`reg [ 3 - 1 : 0 ] rfwb_op_cml_1;`
90			`reg [ 32 - 1 : 0 ] muxin_a_cml_1;`
91			`reg [ 32 - 1 : 0 ] muxreg_cml_1;`
92			`reg muxreg_valid_cml_1;`
93
94
95
96			parameter width = `OR1200_OPERAND_WIDTH;
97
98			`//`
99			`// I/O`
100			`//`
101
102			`//`
103			`// Clock and reset`
104			`//`
105			`input clk;`
106			`input rst;`
107
108			`//`
109			`// Internal i/f`
110			`//`
111			`input wb_freeze;`
112			input [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
113			`input [width-1:0] muxin_a;`
114			`input [width-1:0] muxin_b;`
115			`input [width-1:0] muxin_c;`
116			`input [width-1:0] muxin_d;`
117			`output [width-1:0] muxout;`
118			`output [width-1:0] muxreg;`
119			`output muxreg_valid;`
120
121			`//`
122			`// Internal wires and regs`
123			`//`
124			`reg [width-1:0] muxout;`
125			`reg [width-1:0] muxreg;`
126			`reg muxreg_valid;`
127
128			`//`
129			`// Registered output from the write-back multiplexer`
130			`//`
131
132			`// SynEDA CoreMultiplier`
133			`// assignment(s): muxreg, muxreg_valid`
134			`// replace(s): muxreg, rfwb_op, muxreg_valid`
135			`always @(posedge clk or posedge rst) begin`
136			`if (rst) begin`
137			`muxreg <= #1 32'd0;`
138			`muxreg_valid <= #1 1'b0;`
139			`end`
140			`else begin muxreg_valid <= muxreg_valid_cml_1; muxreg <= muxreg_cml_1; if (!wb_freeze) begin`
141			`muxreg <= #1 muxout;`
142			`muxreg_valid <= #1 rfwb_op_cml_1[0];`
143			`end end`
144			`end`
145
146			`//`
147			`// Write-back multiplexer`
148			`//`
149
150			`// SynEDA CoreMultiplier`
151			`// assignment(s): muxout`
152			`// replace(s): rfwb_op, muxin_a`
153			`always @(muxin_a_cml_1 or muxin_b or muxin_c or muxin_d or rfwb_op_cml_1) begin`
154			`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
155			case(rfwb_op_cml_1[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case infer_mux
156			`else
157			case(rfwb_op_cml_1[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case
158			`endif
159			`2'b00: muxout = muxin_a_cml_1;`
160			`2'b01: begin`
161			`muxout = muxin_b;`
162			`ifdef OR1200_VERBOSE
163			`// synopsys translate_off`
164			`$display(" WBMUX: muxin_b %h", muxin_b);`
165			`// synopsys translate_on`
166			`endif
167			`end`
168			`2'b10: begin`
169			`muxout = muxin_c;`
170			`ifdef OR1200_VERBOSE
171			`// synopsys translate_off`
172			`$display(" WBMUX: muxin_c %h", muxin_c);`
173			`// synopsys translate_on`
174			`endif
175			`end`
176			`2'b11: begin`
177			`muxout = muxin_d + 32'h8;`
178			`ifdef OR1200_VERBOSE
179			`// synopsys translate_off`
180			`$display(" WBMUX: muxin_d %h", muxin_d + 4'h8);`
181			`// synopsys translate_on`
182			`endif
183			`end`
184			`endcase`
185			`end`
186
187
188			`always @ (posedge clk_i_cml_1) begin`
189			`rfwb_op_cml_1 <= rfwb_op;`
190			`muxin_a_cml_1 <= muxin_a;`
191			`muxreg_cml_1 <= muxreg;`
192			`muxreg_valid_cml_1 <= muxreg_valid;`
193			`end`
194			`endmodule`
195

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[/] [or1200_hp/] [trunk/] [rtl/] [rtl_cm2/] [verilog/] [or1200_wbmux.v] - Blame information for rev 2