URL https://opencores.org/ocsvn/or1200_hp/or1200_hp/trunk

Subversion Repositories or1200_hp

[/] [or1200_hp/] [trunk/] [rtl/] [rtl_cm3/] [verilog/] [or1200_alu.v] - Blame information for rev 2

Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's ALU                                                ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  ALU                                                         ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.14  2004/06/08 18:17:36  lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.13  2004/05/09 19:49:03  lampret
// Added some l.cust5 custom instructions as example
//
// Revision 1.12  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
//
// Revision 1.11  2003/04/24 00:16:07  lampret
// No functional changes. Added defines to disable implementation of multiplier/MAC
//
// Revision 1.10  2002/09/08 05:52:16  lampret
// Added optional l.div/l.divu insns. By default they are disabled.
//
// Revision 1.9  2002/09/07 19:16:10  lampret
// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].
//
// Revision 1.8  2002/09/07 05:42:02  lampret
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
//
// Revision 1.7  2002/09/03 22:28:21  lampret
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
//
// Revision 1.6  2002/03/29 16:40:10  lampret
// Added a directive to ignore signed division variables that are only used in simulation.
//
// Revision 1.5  2002/03/29 16:33:59  lampret
// Added again just recently removed full_case directive
//
// Revision 1.4  2002/03/29 15:16:53  lampret
// Some of the warnings fixed.
//
// Revision 1.3  2002/01/28 01:15:59  lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10  2001/11/12 01:45:40  lampret
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
//
// Revision 1.9  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8  2001/10/19 23:28:45  lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_alu_cm3(
                clk_i_cml_1,
                clk_i_cml_2,
 
        a, b, mult_mac_result, macrc_op,
        alu_op, shrot_op, comp_op,
        cust5_op, cust5_limm,
        result, flagforw, flag_we,
        cyforw, cy_we, carry, flag
);
 
 
input clk_i_cml_1;
input clk_i_cml_2;
reg [ 32 - 1 : 0 ] a_cml_1;
reg [ 32 - 1 : 0 ] b_cml_1;
reg [ 32 - 1 : 0 ] mult_mac_result_cml_1;
reg  macrc_op_cml_1;
reg [ 4 - 1 : 0 ] alu_op_cml_2;
reg [ 4 - 1 : 0 ] alu_op_cml_1;
reg [ 4 - 1 : 0 ] comp_op_cml_2;
reg [ 4 - 1 : 0 ] comp_op_cml_1;
reg  carry_cml_1;
reg  flag_cml_1;
reg [ 32 - 1 : 0 ] shifted_rotated_cml_1;
reg [ 32 - 1 : 0 ] result_cust5_cml_1;
reg [ 32 - 1 : 0 ] comp_a_cml_2;
reg [ 32 - 1 : 0 ] comp_b_cml_2;
reg [ 32 - 1 : 0 ] result_sum_cml_1;
reg [ 32 - 1 : 0 ] result_and_cml_1;
reg [ 32 : 0 ] cy_sum_result_sum_cml_2;
reg [ 32 : 0 ] cy_sum_result_sum_cml_1;
reg [ 32 : 0 ] cy_csum_result_csum_cml_2;
 
 
 
parameter width = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
input   [width-1:0]              a;
input   [width-1:0]              b;
input   [width-1:0]              mult_mac_result;
input                           macrc_op;
input   [`OR1200_ALUOP_WIDTH-1:0]        alu_op;
input   [`OR1200_SHROTOP_WIDTH-1:0]      shrot_op;
input   [`OR1200_COMPOP_WIDTH-1:0]       comp_op;
input   [4:0]                    cust5_op;
input   [5:0]                    cust5_limm;
output  [width-1:0]              result;
output                          flagforw;
output                          flag_we;
output                          cyforw;
output                          cy_we;
input                           carry;
input         flag;
 
//
// Internal wires and regs
//
reg     [width-1:0]              result;
reg     [width-1:0]              shifted_rotated;
reg     [width-1:0]              result_cust5;
reg                             flagforw;
reg                             flagcomp;
reg                             flag_we;
reg                             cy_we;
wire    [width-1:0]              comp_a;
wire    [width-1:0]              comp_b;
`ifdef OR1200_IMPL_ALU_COMP1
wire                            a_eq_b;
wire                            a_lt_b;
`endif
wire    [width-1:0]              result_sum;
`ifdef OR1200_IMPL_ADDC
wire    [width-1:0]              result_csum;
wire                            cy_csum;
`endif
wire    [width-1:0]              result_and;
wire                            cy_sum;
reg                             cyforw;
 
//
// Combinatorial logic
//
 
// SynEDA CoreMultiplier
// assignment(s): comp_a
// replace(s): a, comp_op
assign comp_a = {a_cml_1[width-1] ^ comp_op_cml_1[3] , a_cml_1[width-2:0]};
 
// SynEDA CoreMultiplier
// assignment(s): comp_b
// replace(s): b, comp_op
assign comp_b = {b_cml_1[width-1] ^ comp_op_cml_1[3] , b_cml_1[width-2:0]};
`ifdef OR1200_IMPL_ALU_COMP1
assign a_eq_b = (comp_a == comp_b);
assign a_lt_b = (comp_a < comp_b);
`endif
wire    [width:0]                cy_sum_result_sum;
//assign {cy_sum, result_sum} = a + b;
assign cy_sum_result_sum = a + b;
 
// SynEDA CoreMultiplier
// assignment(s): cy_sum
// replace(s): cy_sum_result_sum
assign cy_sum = cy_sum_result_sum_cml_2[32];
assign result_sum = cy_sum_result_sum[31:0];
`ifdef OR1200_IMPL_ADDC
wire    [width:0]                cy_csum_result_csum;
//assign {cy_csum, result_csum} = a + b + {32'd0, carry};
 
// SynEDA CoreMultiplier
// assignment(s): cy_csum_result_csum
// replace(s): a, b, carry
assign cy_csum_result_csum = a_cml_1 + b_cml_1 + {32'd0, carry_cml_1};
 
// SynEDA CoreMultiplier
// assignment(s): cy_csum
// replace(s): cy_csum_result_csum
assign cy_csum = cy_csum_result_csum_cml_2[32];
assign result_csum = cy_csum_result_csum[31:0];
`endif
assign result_and = a & b;
 
//
// Simulation check for bad ALU behavior
//
`ifdef OR1200_WARNINGS
// synopsys translate_off
always @(result) begin
        if (result === 32'bx)
                $display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);
end
// synopsys translate_on
`endif
 
//
// Central part of the ALU
//
 
// SynEDA CoreMultiplier
// assignment(s): result
// replace(s): a, b, mult_mac_result, macrc_op, alu_op, flag, shifted_rotated, result_cust5, result_sum, result_and
always @(alu_op_cml_1 or a_cml_1 or b_cml_1 or result_sum_cml_1 or result_and_cml_1 or macrc_op_cml_1 or shifted_rotated_cml_1 or mult_mac_result_cml_1) begin
`ifdef OR1200_CASE_DEFAULT
        casex (alu_op_cml_1)            // synopsys parallel_case
`else
        casex (alu_op_cml_1)            // synopsys full_case parallel_case
`endif
    `OR1200_ALUOP_FF1: begin
        result = a_cml_1[0] ? 1 : a_cml_1[1] ? 2 : a_cml_1[2] ? 3 : a_cml_1[3] ? 4 : a_cml_1[4] ? 5 : a_cml_1[5] ? 6 : a_cml_1[6] ? 7 : a_cml_1[7] ? 8 : a_cml_1[8] ? 9 : a_cml_1[9] ? 10 : a_cml_1[10] ? 11 : a_cml_1[11] ? 12 : a_cml_1[12] ? 13 : a_cml_1[13] ? 14 : a_cml_1[14] ? 15 : a_cml_1[15] ? 16 : a_cml_1[16] ? 17 : a_cml_1[17] ? 18 : a_cml_1[18] ? 19 : a_cml_1[19] ? 20 : a_cml_1[20] ? 21 : a_cml_1[21] ? 22 : a_cml_1[22] ? 23 : a_cml_1[23] ? 24 : a_cml_1[24] ? 25 : a_cml_1[25] ? 26 : a_cml_1[26] ? 27 : a_cml_1[27] ? 28 : a_cml_1[28] ? 29 : a_cml_1[29] ? 30 : a_cml_1[30] ? 31 : a_cml_1[31] ? 32 : 0;
    end
                `OR1200_ALUOP_CUST5 : begin
                                result = result_cust5_cml_1;
                end
                `OR1200_ALUOP_SHROT : begin
                                result = shifted_rotated_cml_1;
                end
                `OR1200_ALUOP_ADD : begin
                                result = result_sum_cml_1;
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC : begin
                                result = result_csum;
                end
`endif
                `OR1200_ALUOP_SUB : begin
                                result = a_cml_1 - b_cml_1;
                end
                `OR1200_ALUOP_XOR : begin
                                result = a_cml_1 ^ b_cml_1;
                end
                `OR1200_ALUOP_OR  : begin
                                result = a_cml_1 | b_cml_1;
                end
                `OR1200_ALUOP_IMM : begin
                                result = b_cml_1;
                end
                `OR1200_ALUOP_MOVHI : begin
                                if (macrc_op_cml_1) begin
                                        result = mult_mac_result_cml_1;
                                end
                                else begin
                                        result = b_cml_1 << 16;
                                end
                end
`ifdef OR1200_MULT_IMPLEMENTED
`ifdef OR1200_IMPL_DIV
                `OR1200_ALUOP_DIV,
                `OR1200_ALUOP_DIVU,
`endif
                `OR1200_ALUOP_MUL : begin
                                result = mult_mac_result_cml_1;
                end
`endif
    `OR1200_ALUOP_CMOV: begin
        result = flag_cml_1 ? a_cml_1 : b_cml_1;
    end
 
`ifdef OR1200_CASE_DEFAULT
    default: begin
`else
    `OR1200_ALUOP_COMP, `OR1200_ALUOP_AND:
    begin
`endif
      result=result_and_cml_1;
    end
        endcase
end
 
//
// l.cust5 custom instructions
//
// Examples for move byte, set bit and clear bit
//
always @(cust5_op or cust5_limm or a or b) begin
        casex (cust5_op)                // synopsys parallel_case
                5'h1 : begin
                        casex (cust5_limm[1:0])
                                2'h0: result_cust5 = {a[31:8], b[7:0]};
                                2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};
                                2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};
                                2'h3: result_cust5 = {b[7:0], a[23:0]};
                        endcase
                end
                5'h2 :
                        result_cust5 = a | (1 << cust5_limm);
                5'h3 :
                        result_cust5 = a & (32'hffffffff ^ (1 << cust5_limm));
//
// *** Put here new l.cust5 custom instructions ***
//
                default: begin
                        result_cust5 = a;
                end
        endcase
end
 
//
// Generate flag and flag write enable
//
 
// SynEDA CoreMultiplier
// assignment(s): flagforw
// replace(s): alu_op
always @(alu_op_cml_2 or result_sum or result_and or flagcomp) begin
        casex (alu_op_cml_2)            // synopsys parallel_case
`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
                `OR1200_ALUOP_ADD : begin
                        flagforw = (result_sum == 32'h0000_0000);
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC : begin
                        flagforw = (result_csum == 32'h0000_0000);
                end
`endif
                `OR1200_ALUOP_AND: begin
                        flagforw = (result_and == 32'h0000_0000);
                end
`endif
                `OR1200_ALUOP_COMP: begin
                        flagforw = flagcomp;
                end
                default: begin
                        flagforw = 1'b0;
                end
        endcase
end
 
// SynEDA CoreMultiplier
// assignment(s): flag_we
// replace(s): alu_op
always @(alu_op_cml_1 or result_sum or result_and or flagcomp) begin
        casex (alu_op_cml_1)            // synopsys parallel_case
`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
                `OR1200_ALUOP_ADD : begin
                        flag_we = 1'b1;
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC : begin
                        flag_we = 1'b1;
                end
`endif
                `OR1200_ALUOP_AND: begin
                        flag_we = 1'b1;
                end
`endif
                `OR1200_ALUOP_COMP: begin
                        flag_we = 1'b1;
                end
                default: begin
                        flag_we = 1'b0;
                end
        endcase
end
 
//
// Generate SR[CY] write enable
//
 
// SynEDA CoreMultiplier
// assignment(s): cyforw
// replace(s): alu_op
always @(alu_op_cml_2 or cy_sum
`ifdef OR1200_IMPL_ADDC
        or cy_csum
`endif
        ) begin
        casex (alu_op_cml_2)            // synopsys parallel_case
`ifdef OR1200_IMPL_CY
                `OR1200_ALUOP_ADD : begin
                        cyforw = cy_sum;
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC: begin
                        cyforw = cy_csum;
                end
`endif
`endif
                default: begin
                        cyforw = 1'b0;
                end
        endcase
end
 
// SynEDA CoreMultiplier
// assignment(s): cy_we
// replace(s): alu_op
always @(alu_op_cml_1 or cy_sum
`ifdef OR1200_IMPL_ADDC
        or cy_csum
`endif
        ) begin
        casex (alu_op_cml_1)            // synopsys parallel_case
`ifdef OR1200_IMPL_CY
                `OR1200_ALUOP_ADD : begin
                        cy_we = 1'b1;
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC: begin
                        cy_we = 1'b1;
                end
`endif
`endif
                default: begin
                        cy_we = 1'b0;
                end
        endcase
end
 
//
// Shifts and rotation
//
always @(shrot_op or a or b) begin
        case (shrot_op)         // synopsys parallel_case
        `OR1200_SHROTOP_SLL :
                                shifted_rotated = (a << b[4:0]);
                `OR1200_SHROTOP_SRL :
                                shifted_rotated = (a >> b[4:0]);
 
`ifdef OR1200_IMPL_ALU_ROTATE
                `OR1200_SHROTOP_ROR :
                                shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) | (a >> b[4:0]);
`endif
                default:
                                shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) | a >> b[4:0];
        endcase
end
 
//
// First type of compare implementation
//
`ifdef OR1200_IMPL_ALU_COMP1
always @(comp_op_cml_2 or a_eq_b or a_lt_b) begin
        case(comp_op_cml_2[2:0]) // synopsys parallel_case
                `OR1200_COP_SFEQ:
                        flagcomp = a_eq_b;
                `OR1200_COP_SFNE:
                        flagcomp = ~a_eq_b;
                `OR1200_COP_SFGT:
                        flagcomp = ~(a_eq_b | a_lt_b);
                `OR1200_COP_SFGE:
                        flagcomp = ~a_lt_b;
                `OR1200_COP_SFLT:
                        flagcomp = a_lt_b;
                `OR1200_COP_SFLE:
                        flagcomp = a_eq_b | a_lt_b;
                default:
                        flagcomp = 1'b0;
        endcase
end
`endif
 
//
// Second type of compare implementation
//
`ifdef OR1200_IMPL_ALU_COMP2
 
// SynEDA CoreMultiplier
// assignment(s): flagcomp
// replace(s): comp_op, comp_a, comp_b
always @(comp_op_cml_2 or comp_a_cml_2 or comp_b_cml_2) begin
        case(comp_op_cml_2[2:0]) // synopsys parallel_case
                `OR1200_COP_SFEQ:
                        flagcomp = (comp_a_cml_2 == comp_b_cml_2);
                `OR1200_COP_SFNE:
                        flagcomp = (comp_a_cml_2 != comp_b_cml_2);
                `OR1200_COP_SFGT:
                        flagcomp = (comp_a_cml_2 > comp_b_cml_2);
                `OR1200_COP_SFGE:
                        flagcomp = (comp_a_cml_2 >= comp_b_cml_2);
                `OR1200_COP_SFLT:
                        flagcomp = (comp_a_cml_2 < comp_b_cml_2);
                `OR1200_COP_SFLE:
                        flagcomp = (comp_a_cml_2 <= comp_b_cml_2);
                default:
                        flagcomp = 1'b0;
        endcase
end
`endif
 
 
always @ (posedge clk_i_cml_1) begin
a_cml_1 <= a;
b_cml_1 <= b;
mult_mac_result_cml_1 <= mult_mac_result;
macrc_op_cml_1 <= macrc_op;
alu_op_cml_1 <= alu_op;
comp_op_cml_1 <= comp_op;
carry_cml_1 <= carry;
flag_cml_1 <= flag;
shifted_rotated_cml_1 <= shifted_rotated;
result_cust5_cml_1 <= result_cust5;
result_sum_cml_1 <= result_sum;
result_and_cml_1 <= result_and;
cy_sum_result_sum_cml_1 <= cy_sum_result_sum;
end
always @ (posedge clk_i_cml_2) begin
alu_op_cml_2 <= alu_op_cml_1;
comp_op_cml_2 <= comp_op_cml_1;
comp_a_cml_2 <= comp_a;
comp_b_cml_2 <= comp_b;
cy_sum_result_sum_cml_2 <= cy_sum_result_sum_cml_1;
cy_csum_result_csum_cml_2 <= cy_csum_result_csum;
end
endmodule
 

Browse

Tools

Subversion Repositories or1200_hp

[/] [or1200_hp/] [trunk/] [rtl/] [rtl_cm3/] [verilog/] [or1200_alu.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	tobil	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's ALU ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// ALU ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.14 2004/06/08 18:17:36 lampret`
48			`// Non-functional changes. Coding style fixes.`
49			`//`
50			`// Revision 1.13 2004/05/09 19:49:03 lampret`
51			`// Added some l.cust5 custom instructions as example`
52			`//`
53			`// Revision 1.12 2004/04/05 08:29:57 lampret`
54			`// Merged branch_qmem into main tree.`
55			`//`
56			`// Revision 1.11 2003/04/24 00:16:07 lampret`
57			`// No functional changes. Added defines to disable implementation of multiplier/MAC`
58			`//`
59			`// Revision 1.10 2002/09/08 05:52:16 lampret`
60			`// Added optional l.div/l.divu insns. By default they are disabled.`
61			`//`
62			`// Revision 1.9 2002/09/07 19:16:10 lampret`
63			`// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].`
64			`//`
65			`// Revision 1.8 2002/09/07 05:42:02 lampret`
66			`// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.`
67			`//`
68			`// Revision 1.7 2002/09/03 22:28:21 lampret`
69			`// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.`
70			`//`
71			`// Revision 1.6 2002/03/29 16:40:10 lampret`
72			`// Added a directive to ignore signed division variables that are only used in simulation.`
73			`//`
74			`// Revision 1.5 2002/03/29 16:33:59 lampret`
75			`// Added again just recently removed full_case directive`
76			`//`
77			`// Revision 1.4 2002/03/29 15:16:53 lampret`
78			`// Some of the warnings fixed.`
79			`//`
80			`// Revision 1.3 2002/01/28 01:15:59 lampret`
81			`// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.`
82			`//`
83			`// Revision 1.2 2002/01/14 06:18:22 lampret`
84			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
85			`//`
86			`// Revision 1.1 2002/01/03 08:16:15 lampret`
87			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
88			`//`
89			`// Revision 1.10 2001/11/12 01:45:40 lampret`
90			`// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.`
91			`//`
92			`// Revision 1.9 2001/10/21 17:57:16 lampret`
93			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
94			`//`
95			`// Revision 1.8 2001/10/19 23:28:45 lampret`
96			`// Fixed some synthesis warnings. Configured with caches and MMUs.`
97			`//`
98			`// Revision 1.7 2001/10/14 13:12:09 lampret`
99			`// MP3 version.`
100			`//`
101			`// Revision 1.1.1.1 2001/10/06 10:18:35 igorm`
102			`// no message`
103			`//`
104			`// Revision 1.2 2001/08/09 13:39:33 lampret`
105			`// Major clean-up.`
106			`//`
107			`// Revision 1.1 2001/07/20 00:46:03 lampret`
108			`// Development version of RTL. Libraries are missing.`
109			`//`
110			`//`
111
112			`// synopsys translate_off`
113			`include "timescale.v"
114			`// synopsys translate_on`
115			`include "or1200_defines.v"
116
117			`module or1200_alu_cm3(`
118			`clk_i_cml_1,`
119			`clk_i_cml_2,`
120
121			`a, b, mult_mac_result, macrc_op,`
122			`alu_op, shrot_op, comp_op,`
123			`cust5_op, cust5_limm,`
124			`result, flagforw, flag_we,`
125			`cyforw, cy_we, carry, flag`
126			`);`
127
128
129			`input clk_i_cml_1;`
130			`input clk_i_cml_2;`
131			`reg [ 32 - 1 : 0 ] a_cml_1;`
132			`reg [ 32 - 1 : 0 ] b_cml_1;`
133			`reg [ 32 - 1 : 0 ] mult_mac_result_cml_1;`
134			`reg macrc_op_cml_1;`
135			`reg [ 4 - 1 : 0 ] alu_op_cml_2;`
136			`reg [ 4 - 1 : 0 ] alu_op_cml_1;`
137			`reg [ 4 - 1 : 0 ] comp_op_cml_2;`
138			`reg [ 4 - 1 : 0 ] comp_op_cml_1;`
139			`reg carry_cml_1;`
140			`reg flag_cml_1;`
141			`reg [ 32 - 1 : 0 ] shifted_rotated_cml_1;`
142			`reg [ 32 - 1 : 0 ] result_cust5_cml_1;`
143			`reg [ 32 - 1 : 0 ] comp_a_cml_2;`
144			`reg [ 32 - 1 : 0 ] comp_b_cml_2;`
145			`reg [ 32 - 1 : 0 ] result_sum_cml_1;`
146			`reg [ 32 - 1 : 0 ] result_and_cml_1;`
147			`reg [ 32 : 0 ] cy_sum_result_sum_cml_2;`
148			`reg [ 32 : 0 ] cy_sum_result_sum_cml_1;`
149			`reg [ 32 : 0 ] cy_csum_result_csum_cml_2;`
150
151
152
153			parameter width = `OR1200_OPERAND_WIDTH;
154
155			`//`
156			`// I/O`
157			`//`
158			`input [width-1:0] a;`
159			`input [width-1:0] b;`
160			`input [width-1:0] mult_mac_result;`
161			`input macrc_op;`
162			input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
163			input [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
164			input [`OR1200_COMPOP_WIDTH-1:0] comp_op;
165			`input [4:0] cust5_op;`
166			`input [5:0] cust5_limm;`
167			`output [width-1:0] result;`
168			`output flagforw;`
169			`output flag_we;`
170			`output cyforw;`
171			`output cy_we;`
172			`input carry;`
173			`input flag;`
174
175			`//`
176			`// Internal wires and regs`
177			`//`
178			`reg [width-1:0] result;`
179			`reg [width-1:0] shifted_rotated;`
180			`reg [width-1:0] result_cust5;`
181			`reg flagforw;`
182			`reg flagcomp;`
183			`reg flag_we;`
184			`reg cy_we;`
185			`wire [width-1:0] comp_a;`
186			`wire [width-1:0] comp_b;`
187			`ifdef OR1200_IMPL_ALU_COMP1
188			`wire a_eq_b;`
189			`wire a_lt_b;`
190			`endif
191			`wire [width-1:0] result_sum;`
192			`ifdef OR1200_IMPL_ADDC
193			`wire [width-1:0] result_csum;`
194			`wire cy_csum;`
195			`endif
196			`wire [width-1:0] result_and;`
197			`wire cy_sum;`
198			`reg cyforw;`
199
200			`//`
201			`// Combinatorial logic`
202			`//`
203
204			`// SynEDA CoreMultiplier`
205			`// assignment(s): comp_a`
206			`// replace(s): a, comp_op`
207			`assign comp_a = {a_cml_1[width-1] ^ comp_op_cml_1[3] , a_cml_1[width-2:0]};`
208
209			`// SynEDA CoreMultiplier`
210			`// assignment(s): comp_b`
211			`// replace(s): b, comp_op`
212			`assign comp_b = {b_cml_1[width-1] ^ comp_op_cml_1[3] , b_cml_1[width-2:0]};`
213			`ifdef OR1200_IMPL_ALU_COMP1
214			`assign a_eq_b = (comp_a == comp_b);`
215			`assign a_lt_b = (comp_a < comp_b);`
216			`endif
217			`wire [width:0] cy_sum_result_sum;`
218			`//assign {cy_sum, result_sum} = a + b;`
219			`assign cy_sum_result_sum = a + b;`
220
221			`// SynEDA CoreMultiplier`
222			`// assignment(s): cy_sum`
223			`// replace(s): cy_sum_result_sum`
224			`assign cy_sum = cy_sum_result_sum_cml_2[32];`
225			`assign result_sum = cy_sum_result_sum[31:0];`
226			`ifdef OR1200_IMPL_ADDC
227			`wire [width:0] cy_csum_result_csum;`
228			`//assign {cy_csum, result_csum} = a + b + {32'd0, carry};`
229
230			`// SynEDA CoreMultiplier`
231			`// assignment(s): cy_csum_result_csum`
232			`// replace(s): a, b, carry`
233			`assign cy_csum_result_csum = a_cml_1 + b_cml_1 + {32'd0, carry_cml_1};`
234
235			`// SynEDA CoreMultiplier`
236			`// assignment(s): cy_csum`
237			`// replace(s): cy_csum_result_csum`
238			`assign cy_csum = cy_csum_result_csum_cml_2[32];`
239			`assign result_csum = cy_csum_result_csum[31:0];`
240			`endif
241			`assign result_and = a & b;`
242
243			`//`
244			`// Simulation check for bad ALU behavior`
245			`//`
246			`ifdef OR1200_WARNINGS
247			`// synopsys translate_off`
248			`always @(result) begin`
249			`if (result === 32'bx)`
250			`$display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);`
251			`end`
252			`// synopsys translate_on`
253			`endif
254
255			`//`
256			`// Central part of the ALU`
257			`//`
258
259			`// SynEDA CoreMultiplier`
260			`// assignment(s): result`
261			`// replace(s): a, b, mult_mac_result, macrc_op, alu_op, flag, shifted_rotated, result_cust5, result_sum, result_and`
262			`always @(alu_op_cml_1 or a_cml_1 or b_cml_1 or result_sum_cml_1 or result_and_cml_1 or macrc_op_cml_1 or shifted_rotated_cml_1 or mult_mac_result_cml_1) begin`
263			`ifdef OR1200_CASE_DEFAULT
264			`casex (alu_op_cml_1) // synopsys parallel_case`
265			`else
266			`casex (alu_op_cml_1) // synopsys full_case parallel_case`
267			`endif
268			`OR1200_ALUOP_FF1: begin
269			result = a_cml_1[0] ? 1 : a_cml_1[1] ? 2 : a_cml_1[2] ? 3 : a_cml_1[3] ? 4 : a_cml_1[4] ? 5 : a_cml_1[5] ? 6 : a_cml_1[6] ? 7 : a_cml_1[7] ? 8 : a_cml_1[8] ? 9 : a_cml_1[9] ? 10 : a_cml_1[10] ? 11 : a_cml_1[11] ? 12 : a_cml_1[12] ? 13 : a_cml_1[13] ? 14 : a_cml_1[14] ? 15 : a_cml_1[15] ? 16 : a_cml_1[16] ? 17 : a_cml_1[17] ? 18 : a_cml_1[18] ? 19 : a_cml_1[19] ? 20 : a_cml_1[20] ? 21 : a_cml_1[21] ? 22 : a_cml_1[22] ? 23 : a_cml_1[23] ? 24 : a_cml_1[24] ? 25 : a_cml_1[25] ? 26 : a_cml_1[26] ? 27 : a_cml_1[27] ? 28 : a_cml_1[28] ? 29 : a_cml_1[29] ? 30 : a_cml_1[30] ? 31 : a_cml_1[31] ? 32 : 0;
270			`end`
271			`OR1200_ALUOP_CUST5 : begin
272			`result = result_cust5_cml_1;`
273			`end`
274			`OR1200_ALUOP_SHROT : begin
275			`result = shifted_rotated_cml_1;`
276			`end`
277			`OR1200_ALUOP_ADD : begin
278			`result = result_sum_cml_1;`
279			`end`
280			`ifdef OR1200_IMPL_ADDC
281			`OR1200_ALUOP_ADDC : begin
282			`result = result_csum;`
283			`end`
284			`endif
285			`OR1200_ALUOP_SUB : begin
286			`result = a_cml_1 - b_cml_1;`
287			`end`
288			`OR1200_ALUOP_XOR : begin
289			`result = a_cml_1 ^ b_cml_1;`
290			`end`
291			`OR1200_ALUOP_OR : begin
292			`result = a_cml_1 \| b_cml_1;`
293			`end`
294			`OR1200_ALUOP_IMM : begin
295			`result = b_cml_1;`
296			`end`
297			`OR1200_ALUOP_MOVHI : begin
298			`if (macrc_op_cml_1) begin`
299			`result = mult_mac_result_cml_1;`
300			`end`
301			`else begin`
302			`result = b_cml_1 << 16;`
303			`end`
304			`end`
305			`ifdef OR1200_MULT_IMPLEMENTED
306			`ifdef OR1200_IMPL_DIV
307			`OR1200_ALUOP_DIV,
308			`OR1200_ALUOP_DIVU,
309			`endif
310			`OR1200_ALUOP_MUL : begin
311			`result = mult_mac_result_cml_1;`
312			`end`
313			`endif
314			`OR1200_ALUOP_CMOV: begin
315			`result = flag_cml_1 ? a_cml_1 : b_cml_1;`
316			`end`
317
318			`ifdef OR1200_CASE_DEFAULT
319			`default: begin`
320			`else
321			`OR1200_ALUOP_COMP, `OR1200_ALUOP_AND:
322			`begin`
323			`endif
324			`result=result_and_cml_1;`
325			`end`
326			`endcase`
327			`end`
328
329			`//`
330			`// l.cust5 custom instructions`
331			`//`
332			`// Examples for move byte, set bit and clear bit`
333			`//`
334			`always @(cust5_op or cust5_limm or a or b) begin`
335			`casex (cust5_op) // synopsys parallel_case`
336			`5'h1 : begin`
337			`casex (cust5_limm[1:0])`
338			`2'h0: result_cust5 = {a[31:8], b[7:0]};`
339			`2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};`
340			`2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};`
341			`2'h3: result_cust5 = {b[7:0], a[23:0]};`
342			`endcase`
343			`end`
344			`5'h2 :`
345			`result_cust5 = a \| (1 << cust5_limm);`
346			`5'h3 :`
347			`result_cust5 = a & (32'hffffffff ^ (1 << cust5_limm));`
348			`//`
349			`// * Put here new l.cust5 custom instructions *`
350			`//`
351			`default: begin`
352			`result_cust5 = a;`
353			`end`
354			`endcase`
355			`end`
356
357			`//`
358			`// Generate flag and flag write enable`
359			`//`
360
361			`// SynEDA CoreMultiplier`
362			`// assignment(s): flagforw`
363			`// replace(s): alu_op`
364			`always @(alu_op_cml_2 or result_sum or result_and or flagcomp) begin`
365			`casex (alu_op_cml_2) // synopsys parallel_case`
366			`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
367			`OR1200_ALUOP_ADD : begin
368			`flagforw = (result_sum == 32'h0000_0000);`
369			`end`
370			`ifdef OR1200_IMPL_ADDC
371			`OR1200_ALUOP_ADDC : begin
372			`flagforw = (result_csum == 32'h0000_0000);`
373			`end`
374			`endif
375			`OR1200_ALUOP_AND: begin
376			`flagforw = (result_and == 32'h0000_0000);`
377			`end`
378			`endif
379			`OR1200_ALUOP_COMP: begin
380			`flagforw = flagcomp;`
381			`end`
382			`default: begin`
383			`flagforw = 1'b0;`
384			`end`
385			`endcase`
386			`end`
387
388			`// SynEDA CoreMultiplier`
389			`// assignment(s): flag_we`
390			`// replace(s): alu_op`
391			`always @(alu_op_cml_1 or result_sum or result_and or flagcomp) begin`
392			`casex (alu_op_cml_1) // synopsys parallel_case`
393			`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
394			`OR1200_ALUOP_ADD : begin
395			`flag_we = 1'b1;`
396			`end`
397			`ifdef OR1200_IMPL_ADDC
398			`OR1200_ALUOP_ADDC : begin
399			`flag_we = 1'b1;`
400			`end`
401			`endif
402			`OR1200_ALUOP_AND: begin
403			`flag_we = 1'b1;`
404			`end`
405			`endif
406			`OR1200_ALUOP_COMP: begin
407			`flag_we = 1'b1;`
408			`end`
409			`default: begin`
410			`flag_we = 1'b0;`
411			`end`
412			`endcase`
413			`end`
414
415			`//`
416			`// Generate SR[CY] write enable`
417			`//`
418
419			`// SynEDA CoreMultiplier`
420			`// assignment(s): cyforw`
421			`// replace(s): alu_op`
422			`always @(alu_op_cml_2 or cy_sum`
423			`ifdef OR1200_IMPL_ADDC
424			`or cy_csum`
425			`endif
426			`) begin`
427			`casex (alu_op_cml_2) // synopsys parallel_case`
428			`ifdef OR1200_IMPL_CY
429			`OR1200_ALUOP_ADD : begin
430			`cyforw = cy_sum;`
431			`end`
432			`ifdef OR1200_IMPL_ADDC
433			`OR1200_ALUOP_ADDC: begin
434			`cyforw = cy_csum;`
435			`end`
436			`endif
437			`endif
438			`default: begin`
439			`cyforw = 1'b0;`
440			`end`
441			`endcase`
442			`end`
443
444			`// SynEDA CoreMultiplier`
445			`// assignment(s): cy_we`
446			`// replace(s): alu_op`
447			`always @(alu_op_cml_1 or cy_sum`
448			`ifdef OR1200_IMPL_ADDC
449			`or cy_csum`
450			`endif
451			`) begin`
452			`casex (alu_op_cml_1) // synopsys parallel_case`
453			`ifdef OR1200_IMPL_CY
454			`OR1200_ALUOP_ADD : begin
455			`cy_we = 1'b1;`
456			`end`
457			`ifdef OR1200_IMPL_ADDC
458			`OR1200_ALUOP_ADDC: begin
459			`cy_we = 1'b1;`
460			`end`
461			`endif
462			`endif
463			`default: begin`
464			`cy_we = 1'b0;`
465			`end`
466			`endcase`
467			`end`
468
469			`//`
470			`// Shifts and rotation`
471			`//`
472			`always @(shrot_op or a or b) begin`
473			`case (shrot_op) // synopsys parallel_case`
474			`OR1200_SHROTOP_SLL :
475			`shifted_rotated = (a << b[4:0]);`
476			`OR1200_SHROTOP_SRL :
477			`shifted_rotated = (a >> b[4:0]);`
478
479			`ifdef OR1200_IMPL_ALU_ROTATE
480			`OR1200_SHROTOP_ROR :
481			`shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) \| (a >> b[4:0]);`
482			`endif
483			`default:`
484			`shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) \| a >> b[4:0];`
485			`endcase`
486			`end`
487
488			`//`
489			`// First type of compare implementation`
490			`//`
491			`ifdef OR1200_IMPL_ALU_COMP1
492			`always @(comp_op_cml_2 or a_eq_b or a_lt_b) begin`
493			`case(comp_op_cml_2[2:0]) // synopsys parallel_case`
494			`OR1200_COP_SFEQ:
495			`flagcomp = a_eq_b;`
496			`OR1200_COP_SFNE:
497			`flagcomp = ~a_eq_b;`
498			`OR1200_COP_SFGT:
499			`flagcomp = ~(a_eq_b \| a_lt_b);`
500			`OR1200_COP_SFGE:
501			`flagcomp = ~a_lt_b;`
502			`OR1200_COP_SFLT:
503			`flagcomp = a_lt_b;`
504			`OR1200_COP_SFLE:
505			`flagcomp = a_eq_b \| a_lt_b;`
506			`default:`
507			`flagcomp = 1'b0;`
508			`endcase`
509			`end`
510			`endif
511
512			`//`
513			`// Second type of compare implementation`
514			`//`
515			`ifdef OR1200_IMPL_ALU_COMP2
516
517			`// SynEDA CoreMultiplier`
518			`// assignment(s): flagcomp`
519			`// replace(s): comp_op, comp_a, comp_b`
520			`always @(comp_op_cml_2 or comp_a_cml_2 or comp_b_cml_2) begin`
521			`case(comp_op_cml_2[2:0]) // synopsys parallel_case`
522			`OR1200_COP_SFEQ:
523			`flagcomp = (comp_a_cml_2 == comp_b_cml_2);`
524			`OR1200_COP_SFNE:
525			`flagcomp = (comp_a_cml_2 != comp_b_cml_2);`
526			`OR1200_COP_SFGT:
527			`flagcomp = (comp_a_cml_2 > comp_b_cml_2);`
528			`OR1200_COP_SFGE:
529			`flagcomp = (comp_a_cml_2 >= comp_b_cml_2);`
530			`OR1200_COP_SFLT:
531			`flagcomp = (comp_a_cml_2 < comp_b_cml_2);`
532			`OR1200_COP_SFLE:
533			`flagcomp = (comp_a_cml_2 <= comp_b_cml_2);`
534			`default:`
535			`flagcomp = 1'b0;`
536			`endcase`
537			`end`
538			`endif
539
540
541			`always @ (posedge clk_i_cml_1) begin`
542			`a_cml_1 <= a;`
543			`b_cml_1 <= b;`
544			`mult_mac_result_cml_1 <= mult_mac_result;`
545			`macrc_op_cml_1 <= macrc_op;`
546			`alu_op_cml_1 <= alu_op;`
547			`comp_op_cml_1 <= comp_op;`
548			`carry_cml_1 <= carry;`
549			`flag_cml_1 <= flag;`
550			`shifted_rotated_cml_1 <= shifted_rotated;`
551			`result_cust5_cml_1 <= result_cust5;`
552			`result_sum_cml_1 <= result_sum;`
553			`result_and_cml_1 <= result_and;`
554			`cy_sum_result_sum_cml_1 <= cy_sum_result_sum;`
555			`end`
556			`always @ (posedge clk_i_cml_2) begin`
557			`alu_op_cml_2 <= alu_op_cml_1;`
558			`comp_op_cml_2 <= comp_op_cml_1;`
559			`comp_a_cml_2 <= comp_a;`
560			`comp_b_cml_2 <= comp_b;`
561			`cy_sum_result_sum_cml_2 <= cy_sum_result_sum_cml_1;`
562			`cy_csum_result_csum_cml_2 <= cy_csum_result_csum;`
563			`end`
564			`endmodule`
565