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[/] [or1200_hp/] [trunk/] [rtl/] [rtl_cm4/] [verilog/] [or1200_alu.v] - Blame information for rev 2

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's ALU                                                ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  ALU                                                         ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.14  2004/06/08 18:17:36  lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.13  2004/05/09 19:49:03  lampret
// Added some l.cust5 custom instructions as example
//
// Revision 1.12  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
//
// Revision 1.11  2003/04/24 00:16:07  lampret
// No functional changes. Added defines to disable implementation of multiplier/MAC
//
// Revision 1.10  2002/09/08 05:52:16  lampret
// Added optional l.div/l.divu insns. By default they are disabled.
//
// Revision 1.9  2002/09/07 19:16:10  lampret
// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].
//
// Revision 1.8  2002/09/07 05:42:02  lampret
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
//
// Revision 1.7  2002/09/03 22:28:21  lampret
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
//
// Revision 1.6  2002/03/29 16:40:10  lampret
// Added a directive to ignore signed division variables that are only used in simulation.
//
// Revision 1.5  2002/03/29 16:33:59  lampret
// Added again just recently removed full_case directive
//
// Revision 1.4  2002/03/29 15:16:53  lampret
// Some of the warnings fixed.
//
// Revision 1.3  2002/01/28 01:15:59  lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10  2001/11/12 01:45:40  lampret
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
//
// Revision 1.9  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8  2001/10/19 23:28:45  lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_alu_cm4(
                clk_i_cml_1,
 
        a, b, mult_mac_result, macrc_op,
        alu_op, shrot_op, comp_op,
        cust5_op, cust5_limm,
        result, flagforw, flag_we,
        cyforw, cy_we, carry, flag
);
 
 
input clk_i_cml_1;
reg [ 32 - 1 : 0 ] a_cml_1;
reg [ 32 - 1 : 0 ] b_cml_1;
reg [ 32 - 1 : 0 ] mult_mac_result_cml_1;
reg  macrc_op_cml_1;
reg [ 4 - 1 : 0 ] alu_op_cml_1;
reg [ 4 - 1 : 0 ] comp_op_cml_1;
reg  flag_cml_1;
reg [ 32 - 1 : 0 ] shifted_rotated_cml_1;
reg [ 32 - 1 : 0 ] result_cust5_cml_1;
reg [ 32 - 1 : 0 ] result_sum_cml_1;
reg [ 32 - 1 : 0 ] result_csum_cml_1;
reg [ 32 - 1 : 0 ] result_and_cml_1;
reg [ 32 : 0 ] cy_sum_result_sum_cml_1;
reg [ 32 : 0 ] cy_csum_result_csum_cml_1;
 
 
 
parameter width = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
input   [width-1:0]              a;
input   [width-1:0]              b;
input   [width-1:0]              mult_mac_result;
input                           macrc_op;
input   [`OR1200_ALUOP_WIDTH-1:0]        alu_op;
input   [`OR1200_SHROTOP_WIDTH-1:0]      shrot_op;
input   [`OR1200_COMPOP_WIDTH-1:0]       comp_op;
input   [4:0]                    cust5_op;
input   [5:0]                    cust5_limm;
output  [width-1:0]              result;
output                          flagforw;
output                          flag_we;
output                          cyforw;
output                          cy_we;
input                           carry;
input         flag;
 
//
// Internal wires and regs
//
reg     [width-1:0]              result;
reg     [width-1:0]              shifted_rotated;
reg     [width-1:0]              result_cust5;
reg                             flagforw;
reg                             flagcomp;
reg                             flag_we;
reg                             cy_we;
wire    [width-1:0]              comp_a;
wire    [width-1:0]              comp_b;
`ifdef OR1200_IMPL_ALU_COMP1
wire                            a_eq_b;
wire                            a_lt_b;
`endif
wire    [width-1:0]              result_sum;
`ifdef OR1200_IMPL_ADDC
wire    [width-1:0]              result_csum;
wire                            cy_csum;
`endif
wire    [width-1:0]              result_and;
wire                            cy_sum;
reg                             cyforw;
 
//
// Combinatorial logic
//
 
// SynEDA CoreMultiplier
// assignment(s): comp_a
// replace(s): a, comp_op
assign comp_a = {a_cml_1[width-1] ^ comp_op_cml_1[3] , a_cml_1[width-2:0]};
 
// SynEDA CoreMultiplier
// assignment(s): comp_b
// replace(s): b, comp_op
assign comp_b = {b_cml_1[width-1] ^ comp_op_cml_1[3] , b_cml_1[width-2:0]};
`ifdef OR1200_IMPL_ALU_COMP1
assign a_eq_b = (comp_a == comp_b);
assign a_lt_b = (comp_a < comp_b);
`endif
wire    [width:0]                cy_sum_result_sum;
//assign {cy_sum, result_sum} = a + b;
assign cy_sum_result_sum = a + b;
 
// SynEDA CoreMultiplier
// assignment(s): cy_sum
// replace(s): cy_sum_result_sum
assign cy_sum = cy_sum_result_sum_cml_1[32];
assign result_sum = cy_sum_result_sum[31:0];
`ifdef OR1200_IMPL_ADDC
wire    [width:0]                cy_csum_result_csum;
//assign {cy_csum, result_csum} = a + b + {32'd0, carry};
assign cy_csum_result_csum = a + b + {32'd0, carry};
 
// SynEDA CoreMultiplier
// assignment(s): cy_csum
// replace(s): cy_csum_result_csum
assign cy_csum = cy_csum_result_csum_cml_1[32];
assign result_csum = cy_csum_result_csum[31:0];
`endif
assign result_and = a & b;
 
//
// Simulation check for bad ALU behavior
//
`ifdef OR1200_WARNINGS
// synopsys translate_off
always @(result) begin
        if (result === 32'bx)
                $display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);
end
// synopsys translate_on
`endif
 
//
// Central part of the ALU
//
 
// SynEDA CoreMultiplier
// assignment(s): result
// replace(s): a, b, mult_mac_result, macrc_op, alu_op, flag, shifted_rotated, result_cust5, result_sum, result_csum, result_and
always @(alu_op_cml_1 or a_cml_1 or b_cml_1 or result_sum_cml_1 or result_and_cml_1 or macrc_op_cml_1 or shifted_rotated_cml_1 or mult_mac_result_cml_1) begin
`ifdef OR1200_CASE_DEFAULT
        casex (alu_op_cml_1)            // synopsys parallel_case
`else
        casex (alu_op_cml_1)            // synopsys full_case parallel_case
`endif
    `OR1200_ALUOP_FF1: begin
        result = a_cml_1[0] ? 1 : a_cml_1[1] ? 2 : a_cml_1[2] ? 3 : a_cml_1[3] ? 4 : a_cml_1[4] ? 5 : a_cml_1[5] ? 6 : a_cml_1[6] ? 7 : a_cml_1[7] ? 8 : a_cml_1[8] ? 9 : a_cml_1[9] ? 10 : a_cml_1[10] ? 11 : a_cml_1[11] ? 12 : a_cml_1[12] ? 13 : a_cml_1[13] ? 14 : a_cml_1[14] ? 15 : a_cml_1[15] ? 16 : a_cml_1[16] ? 17 : a_cml_1[17] ? 18 : a_cml_1[18] ? 19 : a_cml_1[19] ? 20 : a_cml_1[20] ? 21 : a_cml_1[21] ? 22 : a_cml_1[22] ? 23 : a_cml_1[23] ? 24 : a_cml_1[24] ? 25 : a_cml_1[25] ? 26 : a_cml_1[26] ? 27 : a_cml_1[27] ? 28 : a_cml_1[28] ? 29 : a_cml_1[29] ? 30 : a_cml_1[30] ? 31 : a_cml_1[31] ? 32 : 0;
    end
                `OR1200_ALUOP_CUST5 : begin
                                result = result_cust5_cml_1;
                end
                `OR1200_ALUOP_SHROT : begin
                                result = shifted_rotated_cml_1;
                end
                `OR1200_ALUOP_ADD : begin
                                result = result_sum_cml_1;
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC : begin
                                result = result_csum_cml_1;
                end
`endif
                `OR1200_ALUOP_SUB : begin
                                result = a_cml_1 - b_cml_1;
                end
                `OR1200_ALUOP_XOR : begin
                                result = a_cml_1 ^ b_cml_1;
                end
                `OR1200_ALUOP_OR  : begin
                                result = a_cml_1 | b_cml_1;
                end
                `OR1200_ALUOP_IMM : begin
                                result = b_cml_1;
                end
                `OR1200_ALUOP_MOVHI : begin
                                if (macrc_op_cml_1) begin
                                        result = mult_mac_result_cml_1;
                                end
                                else begin
                                        result = b_cml_1 << 16;
                                end
                end
`ifdef OR1200_MULT_IMPLEMENTED
`ifdef OR1200_IMPL_DIV
                `OR1200_ALUOP_DIV,
                `OR1200_ALUOP_DIVU,
`endif
                `OR1200_ALUOP_MUL : begin
                                result = mult_mac_result_cml_1;
                end
`endif
    `OR1200_ALUOP_CMOV: begin
        result = flag_cml_1 ? a_cml_1 : b_cml_1;
    end
 
`ifdef OR1200_CASE_DEFAULT
    default: begin
`else
    `OR1200_ALUOP_COMP, `OR1200_ALUOP_AND:
    begin
`endif
      result=result_and_cml_1;
    end
        endcase
end
 
//
// l.cust5 custom instructions
//
// Examples for move byte, set bit and clear bit
//
always @(cust5_op or cust5_limm or a or b) begin
        casex (cust5_op)                // synopsys parallel_case
                5'h1 : begin
                        casex (cust5_limm[1:0])
                                2'h0: result_cust5 = {a[31:8], b[7:0]};
                                2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};
                                2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};
                                2'h3: result_cust5 = {b[7:0], a[23:0]};
                        endcase
                end
                5'h2 :
                        result_cust5 = a | (1 << cust5_limm);
                5'h3 :
                        result_cust5 = a & (32'hffffffff ^ (1 << cust5_limm));
//
// *** Put here new l.cust5 custom instructions ***
//
                default: begin
                        result_cust5 = a;
                end
        endcase
end
 
//
// Generate flag and flag write enable
//
 
// SynEDA CoreMultiplier
// assignment(s): flagforw
// replace(s): alu_op
always @(alu_op_cml_1 or result_sum or result_and or flagcomp) begin
        casex (alu_op_cml_1)            // synopsys parallel_case
`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
                `OR1200_ALUOP_ADD : begin
                        flagforw = (result_sum == 32'h0000_0000);
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC : begin
                        flagforw = (result_csum == 32'h0000_0000);
                end
`endif
                `OR1200_ALUOP_AND: begin
                        flagforw = (result_and == 32'h0000_0000);
                end
`endif
                `OR1200_ALUOP_COMP: begin
                        flagforw = flagcomp;
                end
                default: begin
                        flagforw = 1'b0;
                end
        endcase
end
 
// SynEDA CoreMultiplier
// assignment(s): flag_we
// replace(s): alu_op
always @(alu_op_cml_1 or result_sum or result_and or flagcomp) begin
        casex (alu_op_cml_1)            // synopsys parallel_case
`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
                `OR1200_ALUOP_ADD : begin
                        flag_we = 1'b1;
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC : begin
                        flag_we = 1'b1;
                end
`endif
                `OR1200_ALUOP_AND: begin
                        flag_we = 1'b1;
                end
`endif
                `OR1200_ALUOP_COMP: begin
                        flag_we = 1'b1;
                end
                default: begin
                        flag_we = 1'b0;
                end
        endcase
end
 
//
// Generate SR[CY] write enable
//
 
// SynEDA CoreMultiplier
// assignment(s): cyforw
// replace(s): alu_op
always @(alu_op_cml_1 or cy_sum
`ifdef OR1200_IMPL_ADDC
        or cy_csum
`endif
        ) begin
        casex (alu_op_cml_1)            // synopsys parallel_case
`ifdef OR1200_IMPL_CY
                `OR1200_ALUOP_ADD : begin
                        cyforw = cy_sum;
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC: begin
                        cyforw = cy_csum;
                end
`endif
`endif
                default: begin
                        cyforw = 1'b0;
                end
        endcase
end
 
// SynEDA CoreMultiplier
// assignment(s): cy_we
// replace(s): alu_op
always @(alu_op_cml_1 or cy_sum
`ifdef OR1200_IMPL_ADDC
        or cy_csum
`endif
        ) begin
        casex (alu_op_cml_1)            // synopsys parallel_case
`ifdef OR1200_IMPL_CY
                `OR1200_ALUOP_ADD : begin
                        cy_we = 1'b1;
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC: begin
                        cy_we = 1'b1;
                end
`endif
`endif
                default: begin
                        cy_we = 1'b0;
                end
        endcase
end
 
//
// Shifts and rotation
//
always @(shrot_op or a or b) begin
        case (shrot_op)         // synopsys parallel_case
        `OR1200_SHROTOP_SLL :
                                shifted_rotated = (a << b[4:0]);
                `OR1200_SHROTOP_SRL :
                                shifted_rotated = (a >> b[4:0]);
 
`ifdef OR1200_IMPL_ALU_ROTATE
                `OR1200_SHROTOP_ROR :
                                shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) | (a >> b[4:0]);
`endif
                default:
                                shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) | a >> b[4:0];
        endcase
end
 
//
// First type of compare implementation
//
`ifdef OR1200_IMPL_ALU_COMP1
always @(comp_op_cml_1 or a_eq_b or a_lt_b) begin
        case(comp_op_cml_1[2:0]) // synopsys parallel_case
                `OR1200_COP_SFEQ:
                        flagcomp = a_eq_b;
                `OR1200_COP_SFNE:
                        flagcomp = ~a_eq_b;
                `OR1200_COP_SFGT:
                        flagcomp = ~(a_eq_b | a_lt_b);
                `OR1200_COP_SFGE:
                        flagcomp = ~a_lt_b;
                `OR1200_COP_SFLT:
                        flagcomp = a_lt_b;
                `OR1200_COP_SFLE:
                        flagcomp = a_eq_b | a_lt_b;
                default:
                        flagcomp = 1'b0;
        endcase
end
`endif
 
//
// Second type of compare implementation
//
`ifdef OR1200_IMPL_ALU_COMP2
 
// SynEDA CoreMultiplier
// assignment(s): flagcomp
// replace(s): comp_op
always @(comp_op_cml_1 or comp_a or comp_b) begin
        case(comp_op_cml_1[2:0]) // synopsys parallel_case
                `OR1200_COP_SFEQ:
                        flagcomp = (comp_a == comp_b);
                `OR1200_COP_SFNE:
                        flagcomp = (comp_a != comp_b);
                `OR1200_COP_SFGT:
                        flagcomp = (comp_a > comp_b);
                `OR1200_COP_SFGE:
                        flagcomp = (comp_a >= comp_b);
                `OR1200_COP_SFLT:
                        flagcomp = (comp_a < comp_b);
                `OR1200_COP_SFLE:
                        flagcomp = (comp_a <= comp_b);
                default:
                        flagcomp = 1'b0;
        endcase
end
`endif
 
 
always @ (posedge clk_i_cml_1) begin
a_cml_1 <= a;
b_cml_1 <= b;
mult_mac_result_cml_1 <= mult_mac_result;
macrc_op_cml_1 <= macrc_op;
alu_op_cml_1 <= alu_op;
comp_op_cml_1 <= comp_op;
flag_cml_1 <= flag;
shifted_rotated_cml_1 <= shifted_rotated;
result_cust5_cml_1 <= result_cust5;
result_sum_cml_1 <= result_sum;
result_csum_cml_1 <= result_csum;
result_and_cml_1 <= result_and;
cy_sum_result_sum_cml_1 <= cy_sum_result_sum;
cy_csum_result_csum_cml_1 <= cy_csum_result_csum;
end
endmodule
 

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[/] [or1200_hp/] [trunk/] [rtl/] [rtl_cm4/] [verilog/] [or1200_alu.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	tobil	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's ALU ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// ALU ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.14 2004/06/08 18:17:36 lampret`
48			`// Non-functional changes. Coding style fixes.`
49			`//`
50			`// Revision 1.13 2004/05/09 19:49:03 lampret`
51			`// Added some l.cust5 custom instructions as example`
52			`//`
53			`// Revision 1.12 2004/04/05 08:29:57 lampret`
54			`// Merged branch_qmem into main tree.`
55			`//`
56			`// Revision 1.11 2003/04/24 00:16:07 lampret`
57			`// No functional changes. Added defines to disable implementation of multiplier/MAC`
58			`//`
59			`// Revision 1.10 2002/09/08 05:52:16 lampret`
60			`// Added optional l.div/l.divu insns. By default they are disabled.`
61			`//`
62			`// Revision 1.9 2002/09/07 19:16:10 lampret`
63			`// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].`
64			`//`
65			`// Revision 1.8 2002/09/07 05:42:02 lampret`
66			`// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.`
67			`//`
68			`// Revision 1.7 2002/09/03 22:28:21 lampret`
69			`// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.`
70			`//`
71			`// Revision 1.6 2002/03/29 16:40:10 lampret`
72			`// Added a directive to ignore signed division variables that are only used in simulation.`
73			`//`
74			`// Revision 1.5 2002/03/29 16:33:59 lampret`
75			`// Added again just recently removed full_case directive`
76			`//`
77			`// Revision 1.4 2002/03/29 15:16:53 lampret`
78			`// Some of the warnings fixed.`
79			`//`
80			`// Revision 1.3 2002/01/28 01:15:59 lampret`
81			`// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.`
82			`//`
83			`// Revision 1.2 2002/01/14 06:18:22 lampret`
84			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
85			`//`
86			`// Revision 1.1 2002/01/03 08:16:15 lampret`
87			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
88			`//`
89			`// Revision 1.10 2001/11/12 01:45:40 lampret`
90			`// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.`
91			`//`
92			`// Revision 1.9 2001/10/21 17:57:16 lampret`
93			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
94			`//`
95			`// Revision 1.8 2001/10/19 23:28:45 lampret`
96			`// Fixed some synthesis warnings. Configured with caches and MMUs.`
97			`//`
98			`// Revision 1.7 2001/10/14 13:12:09 lampret`
99			`// MP3 version.`
100			`//`
101			`// Revision 1.1.1.1 2001/10/06 10:18:35 igorm`
102			`// no message`
103			`//`
104			`// Revision 1.2 2001/08/09 13:39:33 lampret`
105			`// Major clean-up.`
106			`//`
107			`// Revision 1.1 2001/07/20 00:46:03 lampret`
108			`// Development version of RTL. Libraries are missing.`
109			`//`
110			`//`
111
112			`// synopsys translate_off`
113			`include "timescale.v"
114			`// synopsys translate_on`
115			`include "or1200_defines.v"
116
117			`module or1200_alu_cm4(`
118			`clk_i_cml_1,`
119
120			`a, b, mult_mac_result, macrc_op,`
121			`alu_op, shrot_op, comp_op,`
122			`cust5_op, cust5_limm,`
123			`result, flagforw, flag_we,`
124			`cyforw, cy_we, carry, flag`
125			`);`
126
127
128			`input clk_i_cml_1;`
129			`reg [ 32 - 1 : 0 ] a_cml_1;`
130			`reg [ 32 - 1 : 0 ] b_cml_1;`
131			`reg [ 32 - 1 : 0 ] mult_mac_result_cml_1;`
132			`reg macrc_op_cml_1;`
133			`reg [ 4 - 1 : 0 ] alu_op_cml_1;`
134			`reg [ 4 - 1 : 0 ] comp_op_cml_1;`
135			`reg flag_cml_1;`
136			`reg [ 32 - 1 : 0 ] shifted_rotated_cml_1;`
137			`reg [ 32 - 1 : 0 ] result_cust5_cml_1;`
138			`reg [ 32 - 1 : 0 ] result_sum_cml_1;`
139			`reg [ 32 - 1 : 0 ] result_csum_cml_1;`
140			`reg [ 32 - 1 : 0 ] result_and_cml_1;`
141			`reg [ 32 : 0 ] cy_sum_result_sum_cml_1;`
142			`reg [ 32 : 0 ] cy_csum_result_csum_cml_1;`
143
144
145
146			parameter width = `OR1200_OPERAND_WIDTH;
147
148			`//`
149			`// I/O`
150			`//`
151			`input [width-1:0] a;`
152			`input [width-1:0] b;`
153			`input [width-1:0] mult_mac_result;`
154			`input macrc_op;`
155			input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
156			input [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
157			input [`OR1200_COMPOP_WIDTH-1:0] comp_op;
158			`input [4:0] cust5_op;`
159			`input [5:0] cust5_limm;`
160			`output [width-1:0] result;`
161			`output flagforw;`
162			`output flag_we;`
163			`output cyforw;`
164			`output cy_we;`
165			`input carry;`
166			`input flag;`
167
168			`//`
169			`// Internal wires and regs`
170			`//`
171			`reg [width-1:0] result;`
172			`reg [width-1:0] shifted_rotated;`
173			`reg [width-1:0] result_cust5;`
174			`reg flagforw;`
175			`reg flagcomp;`
176			`reg flag_we;`
177			`reg cy_we;`
178			`wire [width-1:0] comp_a;`
179			`wire [width-1:0] comp_b;`
180			`ifdef OR1200_IMPL_ALU_COMP1
181			`wire a_eq_b;`
182			`wire a_lt_b;`
183			`endif
184			`wire [width-1:0] result_sum;`
185			`ifdef OR1200_IMPL_ADDC
186			`wire [width-1:0] result_csum;`
187			`wire cy_csum;`
188			`endif
189			`wire [width-1:0] result_and;`
190			`wire cy_sum;`
191			`reg cyforw;`
192
193			`//`
194			`// Combinatorial logic`
195			`//`
196
197			`// SynEDA CoreMultiplier`
198			`// assignment(s): comp_a`
199			`// replace(s): a, comp_op`
200			`assign comp_a = {a_cml_1[width-1] ^ comp_op_cml_1[3] , a_cml_1[width-2:0]};`
201
202			`// SynEDA CoreMultiplier`
203			`// assignment(s): comp_b`
204			`// replace(s): b, comp_op`
205			`assign comp_b = {b_cml_1[width-1] ^ comp_op_cml_1[3] , b_cml_1[width-2:0]};`
206			`ifdef OR1200_IMPL_ALU_COMP1
207			`assign a_eq_b = (comp_a == comp_b);`
208			`assign a_lt_b = (comp_a < comp_b);`
209			`endif
210			`wire [width:0] cy_sum_result_sum;`
211			`//assign {cy_sum, result_sum} = a + b;`
212			`assign cy_sum_result_sum = a + b;`
213
214			`// SynEDA CoreMultiplier`
215			`// assignment(s): cy_sum`
216			`// replace(s): cy_sum_result_sum`
217			`assign cy_sum = cy_sum_result_sum_cml_1[32];`
218			`assign result_sum = cy_sum_result_sum[31:0];`
219			`ifdef OR1200_IMPL_ADDC
220			`wire [width:0] cy_csum_result_csum;`
221			`//assign {cy_csum, result_csum} = a + b + {32'd0, carry};`
222			`assign cy_csum_result_csum = a + b + {32'd0, carry};`
223
224			`// SynEDA CoreMultiplier`
225			`// assignment(s): cy_csum`
226			`// replace(s): cy_csum_result_csum`
227			`assign cy_csum = cy_csum_result_csum_cml_1[32];`
228			`assign result_csum = cy_csum_result_csum[31:0];`
229			`endif
230			`assign result_and = a & b;`
231
232			`//`
233			`// Simulation check for bad ALU behavior`
234			`//`
235			`ifdef OR1200_WARNINGS
236			`// synopsys translate_off`
237			`always @(result) begin`
238			`if (result === 32'bx)`
239			`$display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);`
240			`end`
241			`// synopsys translate_on`
242			`endif
243
244			`//`
245			`// Central part of the ALU`
246			`//`
247
248			`// SynEDA CoreMultiplier`
249			`// assignment(s): result`
250			`// replace(s): a, b, mult_mac_result, macrc_op, alu_op, flag, shifted_rotated, result_cust5, result_sum, result_csum, result_and`
251			`always @(alu_op_cml_1 or a_cml_1 or b_cml_1 or result_sum_cml_1 or result_and_cml_1 or macrc_op_cml_1 or shifted_rotated_cml_1 or mult_mac_result_cml_1) begin`
252			`ifdef OR1200_CASE_DEFAULT
253			`casex (alu_op_cml_1) // synopsys parallel_case`
254			`else
255			`casex (alu_op_cml_1) // synopsys full_case parallel_case`
256			`endif
257			`OR1200_ALUOP_FF1: begin
258			result = a_cml_1[0] ? 1 : a_cml_1[1] ? 2 : a_cml_1[2] ? 3 : a_cml_1[3] ? 4 : a_cml_1[4] ? 5 : a_cml_1[5] ? 6 : a_cml_1[6] ? 7 : a_cml_1[7] ? 8 : a_cml_1[8] ? 9 : a_cml_1[9] ? 10 : a_cml_1[10] ? 11 : a_cml_1[11] ? 12 : a_cml_1[12] ? 13 : a_cml_1[13] ? 14 : a_cml_1[14] ? 15 : a_cml_1[15] ? 16 : a_cml_1[16] ? 17 : a_cml_1[17] ? 18 : a_cml_1[18] ? 19 : a_cml_1[19] ? 20 : a_cml_1[20] ? 21 : a_cml_1[21] ? 22 : a_cml_1[22] ? 23 : a_cml_1[23] ? 24 : a_cml_1[24] ? 25 : a_cml_1[25] ? 26 : a_cml_1[26] ? 27 : a_cml_1[27] ? 28 : a_cml_1[28] ? 29 : a_cml_1[29] ? 30 : a_cml_1[30] ? 31 : a_cml_1[31] ? 32 : 0;
259			`end`
260			`OR1200_ALUOP_CUST5 : begin
261			`result = result_cust5_cml_1;`
262			`end`
263			`OR1200_ALUOP_SHROT : begin
264			`result = shifted_rotated_cml_1;`
265			`end`
266			`OR1200_ALUOP_ADD : begin
267			`result = result_sum_cml_1;`
268			`end`
269			`ifdef OR1200_IMPL_ADDC
270			`OR1200_ALUOP_ADDC : begin
271			`result = result_csum_cml_1;`
272			`end`
273			`endif
274			`OR1200_ALUOP_SUB : begin
275			`result = a_cml_1 - b_cml_1;`
276			`end`
277			`OR1200_ALUOP_XOR : begin
278			`result = a_cml_1 ^ b_cml_1;`
279			`end`
280			`OR1200_ALUOP_OR : begin
281			`result = a_cml_1 \| b_cml_1;`
282			`end`
283			`OR1200_ALUOP_IMM : begin
284			`result = b_cml_1;`
285			`end`
286			`OR1200_ALUOP_MOVHI : begin
287			`if (macrc_op_cml_1) begin`
288			`result = mult_mac_result_cml_1;`
289			`end`
290			`else begin`
291			`result = b_cml_1 << 16;`
292			`end`
293			`end`
294			`ifdef OR1200_MULT_IMPLEMENTED
295			`ifdef OR1200_IMPL_DIV
296			`OR1200_ALUOP_DIV,
297			`OR1200_ALUOP_DIVU,
298			`endif
299			`OR1200_ALUOP_MUL : begin
300			`result = mult_mac_result_cml_1;`
301			`end`
302			`endif
303			`OR1200_ALUOP_CMOV: begin
304			`result = flag_cml_1 ? a_cml_1 : b_cml_1;`
305			`end`
306
307			`ifdef OR1200_CASE_DEFAULT
308			`default: begin`
309			`else
310			`OR1200_ALUOP_COMP, `OR1200_ALUOP_AND:
311			`begin`
312			`endif
313			`result=result_and_cml_1;`
314			`end`
315			`endcase`
316			`end`
317
318			`//`
319			`// l.cust5 custom instructions`
320			`//`
321			`// Examples for move byte, set bit and clear bit`
322			`//`
323			`always @(cust5_op or cust5_limm or a or b) begin`
324			`casex (cust5_op) // synopsys parallel_case`
325			`5'h1 : begin`
326			`casex (cust5_limm[1:0])`
327			`2'h0: result_cust5 = {a[31:8], b[7:0]};`
328			`2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};`
329			`2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};`
330			`2'h3: result_cust5 = {b[7:0], a[23:0]};`
331			`endcase`
332			`end`
333			`5'h2 :`
334			`result_cust5 = a \| (1 << cust5_limm);`
335			`5'h3 :`
336			`result_cust5 = a & (32'hffffffff ^ (1 << cust5_limm));`
337			`//`
338			`// * Put here new l.cust5 custom instructions *`
339			`//`
340			`default: begin`
341			`result_cust5 = a;`
342			`end`
343			`endcase`
344			`end`
345
346			`//`
347			`// Generate flag and flag write enable`
348			`//`
349
350			`// SynEDA CoreMultiplier`
351			`// assignment(s): flagforw`
352			`// replace(s): alu_op`
353			`always @(alu_op_cml_1 or result_sum or result_and or flagcomp) begin`
354			`casex (alu_op_cml_1) // synopsys parallel_case`
355			`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
356			`OR1200_ALUOP_ADD : begin
357			`flagforw = (result_sum == 32'h0000_0000);`
358			`end`
359			`ifdef OR1200_IMPL_ADDC
360			`OR1200_ALUOP_ADDC : begin
361			`flagforw = (result_csum == 32'h0000_0000);`
362			`end`
363			`endif
364			`OR1200_ALUOP_AND: begin
365			`flagforw = (result_and == 32'h0000_0000);`
366			`end`
367			`endif
368			`OR1200_ALUOP_COMP: begin
369			`flagforw = flagcomp;`
370			`end`
371			`default: begin`
372			`flagforw = 1'b0;`
373			`end`
374			`endcase`
375			`end`
376
377			`// SynEDA CoreMultiplier`
378			`// assignment(s): flag_we`
379			`// replace(s): alu_op`
380			`always @(alu_op_cml_1 or result_sum or result_and or flagcomp) begin`
381			`casex (alu_op_cml_1) // synopsys parallel_case`
382			`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
383			`OR1200_ALUOP_ADD : begin
384			`flag_we = 1'b1;`
385			`end`
386			`ifdef OR1200_IMPL_ADDC
387			`OR1200_ALUOP_ADDC : begin
388			`flag_we = 1'b1;`
389			`end`
390			`endif
391			`OR1200_ALUOP_AND: begin
392			`flag_we = 1'b1;`
393			`end`
394			`endif
395			`OR1200_ALUOP_COMP: begin
396			`flag_we = 1'b1;`
397			`end`
398			`default: begin`
399			`flag_we = 1'b0;`
400			`end`
401			`endcase`
402			`end`
403
404			`//`
405			`// Generate SR[CY] write enable`
406			`//`
407
408			`// SynEDA CoreMultiplier`
409			`// assignment(s): cyforw`
410			`// replace(s): alu_op`
411			`always @(alu_op_cml_1 or cy_sum`
412			`ifdef OR1200_IMPL_ADDC
413			`or cy_csum`
414			`endif
415			`) begin`
416			`casex (alu_op_cml_1) // synopsys parallel_case`
417			`ifdef OR1200_IMPL_CY
418			`OR1200_ALUOP_ADD : begin
419			`cyforw = cy_sum;`
420			`end`
421			`ifdef OR1200_IMPL_ADDC
422			`OR1200_ALUOP_ADDC: begin
423			`cyforw = cy_csum;`
424			`end`
425			`endif
426			`endif
427			`default: begin`
428			`cyforw = 1'b0;`
429			`end`
430			`endcase`
431			`end`
432
433			`// SynEDA CoreMultiplier`
434			`// assignment(s): cy_we`
435			`// replace(s): alu_op`
436			`always @(alu_op_cml_1 or cy_sum`
437			`ifdef OR1200_IMPL_ADDC
438			`or cy_csum`
439			`endif
440			`) begin`
441			`casex (alu_op_cml_1) // synopsys parallel_case`
442			`ifdef OR1200_IMPL_CY
443			`OR1200_ALUOP_ADD : begin
444			`cy_we = 1'b1;`
445			`end`
446			`ifdef OR1200_IMPL_ADDC
447			`OR1200_ALUOP_ADDC: begin
448			`cy_we = 1'b1;`
449			`end`
450			`endif
451			`endif
452			`default: begin`
453			`cy_we = 1'b0;`
454			`end`
455			`endcase`
456			`end`
457
458			`//`
459			`// Shifts and rotation`
460			`//`
461			`always @(shrot_op or a or b) begin`
462			`case (shrot_op) // synopsys parallel_case`
463			`OR1200_SHROTOP_SLL :
464			`shifted_rotated = (a << b[4:0]);`
465			`OR1200_SHROTOP_SRL :
466			`shifted_rotated = (a >> b[4:0]);`
467
468			`ifdef OR1200_IMPL_ALU_ROTATE
469			`OR1200_SHROTOP_ROR :
470			`shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) \| (a >> b[4:0]);`
471			`endif
472			`default:`
473			`shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) \| a >> b[4:0];`
474			`endcase`
475			`end`
476
477			`//`
478			`// First type of compare implementation`
479			`//`
480			`ifdef OR1200_IMPL_ALU_COMP1
481			`always @(comp_op_cml_1 or a_eq_b or a_lt_b) begin`
482			`case(comp_op_cml_1[2:0]) // synopsys parallel_case`
483			`OR1200_COP_SFEQ:
484			`flagcomp = a_eq_b;`
485			`OR1200_COP_SFNE:
486			`flagcomp = ~a_eq_b;`
487			`OR1200_COP_SFGT:
488			`flagcomp = ~(a_eq_b \| a_lt_b);`
489			`OR1200_COP_SFGE:
490			`flagcomp = ~a_lt_b;`
491			`OR1200_COP_SFLT:
492			`flagcomp = a_lt_b;`
493			`OR1200_COP_SFLE:
494			`flagcomp = a_eq_b \| a_lt_b;`
495			`default:`
496			`flagcomp = 1'b0;`
497			`endcase`
498			`end`
499			`endif
500
501			`//`
502			`// Second type of compare implementation`
503			`//`
504			`ifdef OR1200_IMPL_ALU_COMP2
505
506			`// SynEDA CoreMultiplier`
507			`// assignment(s): flagcomp`
508			`// replace(s): comp_op`
509			`always @(comp_op_cml_1 or comp_a or comp_b) begin`
510			`case(comp_op_cml_1[2:0]) // synopsys parallel_case`
511			`OR1200_COP_SFEQ:
512			`flagcomp = (comp_a == comp_b);`
513			`OR1200_COP_SFNE:
514			`flagcomp = (comp_a != comp_b);`
515			`OR1200_COP_SFGT:
516			`flagcomp = (comp_a > comp_b);`
517			`OR1200_COP_SFGE:
518			`flagcomp = (comp_a >= comp_b);`
519			`OR1200_COP_SFLT:
520			`flagcomp = (comp_a < comp_b);`
521			`OR1200_COP_SFLE:
522			`flagcomp = (comp_a <= comp_b);`
523			`default:`
524			`flagcomp = 1'b0;`
525			`endcase`
526			`end`
527			`endif
528
529
530			`always @ (posedge clk_i_cml_1) begin`
531			`a_cml_1 <= a;`
532			`b_cml_1 <= b;`
533			`mult_mac_result_cml_1 <= mult_mac_result;`
534			`macrc_op_cml_1 <= macrc_op;`
535			`alu_op_cml_1 <= alu_op;`
536			`comp_op_cml_1 <= comp_op;`
537			`flag_cml_1 <= flag;`
538			`shifted_rotated_cml_1 <= shifted_rotated;`
539			`result_cust5_cml_1 <= result_cust5;`
540			`result_sum_cml_1 <= result_sum;`
541			`result_csum_cml_1 <= result_csum;`
542			`result_and_cml_1 <= result_and;`
543			`cy_sum_result_sum_cml_1 <= cy_sum_result_sum;`
544			`cy_csum_result_csum_cml_1 <= cy_csum_result_csum;`
545			`end`
546			`endmodule`
547