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//////////////////////////////////////////////////////////////////////
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//// ////
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//// OR1200 Top Level ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// ////
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//// Description ////
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//// OR1200 Top Level ////
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//// ////
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//// To Do: ////
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//// - make it smaller and faster ////
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//// ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: or1200_top.v,v $
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// Revision 1.13 2004/06/08 18:17:36 lampret
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// Non-functional changes. Coding style fixes.
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//
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// Revision 1.12 2004/04/05 08:29:57 lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.10.4.9 2004/02/11 01:40:11 lampret
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// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
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//
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// Revision 1.10.4.8 2004/01/17 21:14:14 simons
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// Errors fixed.
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//
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// Revision 1.10.4.7 2004/01/17 19:06:38 simons
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// Error fixed.
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//
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// Revision 1.10.4.6 2004/01/17 18:39:48 simons
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// Error fixed.
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//
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// Revision 1.10.4.5 2004/01/15 06:46:38 markom
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// interface to debug changed; no more opselect; stb-ack protocol
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//
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// Revision 1.10.4.4 2003/12/09 11:46:49 simons
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// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
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//
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// Revision 1.10.4.3 2003/12/05 00:08:44 lampret
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// Fixed instantiation name.
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//
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// Revision 1.10.4.2 2003/07/11 01:10:35 lampret
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// Added three missing wire declarations. No functional changes.
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//
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// Revision 1.10.4.1 2003/07/08 15:36:37 lampret
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// Added embedded memory QMEM.
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//
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// Revision 1.10 2002/12/08 08:57:56 lampret
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// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
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//
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// Revision 1.9 2002/10/17 20:04:41 lampret
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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//
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// Revision 1.8 2002/08/18 19:54:22 lampret
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// Added store buffer.
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//
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// Revision 1.7 2002/07/14 22:17:17 lampret
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// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
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//
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// Revision 1.6 2002/03/29 15:16:56 lampret
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// Some of the warnings fixed.
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//
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// Revision 1.5 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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// Revision 1.4 2002/02/01 19:56:55 lampret
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// Fixed combinational loops.
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//
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// Revision 1.3 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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// Revision 1.2 2002/01/18 07:56:00 lampret
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.13 2001/11/23 08:38:51 lampret
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// Changed DSR/DRR behavior and exception detection.
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//
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// Revision 1.12 2001/11/20 00:57:22 lampret
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// Fixed width of du_except.
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//
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// Revision 1.11 2001/11/18 08:36:28 lampret
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// For GDB changed single stepping and disabled trap exception.
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//
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// Revision 1.10 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.9 2001/10/14 13:12:10 lampret
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// MP3 version.
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//
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// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
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// no message
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//
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// Revision 1.4 2001/08/13 03:36:20 lampret
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// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
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//
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// Revision 1.3 2001/08/09 13:39:33 lampret
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// Major clean-up.
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//
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// Revision 1.2 2001/07/22 03:31:54 lampret
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// Fixed RAM's oen bug. Cache bypass under development.
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//
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// Revision 1.1 2001/07/20 00:46:21 lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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module or1200_top_cm4_top(
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cmls,
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// System
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clk_i, rst_i, pic_ints_i, clmode_i,
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// Instruction WISHBONE INTERFACE
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//iwb_clk_i, iwb_rst_i,
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iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i,
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iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o,
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`ifdef OR1200_WB_CAB
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iwb_cab_o,
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`endif
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`ifdef OR1200_WB_B3
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iwb_cti_o, iwb_bte_o,
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`endif
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// Data WISHBONE INTERFACE
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//dwb_clk_i, dwb_rst_i,
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dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i,
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dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o,
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`ifdef OR1200_WB_CAB
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dwb_cab_o,
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`endif
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`ifdef OR1200_WB_B3
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dwb_cti_o, dwb_bte_o,
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`endif
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// External Debug Interface
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dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
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dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o,
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`ifdef OR1200_BIST
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// RAM BIST
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mbist_si_i, mbist_so_o, mbist_ctrl_i,
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`endif
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// Power Management
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pm_cpustall_i,
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pm_clksd_o, pm_dc_gate_o, pm_ic_gate_o, pm_dmmu_gate_o,
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pm_immu_gate_o, pm_tt_gate_o, pm_cpu_gate_o, pm_wakeup_o, pm_lvolt_o
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);
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input [1:0] cmls;
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_OPERAND_WIDTH;
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parameter ppic_ints = `OR1200_PIC_INTS;
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//
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// I/O
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//
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//
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// System
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//
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input clk_i;
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input rst_i;
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input [1:0] clmode_i; // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
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input [ppic_ints-1:0] pic_ints_i;
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//
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// Instruction WISHBONE interface
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//
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//input iwb_clk_i; // clock input
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//input iwb_rst_i; // reset input
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wire iwb_clk_i = clk_i;
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wire iwb_rst_i = rst_i;
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input iwb_ack_i; // normal termination
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input iwb_err_i; // termination w/ error
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input iwb_rty_i; // termination w/ retry
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input [dw-1:0] iwb_dat_i; // input data bus
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output iwb_cyc_o; // cycle valid output
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output [aw-1:0] iwb_adr_o; // address bus outputs
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output iwb_stb_o; // strobe output
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output iwb_we_o; // indicates write transfer
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output [3:0] iwb_sel_o; // byte select outputs
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output [dw-1:0] iwb_dat_o; // output data bus
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`ifdef OR1200_WB_CAB
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output iwb_cab_o; // indicates consecutive address burst
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`endif
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`ifdef OR1200_WB_B3
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output [2:0] iwb_cti_o; // cycle type identifier
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output [1:0] iwb_bte_o; // burst type extension
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`endif
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//
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// Data WISHBONE interface
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//
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//input dwb_clk_i; // clock input
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//input dwb_rst_i; // reset input
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wire dwb_clk_i = clk_i;
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wire dwb_rst_i = rst_i;
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input dwb_ack_i; // normal termination
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input dwb_err_i; // termination w/ error
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input dwb_rty_i; // termination w/ retry
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input [dw-1:0] dwb_dat_i; // input data bus
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output dwb_cyc_o; // cycle valid output
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output [aw-1:0] dwb_adr_o; // address bus outputs
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output dwb_stb_o; // strobe output
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output dwb_we_o; // indicates write transfer
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output [3:0] dwb_sel_o; // byte select outputs
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output [dw-1:0] dwb_dat_o; // output data bus
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`ifdef OR1200_WB_CAB
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output dwb_cab_o; // indicates consecutive address burst
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`endif
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`ifdef OR1200_WB_B3
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output [2:0] dwb_cti_o; // cycle type identifier
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output [1:0] dwb_bte_o; // burst type extension
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`endif
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//
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// External Debug Interface
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//
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input dbg_stall_i; // External Stall Input
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input dbg_ewt_i; // External Watchpoint Trigger Input
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output [3:0] dbg_lss_o; // External Load/Store Unit Status
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output [1:0] dbg_is_o; // External Insn Fetch Status
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output [10:0] dbg_wp_o; // Watchpoints Outputs
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output dbg_bp_o; // Breakpoint Output
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input dbg_stb_i; // External Address/Data Strobe
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input dbg_we_i; // External Write Enable
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input [aw-1:0] dbg_adr_i; // External Address Input
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input [dw-1:0] dbg_dat_i; // External Data Input
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output [dw-1:0] dbg_dat_o; // External Data Output
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output dbg_ack_o; // External Data Acknowledge (not WB compatible)
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`ifdef OR1200_BIST
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//
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// RAM BIST
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//
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input mbist_si_i;
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input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
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output mbist_so_o;
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`endif
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//
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// Power Management
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//
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input pm_cpustall_i;
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output [3:0] pm_clksd_o;
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output pm_dc_gate_o;
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output pm_ic_gate_o;
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output pm_dmmu_gate_o;
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output pm_immu_gate_o;
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output pm_tt_gate_o;
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output pm_cpu_gate_o;
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output pm_wakeup_o;
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output pm_lvolt_o;
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or1200_top_cm4 or1200_top_cm4i(
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.clk_i_cml_1(clk_i),
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.clk_i_cml_2(clk_i),
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.clk_i_cml_3(clk_i),
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.cmls(cmls),
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.clk_i(clk_i),
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.rst_i(rst_i),
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.pic_ints_i(pic_ints_i),
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.clmode_i(clmode_i),
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.iwb_ack_i(iwb_ack_i),
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|
|
.iwb_err_i(iwb_err_i),
|
| 309 |
|
|
.iwb_rty_i(iwb_rty_i),
|
| 310 |
|
|
.iwb_dat_i(iwb_dat_i),
|
| 311 |
|
|
.iwb_cyc_o(iwb_cyc_o),
|
| 312 |
|
|
.iwb_adr_o(iwb_adr_o),
|
| 313 |
|
|
.iwb_stb_o(iwb_stb_o),
|
| 314 |
|
|
.iwb_we_o(iwb_we_o),
|
| 315 |
|
|
.iwb_sel_o(iwb_sel_o),
|
| 316 |
|
|
.iwb_dat_o(iwb_dat_o),
|
| 317 |
|
|
`ifdef OR1200_WB_CAB
|
| 318 |
|
|
.iwb_cab_o(iwb_cab_o),
|
| 319 |
|
|
`endif
|
| 320 |
|
|
`ifdef OR1200_WB_B3
|
| 321 |
|
|
.iwb_cti_o(iwb_cti_o),
|
| 322 |
|
|
.iwb_bte_o(iwb_bte_o),
|
| 323 |
|
|
`endif
|
| 324 |
|
|
.dwb_ack_i(dwb_ack_i),
|
| 325 |
|
|
.dwb_err_i(dwb_err_i),
|
| 326 |
|
|
.dwb_rty_i(dwb_rty_i),
|
| 327 |
|
|
.dwb_dat_i(dwb_dat_i),
|
| 328 |
|
|
.dwb_cyc_o(dwb_cyc_o),
|
| 329 |
|
|
.dwb_adr_o(dwb_adr_o),
|
| 330 |
|
|
.dwb_stb_o(dwb_stb_o),
|
| 331 |
|
|
.dwb_we_o(dwb_we_o),
|
| 332 |
|
|
.dwb_sel_o(dwb_sel_o),
|
| 333 |
|
|
.dwb_dat_o(dwb_dat_o),
|
| 334 |
|
|
`ifdef OR1200_WB_CAB
|
| 335 |
|
|
.dwb_cab_o(dwb_cab_o),
|
| 336 |
|
|
`endif
|
| 337 |
|
|
`ifdef OR1200_WB_B3
|
| 338 |
|
|
.dwb_cti_o(dwb_cti_o),
|
| 339 |
|
|
.dwb_bte_o(dwb_bte_o),
|
| 340 |
|
|
`endif
|
| 341 |
|
|
|
| 342 |
|
|
.dbg_stall_i(dbg_stall_i),
|
| 343 |
|
|
.dbg_ewt_i(dbg_ewt_i),
|
| 344 |
|
|
.dbg_lss_o(dbg_lss_o),
|
| 345 |
|
|
.dbg_is_o(dbg_is_o),
|
| 346 |
|
|
.dbg_wp_o(dbg_wp_o),
|
| 347 |
|
|
.dbg_bp_o(dbg_bp_o),
|
| 348 |
|
|
.dbg_stb_i(dbg_stb_i),
|
| 349 |
|
|
.dbg_we_i(dbg_we_i),
|
| 350 |
|
|
.dbg_adr_i(dbg_adr_i),
|
| 351 |
|
|
.dbg_dat_i(dbg_dat_i),
|
| 352 |
|
|
.dbg_dat_o(dbg_dat_o),
|
| 353 |
|
|
.dbg_ack_o(dbg_ack_o),
|
| 354 |
|
|
|
| 355 |
|
|
`ifdef OR1200_BIST
|
| 356 |
|
|
// RAM BIST
|
| 357 |
|
|
.mbist_si_i(mbist_si_i),
|
| 358 |
|
|
.mbist_so_o(mbist_so_o),
|
| 359 |
|
|
.mbist_ctrl_i(mbist_ctrl_i),
|
| 360 |
|
|
`endif
|
| 361 |
|
|
|
| 362 |
|
|
.pm_cpustall_i(pm_cpustall_i),
|
| 363 |
|
|
.pm_clksd_o(pm_clksd_o),
|
| 364 |
|
|
.pm_dc_gate_o(pm_dc_gate_o),
|
| 365 |
|
|
.pm_ic_gate_o(pm_ic_gate_o),
|
| 366 |
|
|
.pm_dmmu_gate_o(pm_dmmu_gate_o),
|
| 367 |
|
|
.pm_immu_gate_o(pm_immu_gate_o),
|
| 368 |
|
|
.pm_tt_gate_o(pm_tt_gate_o),
|
| 369 |
|
|
.pm_cpu_gate_o(pm_cpu_gate_o),
|
| 370 |
|
|
.pm_wakeup_o(pm_wakeup_o),
|
| 371 |
|
|
.pm_lvolt_o(pm_lvolt_o));
|
| 372 |
|
|
|
| 373 |
|
|
|
| 374 |
|
|
|
| 375 |
|
|
endmodule
|
