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[/] [or1200_hp/] [trunk/] [rtl/] [rtl_orig/] [verilog/] [or1200_alu.v] - Blame information for rev 2

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's ALU                                                ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  ALU                                                         ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.14  2004/06/08 18:17:36  lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.13  2004/05/09 19:49:03  lampret
// Added some l.cust5 custom instructions as example
//
// Revision 1.12  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
//
// Revision 1.11  2003/04/24 00:16:07  lampret
// No functional changes. Added defines to disable implementation of multiplier/MAC
//
// Revision 1.10  2002/09/08 05:52:16  lampret
// Added optional l.div/l.divu insns. By default they are disabled.
//
// Revision 1.9  2002/09/07 19:16:10  lampret
// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].
//
// Revision 1.8  2002/09/07 05:42:02  lampret
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
//
// Revision 1.7  2002/09/03 22:28:21  lampret
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
//
// Revision 1.6  2002/03/29 16:40:10  lampret
// Added a directive to ignore signed division variables that are only used in simulation.
//
// Revision 1.5  2002/03/29 16:33:59  lampret
// Added again just recently removed full_case directive
//
// Revision 1.4  2002/03/29 15:16:53  lampret
// Some of the warnings fixed.
//
// Revision 1.3  2002/01/28 01:15:59  lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10  2001/11/12 01:45:40  lampret
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
//
// Revision 1.9  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8  2001/10/19 23:28:45  lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_alu(
        a, b, mult_mac_result, macrc_op,
        alu_op, shrot_op, comp_op,
        cust5_op, cust5_limm,
        result, flagforw, flag_we,
        cyforw, cy_we, carry, flag
);
 
parameter width = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
input   [width-1:0]              a;
input   [width-1:0]              b;
input   [width-1:0]              mult_mac_result;
input                           macrc_op;
input   [`OR1200_ALUOP_WIDTH-1:0]        alu_op;
input   [`OR1200_SHROTOP_WIDTH-1:0]      shrot_op;
input   [`OR1200_COMPOP_WIDTH-1:0]       comp_op;
input   [4:0]                    cust5_op;
input   [5:0]                    cust5_limm;
output  [width-1:0]              result;
output                          flagforw;
output                          flag_we;
output                          cyforw;
output                          cy_we;
input                           carry;
input         flag;
 
//
// Internal wires and regs
//
reg     [width-1:0]              result;
reg     [width-1:0]              shifted_rotated;
reg     [width-1:0]              result_cust5;
reg                             flagforw;
reg                             flagcomp;
reg                             flag_we;
reg                             cy_we;
wire    [width-1:0]              comp_a;
wire    [width-1:0]              comp_b;
`ifdef OR1200_IMPL_ALU_COMP1
wire                            a_eq_b;
wire                            a_lt_b;
`endif
wire    [width-1:0]              result_sum;
`ifdef OR1200_IMPL_ADDC
wire    [width-1:0]              result_csum;
wire                            cy_csum;
`endif
wire    [width-1:0]              result_and;
wire                            cy_sum;
reg                             cyforw;
 
//
// Combinatorial logic
//
assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
`ifdef OR1200_IMPL_ALU_COMP1
assign a_eq_b = (comp_a == comp_b);
assign a_lt_b = (comp_a < comp_b);
`endif
wire    [width:0]                cy_sum_result_sum;
//assign {cy_sum, result_sum} = a + b;
assign cy_sum_result_sum = a + b;
assign cy_sum = cy_sum_result_sum[32];
assign result_sum = cy_sum_result_sum[31:0];
`ifdef OR1200_IMPL_ADDC
wire    [width:0]                cy_csum_result_csum;
//assign {cy_csum, result_csum} = a + b + {32'd0, carry};
assign cy_csum_result_csum = a + b + {32'd0, carry};
assign cy_csum = cy_csum_result_csum[32];
assign result_csum = cy_csum_result_csum[31:0];
`endif
assign result_and = a & b;
 
//
// Simulation check for bad ALU behavior
//
`ifdef OR1200_WARNINGS
// synopsys translate_off
always @(result) begin
        if (result === 32'bx)
                $display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);
end
// synopsys translate_on
`endif
 
//
// Central part of the ALU
//
always @(alu_op or a or b or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result) begin
`ifdef OR1200_CASE_DEFAULT
        casex (alu_op)          // synopsys parallel_case
`else
        casex (alu_op)          // synopsys full_case parallel_case
`endif
    `OR1200_ALUOP_FF1: begin
        result = a[0] ? 1 : a[1] ? 2 : a[2] ? 3 : a[3] ? 4 : a[4] ? 5 : a[5] ? 6 : a[6] ? 7 : a[7] ? 8 : a[8] ? 9 : a[9] ? 10 : a[10] ? 11 : a[11] ? 12 : a[12] ? 13 : a[13] ? 14 : a[14] ? 15 : a[15] ? 16 : a[16] ? 17 : a[17] ? 18 : a[18] ? 19 : a[19] ? 20 : a[20] ? 21 : a[21] ? 22 : a[22] ? 23 : a[23] ? 24 : a[24] ? 25 : a[25] ? 26 : a[26] ? 27 : a[27] ? 28 : a[28] ? 29 : a[29] ? 30 : a[30] ? 31 : a[31] ? 32 : 0;
    end
                `OR1200_ALUOP_CUST5 : begin
                                result = result_cust5;
                end
                `OR1200_ALUOP_SHROT : begin
                                result = shifted_rotated;
                end
                `OR1200_ALUOP_ADD : begin
                                result = result_sum;
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC : begin
                                result = result_csum;
                end
`endif
                `OR1200_ALUOP_SUB : begin
                                result = a - b;
                end
                `OR1200_ALUOP_XOR : begin
                                result = a ^ b;
                end
                `OR1200_ALUOP_OR  : begin
                                result = a | b;
                end
                `OR1200_ALUOP_IMM : begin
                                result = b;
                end
                `OR1200_ALUOP_MOVHI : begin
                                if (macrc_op) begin
                                        result = mult_mac_result;
                                end
                                else begin
                                        result = b << 16;
                                end
                end
`ifdef OR1200_MULT_IMPLEMENTED
`ifdef OR1200_IMPL_DIV
                `OR1200_ALUOP_DIV,
                `OR1200_ALUOP_DIVU,
`endif
                `OR1200_ALUOP_MUL : begin
                                result = mult_mac_result;
                end
`endif
    `OR1200_ALUOP_CMOV: begin
        result = flag ? a : b;
    end
 
`ifdef OR1200_CASE_DEFAULT
    default: begin
`else
    `OR1200_ALUOP_COMP, `OR1200_ALUOP_AND:
    begin
`endif
      result=result_and;
    end
        endcase
end
 
//
// l.cust5 custom instructions
//
// Examples for move byte, set bit and clear bit
//
always @(cust5_op or cust5_limm or a or b) begin
        casex (cust5_op)                // synopsys parallel_case
                5'h1 : begin
                        casex (cust5_limm[1:0])
                                2'h0: result_cust5 = {a[31:8], b[7:0]};
                                2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};
                                2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};
                                2'h3: result_cust5 = {b[7:0], a[23:0]};
                        endcase
                end
                5'h2 :
                        result_cust5 = a | (1 << cust5_limm);
                5'h3 :
                        result_cust5 = a & (32'hffffffff ^ (1 << cust5_limm));
//
// *** Put here new l.cust5 custom instructions ***
//
                default: begin
                        result_cust5 = a;
                end
        endcase
end
 
//
// Generate flag and flag write enable
//
always @(alu_op or result_sum or result_and or flagcomp) begin
        casex (alu_op)          // synopsys parallel_case
`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
                `OR1200_ALUOP_ADD : begin
                        flagforw = (result_sum == 32'h0000_0000);
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC : begin
                        flagforw = (result_csum == 32'h0000_0000);
                end
`endif
                `OR1200_ALUOP_AND: begin
                        flagforw = (result_and == 32'h0000_0000);
                end
`endif
                `OR1200_ALUOP_COMP: begin
                        flagforw = flagcomp;
                end
                default: begin
                        flagforw = 1'b0;
                end
        endcase
end
always @(alu_op or result_sum or result_and or flagcomp) begin
        casex (alu_op)          // synopsys parallel_case
`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
                `OR1200_ALUOP_ADD : begin
                        flag_we = 1'b1;
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC : begin
                        flag_we = 1'b1;
                end
`endif
                `OR1200_ALUOP_AND: begin
                        flag_we = 1'b1;
                end
`endif
                `OR1200_ALUOP_COMP: begin
                        flag_we = 1'b1;
                end
                default: begin
                        flag_we = 1'b0;
                end
        endcase
end
 
//
// Generate SR[CY] write enable
//
always @(alu_op or cy_sum
`ifdef OR1200_IMPL_ADDC
        or cy_csum
`endif
        ) begin
        casex (alu_op)          // synopsys parallel_case
`ifdef OR1200_IMPL_CY
                `OR1200_ALUOP_ADD : begin
                        cyforw = cy_sum;
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC: begin
                        cyforw = cy_csum;
                end
`endif
`endif
                default: begin
                        cyforw = 1'b0;
                end
        endcase
end
always @(alu_op or cy_sum
`ifdef OR1200_IMPL_ADDC
        or cy_csum
`endif
        ) begin
        casex (alu_op)          // synopsys parallel_case
`ifdef OR1200_IMPL_CY
                `OR1200_ALUOP_ADD : begin
                        cy_we = 1'b1;
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC: begin
                        cy_we = 1'b1;
                end
`endif
`endif
                default: begin
                        cy_we = 1'b0;
                end
        endcase
end
 
//
// Shifts and rotation
//
always @(shrot_op or a or b) begin
        case (shrot_op)         // synopsys parallel_case
        `OR1200_SHROTOP_SLL :
                                shifted_rotated = (a << b[4:0]);
                `OR1200_SHROTOP_SRL :
                                shifted_rotated = (a >> b[4:0]);
 
`ifdef OR1200_IMPL_ALU_ROTATE
                `OR1200_SHROTOP_ROR :
                                shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) | (a >> b[4:0]);
`endif
                default:
                                shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) | a >> b[4:0];
        endcase
end
 
//
// First type of compare implementation
//
`ifdef OR1200_IMPL_ALU_COMP1
always @(comp_op or a_eq_b or a_lt_b) begin
        case(comp_op[2:0])       // synopsys parallel_case
                `OR1200_COP_SFEQ:
                        flagcomp = a_eq_b;
                `OR1200_COP_SFNE:
                        flagcomp = ~a_eq_b;
                `OR1200_COP_SFGT:
                        flagcomp = ~(a_eq_b | a_lt_b);
                `OR1200_COP_SFGE:
                        flagcomp = ~a_lt_b;
                `OR1200_COP_SFLT:
                        flagcomp = a_lt_b;
                `OR1200_COP_SFLE:
                        flagcomp = a_eq_b | a_lt_b;
                default:
                        flagcomp = 1'b0;
        endcase
end
`endif
 
//
// Second type of compare implementation
//
`ifdef OR1200_IMPL_ALU_COMP2
always @(comp_op or comp_a or comp_b) begin
        case(comp_op[2:0])       // synopsys parallel_case
                `OR1200_COP_SFEQ:
                        flagcomp = (comp_a == comp_b);
                `OR1200_COP_SFNE:
                        flagcomp = (comp_a != comp_b);
                `OR1200_COP_SFGT:
                        flagcomp = (comp_a > comp_b);
                `OR1200_COP_SFGE:
                        flagcomp = (comp_a >= comp_b);
                `OR1200_COP_SFLT:
                        flagcomp = (comp_a < comp_b);
                `OR1200_COP_SFLE:
                        flagcomp = (comp_a <= comp_b);
                default:
                        flagcomp = 1'b0;
        endcase
end
`endif
 
endmodule

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[/] [or1200_hp/] [trunk/] [rtl/] [rtl_orig/] [verilog/] [or1200_alu.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	tobil	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's ALU ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// ALU ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.14 2004/06/08 18:17:36 lampret`
48			`// Non-functional changes. Coding style fixes.`
49			`//`
50			`// Revision 1.13 2004/05/09 19:49:03 lampret`
51			`// Added some l.cust5 custom instructions as example`
52			`//`
53			`// Revision 1.12 2004/04/05 08:29:57 lampret`
54			`// Merged branch_qmem into main tree.`
55			`//`
56			`// Revision 1.11 2003/04/24 00:16:07 lampret`
57			`// No functional changes. Added defines to disable implementation of multiplier/MAC`
58			`//`
59			`// Revision 1.10 2002/09/08 05:52:16 lampret`
60			`// Added optional l.div/l.divu insns. By default they are disabled.`
61			`//`
62			`// Revision 1.9 2002/09/07 19:16:10 lampret`
63			`// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].`
64			`//`
65			`// Revision 1.8 2002/09/07 05:42:02 lampret`
66			`// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.`
67			`//`
68			`// Revision 1.7 2002/09/03 22:28:21 lampret`
69			`// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.`
70			`//`
71			`// Revision 1.6 2002/03/29 16:40:10 lampret`
72			`// Added a directive to ignore signed division variables that are only used in simulation.`
73			`//`
74			`// Revision 1.5 2002/03/29 16:33:59 lampret`
75			`// Added again just recently removed full_case directive`
76			`//`
77			`// Revision 1.4 2002/03/29 15:16:53 lampret`
78			`// Some of the warnings fixed.`
79			`//`
80			`// Revision 1.3 2002/01/28 01:15:59 lampret`
81			`// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.`
82			`//`
83			`// Revision 1.2 2002/01/14 06:18:22 lampret`
84			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
85			`//`
86			`// Revision 1.1 2002/01/03 08:16:15 lampret`
87			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
88			`//`
89			`// Revision 1.10 2001/11/12 01:45:40 lampret`
90			`// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.`
91			`//`
92			`// Revision 1.9 2001/10/21 17:57:16 lampret`
93			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
94			`//`
95			`// Revision 1.8 2001/10/19 23:28:45 lampret`
96			`// Fixed some synthesis warnings. Configured with caches and MMUs.`
97			`//`
98			`// Revision 1.7 2001/10/14 13:12:09 lampret`
99			`// MP3 version.`
100			`//`
101			`// Revision 1.1.1.1 2001/10/06 10:18:35 igorm`
102			`// no message`
103			`//`
104			`// Revision 1.2 2001/08/09 13:39:33 lampret`
105			`// Major clean-up.`
106			`//`
107			`// Revision 1.1 2001/07/20 00:46:03 lampret`
108			`// Development version of RTL. Libraries are missing.`
109			`//`
110			`//`
111
112			`// synopsys translate_off`
113			`include "timescale.v"
114			`// synopsys translate_on`
115			`include "or1200_defines.v"
116
117			`module or1200_alu(`
118			`a, b, mult_mac_result, macrc_op,`
119			`alu_op, shrot_op, comp_op,`
120			`cust5_op, cust5_limm,`
121			`result, flagforw, flag_we,`
122			`cyforw, cy_we, carry, flag`
123			`);`
124
125			parameter width = `OR1200_OPERAND_WIDTH;
126
127			`//`
128			`// I/O`
129			`//`
130			`input [width-1:0] a;`
131			`input [width-1:0] b;`
132			`input [width-1:0] mult_mac_result;`
133			`input macrc_op;`
134			input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
135			input [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
136			input [`OR1200_COMPOP_WIDTH-1:0] comp_op;
137			`input [4:0] cust5_op;`
138			`input [5:0] cust5_limm;`
139			`output [width-1:0] result;`
140			`output flagforw;`
141			`output flag_we;`
142			`output cyforw;`
143			`output cy_we;`
144			`input carry;`
145			`input flag;`
146
147			`//`
148			`// Internal wires and regs`
149			`//`
150			`reg [width-1:0] result;`
151			`reg [width-1:0] shifted_rotated;`
152			`reg [width-1:0] result_cust5;`
153			`reg flagforw;`
154			`reg flagcomp;`
155			`reg flag_we;`
156			`reg cy_we;`
157			`wire [width-1:0] comp_a;`
158			`wire [width-1:0] comp_b;`
159			`ifdef OR1200_IMPL_ALU_COMP1
160			`wire a_eq_b;`
161			`wire a_lt_b;`
162			`endif
163			`wire [width-1:0] result_sum;`
164			`ifdef OR1200_IMPL_ADDC
165			`wire [width-1:0] result_csum;`
166			`wire cy_csum;`
167			`endif
168			`wire [width-1:0] result_and;`
169			`wire cy_sum;`
170			`reg cyforw;`
171
172			`//`
173			`// Combinatorial logic`
174			`//`
175			`assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};`
176			`assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};`
177			`ifdef OR1200_IMPL_ALU_COMP1
178			`assign a_eq_b = (comp_a == comp_b);`
179			`assign a_lt_b = (comp_a < comp_b);`
180			`endif
181			`wire [width:0] cy_sum_result_sum;`
182			`//assign {cy_sum, result_sum} = a + b;`
183			`assign cy_sum_result_sum = a + b;`
184			`assign cy_sum = cy_sum_result_sum[32];`
185			`assign result_sum = cy_sum_result_sum[31:0];`
186			`ifdef OR1200_IMPL_ADDC
187			`wire [width:0] cy_csum_result_csum;`
188			`//assign {cy_csum, result_csum} = a + b + {32'd0, carry};`
189			`assign cy_csum_result_csum = a + b + {32'd0, carry};`
190			`assign cy_csum = cy_csum_result_csum[32];`
191			`assign result_csum = cy_csum_result_csum[31:0];`
192			`endif
193			`assign result_and = a & b;`
194
195			`//`
196			`// Simulation check for bad ALU behavior`
197			`//`
198			`ifdef OR1200_WARNINGS
199			`// synopsys translate_off`
200			`always @(result) begin`
201			`if (result === 32'bx)`
202			`$display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);`
203			`end`
204			`// synopsys translate_on`
205			`endif
206
207			`//`
208			`// Central part of the ALU`
209			`//`
210			`always @(alu_op or a or b or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result) begin`
211			`ifdef OR1200_CASE_DEFAULT
212			`casex (alu_op) // synopsys parallel_case`
213			`else
214			`casex (alu_op) // synopsys full_case parallel_case`
215			`endif
216			`OR1200_ALUOP_FF1: begin
217			`result = a[0] ? 1 : a[1] ? 2 : a[2] ? 3 : a[3] ? 4 : a[4] ? 5 : a[5] ? 6 : a[6] ? 7 : a[7] ? 8 : a[8] ? 9 : a[9] ? 10 : a[10] ? 11 : a[11] ? 12 : a[12] ? 13 : a[13] ? 14 : a[14] ? 15 : a[15] ? 16 : a[16] ? 17 : a[17] ? 18 : a[18] ? 19 : a[19] ? 20 : a[20] ? 21 : a[21] ? 22 : a[22] ? 23 : a[23] ? 24 : a[24] ? 25 : a[25] ? 26 : a[26] ? 27 : a[27] ? 28 : a[28] ? 29 : a[29] ? 30 : a[30] ? 31 : a[31] ? 32 : 0;`
218			`end`
219			`OR1200_ALUOP_CUST5 : begin
220			`result = result_cust5;`
221			`end`
222			`OR1200_ALUOP_SHROT : begin
223			`result = shifted_rotated;`
224			`end`
225			`OR1200_ALUOP_ADD : begin
226			`result = result_sum;`
227			`end`
228			`ifdef OR1200_IMPL_ADDC
229			`OR1200_ALUOP_ADDC : begin
230			`result = result_csum;`
231			`end`
232			`endif
233			`OR1200_ALUOP_SUB : begin
234			`result = a - b;`
235			`end`
236			`OR1200_ALUOP_XOR : begin
237			`result = a ^ b;`
238			`end`
239			`OR1200_ALUOP_OR : begin
240			`result = a \| b;`
241			`end`
242			`OR1200_ALUOP_IMM : begin
243			`result = b;`
244			`end`
245			`OR1200_ALUOP_MOVHI : begin
246			`if (macrc_op) begin`
247			`result = mult_mac_result;`
248			`end`
249			`else begin`
250			`result = b << 16;`
251			`end`
252			`end`
253			`ifdef OR1200_MULT_IMPLEMENTED
254			`ifdef OR1200_IMPL_DIV
255			`OR1200_ALUOP_DIV,
256			`OR1200_ALUOP_DIVU,
257			`endif
258			`OR1200_ALUOP_MUL : begin
259			`result = mult_mac_result;`
260			`end`
261			`endif
262			`OR1200_ALUOP_CMOV: begin
263			`result = flag ? a : b;`
264			`end`
265
266			`ifdef OR1200_CASE_DEFAULT
267			`default: begin`
268			`else
269			`OR1200_ALUOP_COMP, `OR1200_ALUOP_AND:
270			`begin`
271			`endif
272			`result=result_and;`
273			`end`
274			`endcase`
275			`end`
276
277			`//`
278			`// l.cust5 custom instructions`
279			`//`
280			`// Examples for move byte, set bit and clear bit`
281			`//`
282			`always @(cust5_op or cust5_limm or a or b) begin`
283			`casex (cust5_op) // synopsys parallel_case`
284			`5'h1 : begin`
285			`casex (cust5_limm[1:0])`
286			`2'h0: result_cust5 = {a[31:8], b[7:0]};`
287			`2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};`
288			`2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};`
289			`2'h3: result_cust5 = {b[7:0], a[23:0]};`
290			`endcase`
291			`end`
292			`5'h2 :`
293			`result_cust5 = a \| (1 << cust5_limm);`
294			`5'h3 :`
295			`result_cust5 = a & (32'hffffffff ^ (1 << cust5_limm));`
296			`//`
297			`// * Put here new l.cust5 custom instructions *`
298			`//`
299			`default: begin`
300			`result_cust5 = a;`
301			`end`
302			`endcase`
303			`end`
304
305			`//`
306			`// Generate flag and flag write enable`
307			`//`
308			`always @(alu_op or result_sum or result_and or flagcomp) begin`
309			`casex (alu_op) // synopsys parallel_case`
310			`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
311			`OR1200_ALUOP_ADD : begin
312			`flagforw = (result_sum == 32'h0000_0000);`
313			`end`
314			`ifdef OR1200_IMPL_ADDC
315			`OR1200_ALUOP_ADDC : begin
316			`flagforw = (result_csum == 32'h0000_0000);`
317			`end`
318			`endif
319			`OR1200_ALUOP_AND: begin
320			`flagforw = (result_and == 32'h0000_0000);`
321			`end`
322			`endif
323			`OR1200_ALUOP_COMP: begin
324			`flagforw = flagcomp;`
325			`end`
326			`default: begin`
327			`flagforw = 1'b0;`
328			`end`
329			`endcase`
330			`end`
331			`always @(alu_op or result_sum or result_and or flagcomp) begin`
332			`casex (alu_op) // synopsys parallel_case`
333			`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
334			`OR1200_ALUOP_ADD : begin
335			`flag_we = 1'b1;`
336			`end`
337			`ifdef OR1200_IMPL_ADDC
338			`OR1200_ALUOP_ADDC : begin
339			`flag_we = 1'b1;`
340			`end`
341			`endif
342			`OR1200_ALUOP_AND: begin
343			`flag_we = 1'b1;`
344			`end`
345			`endif
346			`OR1200_ALUOP_COMP: begin
347			`flag_we = 1'b1;`
348			`end`
349			`default: begin`
350			`flag_we = 1'b0;`
351			`end`
352			`endcase`
353			`end`
354
355			`//`
356			`// Generate SR[CY] write enable`
357			`//`
358			`always @(alu_op or cy_sum`
359			`ifdef OR1200_IMPL_ADDC
360			`or cy_csum`
361			`endif
362			`) begin`
363			`casex (alu_op) // synopsys parallel_case`
364			`ifdef OR1200_IMPL_CY
365			`OR1200_ALUOP_ADD : begin
366			`cyforw = cy_sum;`
367			`end`
368			`ifdef OR1200_IMPL_ADDC
369			`OR1200_ALUOP_ADDC: begin
370			`cyforw = cy_csum;`
371			`end`
372			`endif
373			`endif
374			`default: begin`
375			`cyforw = 1'b0;`
376			`end`
377			`endcase`
378			`end`
379			`always @(alu_op or cy_sum`
380			`ifdef OR1200_IMPL_ADDC
381			`or cy_csum`
382			`endif
383			`) begin`
384			`casex (alu_op) // synopsys parallel_case`
385			`ifdef OR1200_IMPL_CY
386			`OR1200_ALUOP_ADD : begin
387			`cy_we = 1'b1;`
388			`end`
389			`ifdef OR1200_IMPL_ADDC
390			`OR1200_ALUOP_ADDC: begin
391			`cy_we = 1'b1;`
392			`end`
393			`endif
394			`endif
395			`default: begin`
396			`cy_we = 1'b0;`
397			`end`
398			`endcase`
399			`end`
400
401			`//`
402			`// Shifts and rotation`
403			`//`
404			`always @(shrot_op or a or b) begin`
405			`case (shrot_op) // synopsys parallel_case`
406			`OR1200_SHROTOP_SLL :
407			`shifted_rotated = (a << b[4:0]);`
408			`OR1200_SHROTOP_SRL :
409			`shifted_rotated = (a >> b[4:0]);`
410
411			`ifdef OR1200_IMPL_ALU_ROTATE
412			`OR1200_SHROTOP_ROR :
413			`shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) \| (a >> b[4:0]);`
414			`endif
415			`default:`
416			`shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) \| a >> b[4:0];`
417			`endcase`
418			`end`
419
420			`//`
421			`// First type of compare implementation`
422			`//`
423			`ifdef OR1200_IMPL_ALU_COMP1
424			`always @(comp_op or a_eq_b or a_lt_b) begin`
425			`case(comp_op[2:0]) // synopsys parallel_case`
426			`OR1200_COP_SFEQ:
427			`flagcomp = a_eq_b;`
428			`OR1200_COP_SFNE:
429			`flagcomp = ~a_eq_b;`
430			`OR1200_COP_SFGT:
431			`flagcomp = ~(a_eq_b \| a_lt_b);`
432			`OR1200_COP_SFGE:
433			`flagcomp = ~a_lt_b;`
434			`OR1200_COP_SFLT:
435			`flagcomp = a_lt_b;`
436			`OR1200_COP_SFLE:
437			`flagcomp = a_eq_b \| a_lt_b;`
438			`default:`
439			`flagcomp = 1'b0;`
440			`endcase`
441			`end`
442			`endif
443
444			`//`
445			`// Second type of compare implementation`
446			`//`
447			`ifdef OR1200_IMPL_ALU_COMP2
448			`always @(comp_op or comp_a or comp_b) begin`
449			`case(comp_op[2:0]) // synopsys parallel_case`
450			`OR1200_COP_SFEQ:
451			`flagcomp = (comp_a == comp_b);`
452			`OR1200_COP_SFNE:
453			`flagcomp = (comp_a != comp_b);`
454			`OR1200_COP_SFGT:
455			`flagcomp = (comp_a > comp_b);`
456			`OR1200_COP_SFGE:
457			`flagcomp = (comp_a >= comp_b);`
458			`OR1200_COP_SFLT:
459			`flagcomp = (comp_a < comp_b);`
460			`OR1200_COP_SFLE:
461			`flagcomp = (comp_a <= comp_b);`
462			`default:`
463			`flagcomp = 1'b0;`
464			`endcase`
465			`end`
466			`endif
467
468			`endmodule`