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[/] [or1200_hp/] [trunk/] [rtl/] [rtl_orig/] [verilog/] [or1200_wb_biu.v] - Blame information for rev 2

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's WISHBONE BIU                                       ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/cores/or1k/                        ////
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////                                                              ////
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////  Description                                                 ////
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////  Implements WISHBONE interface                               ////
10
////                                                              ////
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////  To Do:                                                      ////
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////   - if biu_cyc/stb are deasserted and wb_ack_i is asserted   ////
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////   and this happens even before aborted_r is asssrted,        ////
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////   wb_ack_i will be delivered even though transfer is         ////
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////   internally considered already aborted. However most        ////
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////   wb_ack_i are externally registered and delayed. Normally   ////
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////   this shouldn't cause any problems.                         ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
48
//
49
// CVS Revision History
50
//
51
// $Log: not supported by cvs2svn $
52
// Revision 1.6.4.1  2003/07/08 15:36:37  lampret
53
// Added embedded memory QMEM.
54
//
55
// Revision 1.6  2003/04/07 20:57:46  lampret
56
// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Fixed order of ifdefs.
57
//
58
// Revision 1.5  2002/12/08 08:57:56  lampret
59
// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
60
//
61
// Revision 1.4  2002/09/16 03:09:16  lampret
62
// Fixed a combinational loop.
63
//
64
// Revision 1.3  2002/08/12 05:31:37  lampret
65
// Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers.
66
//
67
// Revision 1.2  2002/07/14 22:17:17  lampret
68
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
69
//
70
// Revision 1.1  2002/01/03 08:16:15  lampret
71
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
72
//
73
// Revision 1.12  2001/11/22 13:42:51  lampret
74
// Added wb_cyc_o assignment after it was removed by accident.
75
//
76
// Revision 1.11  2001/11/20 21:28:10  lampret
77
// Added optional sampling of inputs.
78
//
79
// Revision 1.10  2001/11/18 11:32:00  lampret
80
// OR1200_REGISTERED_OUTPUTS can now be enabled.
81
//
82
// Revision 1.9  2001/10/21 17:57:16  lampret
83
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
84
//
85
// Revision 1.8  2001/10/14 13:12:10  lampret
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// MP3 version.
87
//
88
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
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// no message
90
//
91
// Revision 1.3  2001/08/09 13:39:33  lampret
92
// Major clean-up.
93
//
94
// Revision 1.2  2001/07/22 03:31:54  lampret
95
// Fixed RAM's oen bug. Cache bypass under development.
96
//
97
// Revision 1.1  2001/07/20 00:46:23  lampret
98
// Development version of RTL. Libraries are missing.
99
//
100
//
101
 
102
// synopsys translate_off
103
`include "timescale.v"
104
// synopsys translate_on
105
`include "or1200_defines.v"
106
 
107
module or1200_wb_biu(
108
        // RISC clock, reset and clock control
109
        clk, rst, clmode,
110
 
111
        // WISHBONE interface
112
        wb_clk_i, wb_rst_i, wb_ack_i, wb_err_i, wb_rty_i, wb_dat_i,
113
        wb_cyc_o, wb_adr_o, wb_stb_o, wb_we_o, wb_sel_o, wb_dat_o,
114
`ifdef OR1200_WB_CAB
115
        wb_cab_o,
116
`endif
117
`ifdef OR1200_WB_B3
118
        wb_cti_o, wb_bte_o,
119
`endif
120
 
121
        // Internal RISC bus
122
        biu_dat_i, biu_adr_i, biu_cyc_i, biu_stb_i, biu_we_i, biu_sel_i, biu_cab_i,
123
        biu_dat_o, biu_ack_o, biu_err_o
124
);
125
 
126
parameter dw = `OR1200_OPERAND_WIDTH;
127
parameter aw = `OR1200_OPERAND_WIDTH;
128
 
129
//
130
// RISC clock, reset and clock control
131
//
132
input                   clk;            // RISC clock
133
input                   rst;            // RISC reset
134
input   [1:0]            clmode;         // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
135
 
136
//
137
// WISHBONE interface
138
//
139
input                   wb_clk_i;       // clock input
140
input                   wb_rst_i;       // reset input
141
input                   wb_ack_i;       // normal termination
142
input                   wb_err_i;       // termination w/ error
143
input                   wb_rty_i;       // termination w/ retry
144
input   [dw-1:0] wb_dat_i;       // input data bus
145
output                  wb_cyc_o;       // cycle valid output
146
output  [aw-1:0] wb_adr_o;       // address bus outputs
147
output                  wb_stb_o;       // strobe output
148
output                  wb_we_o;        // indicates write transfer
149
output  [3:0]            wb_sel_o;       // byte select outputs
150
output  [dw-1:0] wb_dat_o;       // output data bus
151
`ifdef OR1200_WB_CAB
152
output                  wb_cab_o;       // consecutive address burst
153
`endif
154
`ifdef OR1200_WB_B3
155
output  [2:0]            wb_cti_o;       // cycle type identifier
156
output  [1:0]            wb_bte_o;       // burst type extension
157
`endif
158
 
159
//
160
// Internal RISC interface
161
//
162
input   [dw-1:0] biu_dat_i;      // input data bus
163
input   [aw-1:0] biu_adr_i;      // address bus
164
input                   biu_cyc_i;      // WB cycle
165
input                   biu_stb_i;      // WB strobe
166
input                   biu_we_i;       // WB write enable
167
input                   biu_cab_i;      // CAB input
168
input   [3:0]            biu_sel_i;      // byte selects
169
output  [31:0]           biu_dat_o;      // output data bus
170
output                  biu_ack_o;      // ack output
171
output                  biu_err_o;      // err output
172
 
173
//
174
// Registers
175
//
176
reg     [1:0]            valid_div;      // Used for synchronization
177
`ifdef OR1200_REGISTERED_OUTPUTS
178
reg     [aw-1:0] wb_adr_o;       // address bus outputs
179
reg                     wb_cyc_o;       // cycle output
180
reg                     wb_stb_o;       // strobe output
181
reg                     wb_we_o;        // indicates write transfer
182
reg     [3:0]            wb_sel_o;       // byte select outputs
183
`ifdef OR1200_WB_CAB
184
reg                     wb_cab_o;       // CAB output
185
`endif
186
`ifdef OR1200_WB_B3
187
reg     [1:0]            burst_len;      // burst counter
188
reg     [2:0]            wb_cti_o;       // cycle type identifier
189
`endif
190
reg     [dw-1:0] wb_dat_o;       // output data bus
191
`endif
192
`ifdef OR1200_REGISTERED_INPUTS
193
reg                     long_ack_o;     // normal termination
194
reg                     long_err_o;     // error termination
195
reg     [dw-1:0] biu_dat_o;      // output data bus
196
`else
197
wire                    long_ack_o;     // normal termination
198
wire                    long_err_o;     // error termination
199
`endif
200
wire                    aborted;        // Graceful abort
201
reg                     aborted_r;      // Graceful abort
202
wire                    retry;          // Retry
203
`ifdef OR1200_WB_RETRY
204
reg     [`OR1200_WB_RETRY-1:0] retry_cntr;       // Retry counter
205
`endif
206
 
207
//
208
// WISHBONE I/F <-> Internal RISC I/F conversion
209
//
210
 
211
//
212
// Address bus
213
//
214
`ifdef OR1200_REGISTERED_OUTPUTS
215
always @(posedge wb_clk_i or posedge wb_rst_i)
216
        if (wb_rst_i)
217
                wb_adr_o <= #1 {aw{1'b0}};
218
        else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~aborted & ~(wb_stb_o & ~wb_ack_i))
219
                wb_adr_o <= #1 biu_adr_i;
220
`else
221
assign wb_adr_o = biu_adr_i;
222
`endif
223
 
224
//
225
// Input data bus
226
//
227
`ifdef OR1200_REGISTERED_INPUTS
228
always @(posedge wb_clk_i or posedge wb_rst_i)
229
        if (wb_rst_i)
230
                biu_dat_o <= #1 32'h0000_0000;
231
        else if (wb_ack_i)
232
                biu_dat_o <= #1 wb_dat_i;
233
`else
234
assign biu_dat_o = wb_dat_i;
235
`endif
236
 
237
//
238
// Output data bus
239
//
240
`ifdef OR1200_REGISTERED_OUTPUTS
241
always @(posedge wb_clk_i or posedge wb_rst_i)
242
        if (wb_rst_i)
243
                wb_dat_o <= #1 {dw{1'b0}};
244
        else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~aborted)
245
                wb_dat_o <= #1 biu_dat_i;
246
`else
247
assign wb_dat_o = biu_dat_i;
248
`endif
249
 
250
//
251
// Valid_div counts RISC clock cycles by modulo 4
252
// and is used to synchronize external WB i/f to
253
// RISC clock
254
//
255
always @(posedge clk or posedge rst)
256
        if (rst)
257
                valid_div <= #1 2'b0;
258
        else
259
                valid_div <= #1 valid_div + 1'd1;
260
 
261
//
262
// biu_ack_o is one RISC clock cycle long long_ack_o.
263
// long_ack_o is one, two or four RISC clock cycles long because
264
// WISHBONE can work at 1, 1/2 or 1/4 RISC clock.
265
//
266
assign biu_ack_o = long_ack_o
267
`ifdef OR1200_CLKDIV_2_SUPPORTED
268
                & (valid_div[0] | ~clmode[0])
269
`ifdef OR1200_CLKDIV_4_SUPPORTED
270
                & (valid_div[1] | ~clmode[1])
271
`endif
272
`endif
273
                ;
274
 
275
//
276
// Acknowledgment of the data to the RISC
277
//
278
// long_ack_o
279
//
280
`ifdef OR1200_REGISTERED_INPUTS
281
always @(posedge wb_clk_i or posedge wb_rst_i)
282
        if (wb_rst_i)
283
                long_ack_o <= #1 1'b0;
284
        else
285
                long_ack_o <= #1 wb_ack_i & ~aborted;
286
`else
287
assign long_ack_o = wb_ack_i & ~aborted_r;
288
`endif
289
 
290
//
291
// biu_err_o is one RISC clock cycle long long_err_o.
292
// long_err_o is one, two or four RISC clock cycles long because
293
// WISHBONE can work at 1, 1/2 or 1/4 RISC clock.
294
//
295
assign biu_err_o = long_err_o
296
`ifdef OR1200_CLKDIV_2_SUPPORTED
297
                & (valid_div[0] | ~clmode[0])
298
`ifdef OR1200_CLKDIV_4_SUPPORTED
299
                & (valid_div[1] | ~clmode[1])
300
`endif
301
`endif
302
                ;
303
 
304
//
305
// Error termination
306
//
307
// long_err_o
308
//
309
`ifdef OR1200_REGISTERED_INPUTS
310
always @(posedge wb_clk_i or posedge wb_rst_i)
311
        if (wb_rst_i)
312
                long_err_o <= #1 1'b0;
313
        else
314
                long_err_o <= #1 wb_err_i & ~aborted;
315
`else
316
assign long_err_o = wb_err_i & ~aborted_r;
317
`endif
318
 
319
//
320
// Retry counter
321
//
322
// Assert 'retry' when 'wb_rty_i' is sampled high and keep it high
323
// until retry counter doesn't expire
324
// 
325
`ifdef OR1200_WB_RETRY
326
assign retry = wb_rty_i | (|retry_cntr);
327
`else
328
assign retry = 1'b0;
329
`endif
330
`ifdef OR1200_WB_RETRY
331
always @(posedge wb_clk_i or posedge wb_rst_i)
332
        if (wb_rst_i)
333
                retry_cntr <= #1 1'b0;
334
        else if (wb_rty_i)
335
                retry_cntr <= #1 {`OR1200_WB_RETRY{1'b1}};
336
        else if (retry_cntr)
337
                retry_cntr <= #1 retry_cntr - 7'd1;
338
`endif
339
 
340
//
341
// Graceful completion of aborted transfers
342
//
343
// Assert 'aborted' when 1) current transfer is in progress (wb_stb_o; which
344
// we know is only asserted together with wb_cyc_o) 2) and in next WB clock cycle
345
// wb_stb_o would be deasserted (biu_cyc_i and biu_stb_i are low) 3) and
346
// there is no termination of current transfer in this WB clock cycle (wb_ack_i
347
// and wb_err_i are low).
348
// 'aborted_r' is registered 'aborted' and extended until this "aborted" transfer
349
// is properly terminated with wb_ack_i/wb_err_i.
350
// 
351
assign aborted = wb_stb_o & ~(biu_cyc_i & biu_stb_i) & ~(wb_ack_i | wb_err_i);
352
always @(posedge wb_clk_i or posedge wb_rst_i)
353
        if (wb_rst_i)
354
                aborted_r <= #1 1'b0;
355
        else if (wb_ack_i | wb_err_i)
356
                aborted_r <= #1 1'b0;
357
        else if (aborted)
358
                aborted_r <= #1 1'b1;
359
 
360
//
361
// WB cyc_o
362
//
363
// Either 1) normal transfer initiated by biu_cyc_i (and biu_cab_i if
364
// bursts are enabled) and possibly suspended by 'retry'
365
// or 2) extended "aborted" transfer
366
//
367
`ifdef OR1200_REGISTERED_OUTPUTS
368
always @(posedge wb_clk_i or posedge wb_rst_i)
369
        if (wb_rst_i)
370
                wb_cyc_o <= #1 1'b0;
371
        else
372
`ifdef OR1200_NO_BURSTS
373
                wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i & ~retry | aborted & ~wb_ack_i;
374
`else
375
                wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i & ~retry | biu_cab_i | aborted & ~wb_ack_i;
376
`endif
377
`else
378
`ifdef OR1200_NO_BURSTS
379
assign wb_cyc_o = biu_cyc_i & ~retry;
380
`else
381
assign wb_cyc_o = biu_cyc_i | biu_cab_i & ~retry;
382
`endif
383
`endif
384
 
385
//
386
// WB stb_o
387
//
388
`ifdef OR1200_REGISTERED_OUTPUTS
389
always @(posedge wb_clk_i or posedge wb_rst_i)
390
        if (wb_rst_i)
391
                wb_stb_o <= #1 1'b0;
392
        else
393
                wb_stb_o <= #1 (biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~retry | aborted & ~wb_ack_i;
394
`else
395
assign wb_stb_o = biu_cyc_i & biu_stb_i;
396
`endif
397
 
398
//
399
// WB we_o
400
//
401
`ifdef OR1200_REGISTERED_OUTPUTS
402
always @(posedge wb_clk_i or posedge wb_rst_i)
403
        if (wb_rst_i)
404
                wb_we_o <= #1 1'b0;
405
        else
406
                wb_we_o <= #1 biu_cyc_i & biu_stb_i & biu_we_i | aborted & wb_we_o;
407
`else
408
assign wb_we_o = biu_cyc_i & biu_stb_i & biu_we_i;
409
`endif
410
 
411
//
412
// WB sel_o
413
//
414
`ifdef OR1200_REGISTERED_OUTPUTS
415
always @(posedge wb_clk_i or posedge wb_rst_i)
416
        if (wb_rst_i)
417
                wb_sel_o <= #1 4'b0000;
418
        else
419
                wb_sel_o <= #1 biu_sel_i;
420
`else
421
assign wb_sel_o = biu_sel_i;
422
`endif
423
 
424
`ifdef OR1200_WB_CAB
425
//
426
// WB cab_o
427
//
428
`ifdef OR1200_REGISTERED_OUTPUTS
429
always @(posedge wb_clk_i or posedge wb_rst_i)
430
        if (wb_rst_i)
431
                wb_cab_o <= #1 1'b0;
432
        else
433
                wb_cab_o <= #1 biu_cab_i;
434
`else
435
assign wb_cab_o = biu_cab_i;
436
`endif
437
`endif
438
 
439
`ifdef OR1200_WB_B3
440
//
441
// Count burst beats
442
//
443
always @(posedge wb_clk_i or posedge wb_rst_i)
444
        if (wb_rst_i)
445
                burst_len <= #1 2'b00;
446
        else if (biu_cab_i && burst_len && wb_ack_i)
447
                burst_len <= #1 burst_len - 1'b1;
448
        else if (~biu_cab_i)
449
                burst_len <= #1 2'b11;
450
 
451
//
452
// WB cti_o
453
//
454
`ifdef OR1200_REGISTERED_OUTPUTS
455
always @(posedge wb_clk_i or posedge wb_rst_i)
456
        if (wb_rst_i)
457
                wb_cti_o <= #1 3'b000;  // classic cycle
458
`ifdef OR1200_NO_BURSTS
459
        else
460
                wb_cti_o <= #1 3'b111;  // end-of-burst
461
`else
462
        else if (biu_cab_i && burst_len[1])
463
                wb_cti_o <= #1 3'b010;  // incrementing burst cycle
464
        else if (biu_cab_i && wb_ack_i)
465
                wb_cti_o <= #1 3'b111;  // end-of-burst
466
`endif  // OR1200_NO_BURSTS
467
`else
468
Unsupported !!!;
469
`endif
470
 
471
//
472
// WB bte_o
473
//
474
assign wb_bte_o = 2'b01;        // 4-beat wrap burst
475
 
476
`endif  // OR1200_WB_B3
477
 
478
endmodule

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