OpenCores
URL https://opencores.org/ocsvn/or1200_hp/or1200_hp/trunk

Subversion Repositories or1200_hp

[/] [or1200_hp/] [trunk/] [rtl/] [rtl_virtex_orig/] [verilog/] [ic_ram_blk.v] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 tobil
/*******************************************************************************
2
*     This file is owned and controlled by Xilinx and must be used             *
3
*     solely for design, simulation, implementation and creation of            *
4
*     design files limited to Xilinx devices or technologies. Use              *
5
*     with non-Xilinx devices or technologies is expressly prohibited          *
6
*     and immediately terminates your license.                                 *
7
*                                                                              *
8
*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
9
*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
10
*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
11
*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
12
*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
13
*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
14
*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
15
*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
16
*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
17
*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
18
*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
19
*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
20
*     FOR A PARTICULAR PURPOSE.                                                *
21
*                                                                              *
22
*     Xilinx products are not intended for use in life support                 *
23
*     appliances, devices, or systems. Use in such applications are            *
24
*     expressly prohibited.                                                    *
25
*                                                                              *
26
*     (c) Copyright 1995-2009 Xilinx, Inc.                                     *
27
*     All rights reserved.                                                     *
28
*******************************************************************************/
29
// The synthesis directives "translate_off/translate_on" specified below are
30
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
31
// tools. Ensure they are correct for your synthesis tool(s).
32
 
33
// You must compile the wrapper file ic_ram_blk.v when simulating
34
// the core, ic_ram_blk. When compiling the wrapper file, be sure to
35
// reference the XilinxCoreLib Verilog simulation library. For detailed
36
// instructions, please refer to the "CORE Generator Help".
37
 
38
// synopsys translate_off
39
`include "timescale.v"
40
// synopsys translate_on
41
 
42
`include "or1200_defines.v"
43
 
44
module ic_ram_blk(
45
        clka,
46
        ena,
47
        wea,
48
        addra,
49
        dina,
50
        clkb,
51
        addrb,
52
        doutb);
53
 
54
 
55
input clka;
56
input ena;
57
input [0 : 0] wea;
58
input [10 : 0] addra;
59
input [31 : 0] dina;
60
input clkb;
61
input [10 : 0] addrb;
62
output [31 : 0] doutb;
63
 
64
`ifdef BLK_MEM_GEN
65
 
66
// synthesis translate_off
67
 
68
      BLK_MEM_GEN_V3_1 #(
69
                .C_ADDRA_WIDTH(11),
70
                .C_ADDRB_WIDTH(11),
71
                .C_ALGORITHM(1),
72
                .C_BYTE_SIZE(9),
73
                .C_COMMON_CLK(0),
74
                .C_DEFAULT_DATA("0"),
75
                .C_DISABLE_WARN_BHV_COLL(0),
76
                .C_DISABLE_WARN_BHV_RANGE(0),
77
                .C_FAMILY("virtex5"),
78
                .C_HAS_ENA(1),
79
                .C_HAS_ENB(0),
80
                .C_HAS_INJECTERR(0),
81
                .C_HAS_MEM_OUTPUT_REGS_A(0),
82
                .C_HAS_MEM_OUTPUT_REGS_B(0),
83
                .C_HAS_MUX_OUTPUT_REGS_A(0),
84
                .C_HAS_MUX_OUTPUT_REGS_B(0),
85
                .C_HAS_REGCEA(0),
86
                .C_HAS_REGCEB(0),
87
                .C_HAS_RSTA(0),
88
                .C_HAS_RSTB(0),
89
                .C_INITA_VAL("0"),
90
                .C_INITB_VAL("0"),
91
                .C_INIT_FILE_NAME("no_coe_file_loaded"),
92
                .C_LOAD_INIT_FILE(0),
93
                .C_MEM_TYPE(1),
94
                .C_MUX_PIPELINE_STAGES(0),
95
                .C_PRIM_TYPE(1),
96
                .C_READ_DEPTH_A(2048),
97
                .C_READ_DEPTH_B(2048),
98
                .C_READ_WIDTH_A(32),
99
                .C_READ_WIDTH_B(32),
100
                .C_RSTRAM_A(0),
101
                .C_RSTRAM_B(0),
102
                .C_RST_PRIORITY_A("CE"),
103
                .C_RST_PRIORITY_B("CE"),
104
                .C_RST_TYPE("SYNC"),
105
                .C_SIM_COLLISION_CHECK("ALL"),
106
                .C_USE_BYTE_WEA(0),
107
                .C_USE_BYTE_WEB(0),
108
                .C_USE_DEFAULT_DATA(0),
109
                .C_USE_ECC(0),
110
                .C_WEA_WIDTH(1),
111
                .C_WEB_WIDTH(1),
112
                .C_WRITE_DEPTH_A(2048),
113
                .C_WRITE_DEPTH_B(2048),
114
                .C_WRITE_MODE_A("READ_FIRST"),
115
                .C_WRITE_MODE_B("READ_FIRST"),
116
                .C_WRITE_WIDTH_A(32),
117
                .C_WRITE_WIDTH_B(32),
118
                .C_XDEVICEFAMILY("virtex5"))
119
        inst (
120
                .CLKA(clka),
121
                .ENA(ena),
122
                .WEA(wea),
123
                .ADDRA(addra),
124
                .DINA(dina),
125
                .CLKB(clkb),
126
                .ADDRB(addrb),
127
                .DOUTB(doutb),
128
                .RSTA(),
129
                .REGCEA(),
130
                .DOUTA(),
131
                .RSTB(),
132
                .ENB(),
133
                .REGCEB(),
134
                .WEB(),
135
                .DINB(),
136
                .INJECTSBITERR(),
137
                .INJECTDBITERR(),
138
                .SBITERR(),
139
                .DBITERR(),
140
                .RDADDRECC());
141
 
142
 
143
// synthesis translate_on
144
 
145
`else
146
 
147
reg     [10:0]   addrb_reg;              // RAM address register
148
 
149
always @(posedge clka)
150
                addrb_reg <= #1 addrb;
151
 
152
//
153
// Generic RAM's registers and wires
154
//
155
reg     [31:0]   mem [(1<<11)-1:0];       // RAM content
156
 
157
//
158
// Data output drivers
159
//
160
assign doutb = mem[addrb_reg];
161
 
162
//
163
// RAM write
164
//
165
always @(posedge clka)
166
        if (ena && wea)
167
                mem[addra] <= #1 dina;
168
 
169
`endif
170
 
171
endmodule
172
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.