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// The synthesis directives "translate_off/translate_on" specified below are

// supported by Xilinx, Mentor Graphics and Synplicity synthesis

// tools. Ensure they are correct for your synthesis tool(s).

// You must compile the wrapper file rf_blk.v when simulating

// the core, rf_blk. When compiling the wrapper file, be sure to

// reference the XilinxCoreLib Verilog simulation library. For detailed

// instructions, please refer to the "CORE Generator Help".

`timescale 1ns/1ps

module rf_sub(

        a,

        d,

        dpra,

        clk,

        we,

        spo,

        dpo);

input [4 : 0] a;

input [31 : 0] d;

input [4 : 0] dpra;

input clk;

input we;

output [31 : 0] spo;

output [31 : 0] dpo;

rf_dist rf_disti(

        .a(a),

        .d(d),

        .dpra(dpra),

        .clk(clk),

        .we(we),

        .spo(spo),

        .dpo(dpo));

endmodule