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Subversion Repositories or1200_soc

[/] [or1200_soc/] [trunk/] [boards/] [de1_board/] [libs/] [uart16550.cr.mti] - Blame information for rev 23

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Line No. Rev Author Line
1 23 qaztronic 
C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/raminfr.v {1 {vlog -work uart16550 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/raminfr.v
2 
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct  1 2009
3 
-- Compiling module raminfr
4 21 qaztronic 
 
5 
Top level modules:
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        raminfr
7 21 qaztronic 
 
8 
} {} {}} C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_sync_flops.v {1 {vlog -work uart16550 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_sync_flops.v
9 23 qaztronic 
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct  1 2009
10 21 qaztronic 
-- Compiling module uart_sync_flops
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Top level modules:
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        uart_sync_flops
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15 23 qaztronic 
} {} {}} C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_tfifo.v {1 {vlog -work uart16550 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_tfifo.v
16 
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct  1 2009
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-- Compiling module uart_tfifo
18 21 qaztronic 
 
19 
Top level modules:
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        uart_tfifo
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22 23 qaztronic 
} {} {}} C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_wb.v {1 {vlog -work uart16550 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_wb.v
23 
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct  1 2009
24 
-- Compiling module uart_wb
25 21 qaztronic 
 
26 
Top level modules:
27 23 qaztronic 
        uart_wb
28 21 qaztronic 
 
29 23 qaztronic 
} {} {}} C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_debug_if.v {1 {vlog -work uart16550 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_debug_if.v
30 
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct  1 2009
31 
-- Compiling module uart_debug_if
32 21 qaztronic 
 
33 
Top level modules:
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        uart_debug_if
35 21 qaztronic 
 
36 
} {} {}} C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_receiver.v {1 {vlog -work uart16550 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_receiver.v
37 23 qaztronic 
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct  1 2009
38 21 qaztronic 
-- Compiling module uart_receiver
39 
 
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Top level modules:
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        uart_receiver
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43 23 qaztronic 
} {} {}} C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_regs.v {1 {vlog -work uart16550 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_regs.v
44 
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct  1 2009
45 
-- Compiling module uart_regs
46 21 qaztronic 
 
47 
Top level modules:
48 23 qaztronic 
        uart_regs
49 21 qaztronic 
 
50 23 qaztronic 
} {} {}} C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_transmitter.v {1 {vlog -work uart16550 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_transmitter.v
51 
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct  1 2009
52 
-- Compiling module uart_transmitter
53 21 qaztronic 
 
54 
Top level modules:
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        uart_transmitter
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57 
} {} {}} C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_rfifo.v {1 {vlog -work uart16550 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_rfifo.v
58 23 qaztronic 
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct  1 2009
59 21 qaztronic 
-- Compiling module uart_rfifo
60 
 
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Top level modules:
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        uart_rfifo
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} {} {}} C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_top.v {1 {vlog -work uart16550 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_top.v
65 23 qaztronic 
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct  1 2009
66 21 qaztronic 
-- Compiling module uart_top
67 
 
68 
Top level modules:
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        uart_top
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} {} {}}

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