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qaztronic |
------------------------------------------------------------------------------
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-- File name : s29al032d_00.vhd
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Copyright (C) 2005 Spansion, LLC.
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--
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-- MODIFICATION HISTORY :
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--
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-- version: | author: | mod date: | changes made:
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-- V1.0 D.Lukovic 05 May 16 Initial release
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--
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-------------------------------------------------------------------------------
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-- PART DESCRIPTION:
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--
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-- Library: FLASH
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-- Technology: Flash memory
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-- Part: s29al032d_00
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--
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-- Description: 32Mbit (4M x 8-Bit) Flash Memory
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--
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--
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-------------------------------------------------------------------------------
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-- Known Bugs:
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--
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-------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.VITAL_timing.ALL;
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USE IEEE.VITAL_primitives.ALL;
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USE STD.textio.ALL;
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LIBRARY FMF;
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USE FMF.gen_utils.all;
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USE FMF.conversions.all;
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-------------------------------------------------------------------------------
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-- ENTITY DECLARATION
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-------------------------------------------------------------------------------
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ENTITY s29al032d_00 IS
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GENERIC (
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-- tipd delays: interconnect path delays
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tipd_A0 : VitalDelayType01 := VitalZeroDelay01; --
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tipd_A1 : VitalDelayType01 := VitalZeroDelay01; --
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tipd_A2 : VitalDelayType01 := VitalZeroDelay01; --
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tipd_A3 : VitalDelayType01 := VitalZeroDelay01; --
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tipd_A4 : VitalDelayType01 := VitalZeroDelay01; --
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tipd_A5 : VitalDelayType01 := VitalZeroDelay01; --
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tipd_A6 : VitalDelayType01 := VitalZeroDelay01; --
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tipd_A7 : VitalDelayType01 := VitalZeroDelay01; --
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tipd_A8 : VitalDelayType01 := VitalZeroDelay01; --
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tipd_A9 : VitalDelayType01 := VitalZeroDelay01; --address
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tipd_A10 : VitalDelayType01 := VitalZeroDelay01; --lines
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tipd_A11 : VitalDelayType01 := VitalZeroDelay01; --
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tipd_A12 : VitalDelayType01 := VitalZeroDelay01; --
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tipd_A13 : VitalDelayType01 := VitalZeroDelay01; --
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tipd_A14 : VitalDelayType01 := VitalZeroDelay01; --
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tipd_A15 : VitalDelayType01 := VitalZeroDelay01; --
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tipd_A16 : VitalDelayType01 := VitalZeroDelay01; --
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tipd_A17 : VitalDelayType01 := VitalZeroDelay01; --
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tipd_A18 : VitalDelayType01 := VitalZeroDelay01; --
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tipd_A19 : VitalDelayType01 := VitalZeroDelay01; --
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tipd_A20 : VitalDelayType01 := VitalZeroDelay01; --
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tipd_A21 : VitalDelayType01 := VitalZeroDelay01; --
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tipd_DQ0 : VitalDelayType01 := VitalZeroDelay01; --
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tipd_DQ1 : VitalDelayType01 := VitalZeroDelay01; --
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tipd_DQ2 : VitalDelayType01 := VitalZeroDelay01; --
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tipd_DQ3 : VitalDelayType01 := VitalZeroDelay01; -- data
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tipd_DQ4 : VitalDelayType01 := VitalZeroDelay01; -- lines
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tipd_DQ5 : VitalDelayType01 := VitalZeroDelay01; --
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tipd_DQ6 : VitalDelayType01 := VitalZeroDelay01; --
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tipd_DQ7 : VitalDelayType01 := VitalZeroDelay01; --
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tipd_CENeg : VitalDelayType01 := VitalZeroDelay01;
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tipd_OENeg : VitalDelayType01 := VitalZeroDelay01;
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tipd_WENeg : VitalDelayType01 := VitalZeroDelay01;
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tipd_RESETNeg : VitalDelayType01 := VitalZeroDelay01;
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tipd_ACC : VitalDelayType01 := VitalZeroDelay01;
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-- tpd delays
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tpd_A0_DQ0 : VitalDelayType01 := UnitDelay01;--tACC
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tpd_CENeg_DQ0 : VitalDelayType01Z := UnitDelay01Z;
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--(tCE,tCE,tDF,-,tDF,-)
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tpd_OENeg_DQ0 : VitalDelayType01Z := UnitDelay01Z;
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--(tOE,tOE,tDF,-,tDF,-)
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tpd_RESETNeg_DQ0 : VitalDelayType01Z := UnitDelay01Z;
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--(-,-,0,-,0,-)
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tpd_CENeg_RY : VitalDelayType01Z := UnitDelay01Z; --tBUSY
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tpd_WENeg_RY : VitalDelayType01Z := UnitDelay01Z; --tBUSY
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--tsetup values
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tsetup_A0_WENeg : VitalDelayType := UnitDelay; --tAS edge \
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tsetup_DQ0_WENeg : VitalDelayType := UnitDelay; --tDS edge /
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--thold values
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thold_CENeg_RESETNeg: VitalDelayType := UnitDelay; --tRH edge /
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thold_A0_WENeg : VitalDelayType := UnitDelay; --tAH edge \
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thold_DQ0_CENeg : VitalDelayType := UnitDelay; --tDH edge /
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thold_OENeg_WENeg_noedge_negedge
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: VitalDelayType := UnitDelay; --tOEH edge /
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thold_OENeg_WENeg_noedge_posedge
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: VitalDelayType := UnitDelay; --tOEH edge /
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--tpw values: pulse width
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tpw_RESETNeg_negedge: VitalDelayType := UnitDelay; --tRP
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tpw_WENeg_negedge : VitalDelayType := UnitDelay; --tWP
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tpw_WENeg_posedge : VitalDelayType := UnitDelay; --tWPH
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tpw_CENeg_negedge : VitalDelayType := UnitDelay; --tCP
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tpw_CENeg_posedge : VitalDelayType := UnitDelay; --tCEPH
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tpw_A0_negedge : VitalDelayType := UnitDelay; --tWC tRC
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-- tdevice values: values for internal delays
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tdevice_POB : VitalDelayType := 9 us;
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--word write
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tdevice_SEO : VitalDelayType := 700 ms;
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--Timing Limit Exceeded
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tdevice_HANG : VitalDelayType := 400 ms; --?
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--erase suspend timeout - only max time specified
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tdevice_ESTART_T1 : VitalDelayType := 20 us;--max 20 us
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--sector erase command sequence timeout
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tdevice_CTMOUTS : VitalDelayType := 50 us;
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--device ready after Hardware reset(during embeded algorithm)
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tdevice_READYR : VitalDelayType := 20 us; --tReady
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-- generic control parameters
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InstancePath : STRING := DefaultInstancePath;
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TimingChecksOn : BOOLEAN := DefaultTimingChecks;
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MsgOn : BOOLEAN := DefaultMsgOn;
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XOn : BOOLEAN := DefaultXon;
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-- memory file to be loaded
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mem_file_name : STRING := "none";--"s29al032d_00.mem";
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prot_file_name : STRING := "none";--"s29al032d_00_prot.mem";
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secsi_file_name : STRING := "none";--"s29al032d_00_secsi.mem";
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UserPreload : BOOLEAN := FALSE;
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LongTimming : BOOLEAN := TRUE;
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-- For FMF SDF technology file usage
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TimingModel : STRING := DefaultTimingModel
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);
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PORT (
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A21 : IN std_ulogic := 'U'; --
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A20 : IN std_ulogic := 'U'; --
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A19 : IN std_ulogic := 'U'; --
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A18 : IN std_ulogic := 'U'; --
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A17 : IN std_ulogic := 'U'; --
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A16 : IN std_ulogic := 'U'; --
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A15 : IN std_ulogic := 'U'; --
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A14 : IN std_ulogic := 'U'; --
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A13 : IN std_ulogic := 'U'; --address
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A12 : IN std_ulogic := 'U'; --lines
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A11 : IN std_ulogic := 'U'; --
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A10 : IN std_ulogic := 'U'; --
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A9 : IN std_ulogic := 'U'; --
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A8 : IN std_ulogic := 'U'; --
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A7 : IN std_ulogic := 'U'; --
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A6 : IN std_ulogic := 'U'; --
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A5 : IN std_ulogic := 'U'; --
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A4 : IN std_ulogic := 'U'; --
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A3 : IN std_ulogic := 'U'; --
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A2 : IN std_ulogic := 'U'; --
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A1 : IN std_ulogic := 'U'; --
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A0 : IN std_ulogic := 'U'; --
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DQ7 : INOUT std_ulogic := 'U'; --
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DQ6 : INOUT std_ulogic := 'U'; --
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DQ5 : INOUT std_ulogic := 'U'; --
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DQ4 : INOUT std_ulogic := 'U'; --
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DQ3 : INOUT std_ulogic := 'U'; --
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DQ2 : INOUT std_ulogic := 'U'; --
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DQ1 : INOUT std_ulogic := 'U'; --
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DQ0 : INOUT std_ulogic := 'U'; --
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CENeg : IN std_ulogic := 'U';
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OENeg : IN std_ulogic := 'U';
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WENeg : IN std_ulogic := 'U';
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RESETNeg : IN std_ulogic := 'U';
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ACC : IN std_ulogic := 'U';
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RY : OUT std_ulogic := 'U' --RY/BY#
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);
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ATTRIBUTE VITAL_LEVEL0 of s29al032d_00 : ENTITY IS TRUE;
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END s29al032d_00;
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-------------------------------------------------------------------------------
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-- ARCHITECTURE DECLARATION
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-------------------------------------------------------------------------------
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ARCHITECTURE vhdl_behavioral of s29al032d_00 IS
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ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;
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CONSTANT PartID : STRING := "s29al032d_00";
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CONSTANT MaxData : NATURAL := 16#FF#; --255;
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CONSTANT SecSize : NATURAL := 16#FFFF#; --65535
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CONSTANT SecSiSize : NATURAL := 255;
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CONSTANT MemSize : NATURAL := 16#3FFFFF#;
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CONSTANT SecNum : NATURAL := 63;
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CONSTANT HiAddrBit : NATURAL := 21;
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-- interconnect path delay signals
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SIGNAL A21_ipd : std_ulogic := 'U';
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SIGNAL A20_ipd : std_ulogic := 'U';
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SIGNAL A19_ipd : std_ulogic := 'U';
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SIGNAL A18_ipd : std_ulogic := 'U';
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SIGNAL A17_ipd : std_ulogic := 'U';
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SIGNAL A16_ipd : std_ulogic := 'U';
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SIGNAL A15_ipd : std_ulogic := 'U';
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SIGNAL A14_ipd : std_ulogic := 'U';
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SIGNAL A13_ipd : std_ulogic := 'U';
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SIGNAL A12_ipd : std_ulogic := 'U';
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SIGNAL A11_ipd : std_ulogic := 'U';
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SIGNAL A10_ipd : std_ulogic := 'U';
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SIGNAL A9_ipd : std_ulogic := 'U';
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SIGNAL A8_ipd : std_ulogic := 'U';
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SIGNAL A7_ipd : std_ulogic := 'U';
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SIGNAL A6_ipd : std_ulogic := 'U';
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SIGNAL A5_ipd : std_ulogic := 'U';
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SIGNAL A4_ipd : std_ulogic := 'U';
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SIGNAL A3_ipd : std_ulogic := 'U';
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SIGNAL A2_ipd : std_ulogic := 'U';
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SIGNAL A1_ipd : std_ulogic := 'U';
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SIGNAL A0_ipd : std_ulogic := 'U';
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SIGNAL DQ7_ipd : std_ulogic := 'U';
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SIGNAL DQ6_ipd : std_ulogic := 'U';
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SIGNAL DQ5_ipd : std_ulogic := 'U';
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SIGNAL DQ4_ipd : std_ulogic := 'U';
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SIGNAL DQ3_ipd : std_ulogic := 'U';
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SIGNAL DQ2_ipd : std_ulogic := 'U';
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SIGNAL DQ1_ipd : std_ulogic := 'U';
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SIGNAL DQ0_ipd : std_ulogic := 'U';
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SIGNAL CENeg_ipd : std_ulogic := 'U';
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SIGNAL OENeg_ipd : std_ulogic := 'U';
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SIGNAL WENeg_ipd : std_ulogic := 'U';
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SIGNAL RESETNeg_ipd : std_ulogic := 'U';
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SIGNAL ACC_ipd : std_ulogic := 'U';
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--- internal delays
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SIGNAL POB_in : std_ulogic := '0';
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SIGNAL POB_out : std_ulogic := '0';
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SIGNAL SEO_in : std_ulogic := '0';
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SIGNAL SEO_out : std_ulogic := '0';
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SIGNAL HANG_out : std_ulogic := '0'; --Program/Erase Timing Limit
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SIGNAL HANG_in : std_ulogic := '0';
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SIGNAL START_T1 : std_ulogic := '0'; --Start TimeOut; SUSPEND
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SIGNAL START_T1_in : std_ulogic := '0';
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SIGNAL CTMOUT : std_ulogic := '0'; --Sector Erase TimeOut
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SIGNAL CTMOUT_in : std_ulogic := '0';
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SIGNAL READY_in : std_ulogic := '0';
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SIGNAL READY : std_ulogic := '0'; -- Device ready after reset
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BEGIN
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---------------------------------------------------------------------------
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-- Internal Delays
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---------------------------------------------------------------------------
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-- Artificial VITAL primitives to incorporate internal delays
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POB :VitalBuf(POB_out, POB_in, (tdevice_POB ,UnitDelay));
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SEO :VitalBuf(SEO_out, SEO_in, (tdevice_SEO ,UnitDelay));
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HANG :VitalBuf(HANG_out, HANG_in, (tdevice_HANG ,UnitDelay));
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ESTART_T1:VitalBuf(START_T1, START_T1_in, (tdevice_ESTART_T1 ,UnitDelay));
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CTMOUTS :VitalBuf(CTMOUT, CTMOUT_in, (tdevice_CTMOUTS ,UnitDelay));
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READYR :VitalBuf(READY, READY_in, (tdevice_READYR ,UnitDelay));
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---------------------------------------------------------------------------
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-- Wire Delays
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---------------------------------------------------------------------------
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WireDelay : BLOCK
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BEGIN
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w_1 : VitalWireDelay (A21_ipd, A21, tipd_A21);
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w_2 : VitalWireDelay (A20_ipd, A20, tipd_A20);
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w_3 : VitalWireDelay (A19_ipd, A19, tipd_A19);
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w_4 : VitalWireDelay (A18_ipd, A18, tipd_A18);
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w_5 : VitalWireDelay (A17_ipd, A17, tipd_A17);
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w_6 : VitalWireDelay (A16_ipd, A16, tipd_A16);
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w_7 : VitalWireDelay (A15_ipd, A15, tipd_A15);
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w_8 : VitalWireDelay (A14_ipd, A14, tipd_A14);
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w_9 : VitalWireDelay (A13_ipd, A13, tipd_A13);
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w_10 : VitalWireDelay (A12_ipd, A12, tipd_A12);
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w_11 : VitalWireDelay (A11_ipd, A11, tipd_A11);
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w_12 : VitalWireDelay (A10_ipd, A10, tipd_A10);
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|
|
w_13 : VitalWireDelay (A9_ipd, A9, tipd_A9);
|
| 281 |
|
|
w_14 : VitalWireDelay (A8_ipd, A8, tipd_A8);
|
| 282 |
|
|
w_15 : VitalWireDelay (A7_ipd, A7, tipd_A7);
|
| 283 |
|
|
w_16 : VitalWireDelay (A6_ipd, A6, tipd_A6);
|
| 284 |
|
|
w_17 : VitalWireDelay (A5_ipd, A5, tipd_A5);
|
| 285 |
|
|
w_18 : VitalWireDelay (A4_ipd, A4, tipd_A4);
|
| 286 |
|
|
w_19 : VitalWireDelay (A3_ipd, A3, tipd_A3);
|
| 287 |
|
|
w_20 : VitalWireDelay (A2_ipd, A2, tipd_A2);
|
| 288 |
|
|
w_21 : VitalWireDelay (A1_ipd, A1, tipd_A1);
|
| 289 |
|
|
w_22 : VitalWireDelay (A0_ipd, A0, tipd_A0);
|
| 290 |
|
|
|
| 291 |
|
|
w_23 : VitalWireDelay (DQ7_ipd, DQ7, tipd_DQ7);
|
| 292 |
|
|
w_24 : VitalWireDelay (DQ6_ipd, DQ6, tipd_DQ6);
|
| 293 |
|
|
w_25 : VitalWireDelay (DQ5_ipd, DQ5, tipd_DQ5);
|
| 294 |
|
|
w_26 : VitalWireDelay (DQ4_ipd, DQ4, tipd_DQ4);
|
| 295 |
|
|
w_27 : VitalWireDelay (DQ3_ipd, DQ3, tipd_DQ3);
|
| 296 |
|
|
w_28 : VitalWireDelay (DQ2_ipd, DQ2, tipd_DQ2);
|
| 297 |
|
|
w_29 : VitalWireDelay (DQ1_ipd, DQ1, tipd_DQ1);
|
| 298 |
|
|
w_30 : VitalWireDelay (DQ0_ipd, DQ0, tipd_DQ0);
|
| 299 |
|
|
w_31 : VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg);
|
| 300 |
|
|
w_32 : VitalWireDelay (WENeg_ipd, WENeg, tipd_WENeg);
|
| 301 |
|
|
w_33 : VitalWireDelay (RESETNeg_ipd, RESETNeg, tipd_RESETNeg);
|
| 302 |
|
|
w_34 : VitalWireDelay (CENeg_ipd, CENeg, tipd_CENeg);
|
| 303 |
|
|
w_35 : VitalWireDelay (ACC_ipd, ACC, tipd_ACC);
|
| 304 |
|
|
|
| 305 |
|
|
END BLOCK;
|
| 306 |
|
|
|
| 307 |
|
|
---------------------------------------------------------------------------
|
| 308 |
|
|
-- Main Behavior Block
|
| 309 |
|
|
---------------------------------------------------------------------------
|
| 310 |
|
|
Behavior: BLOCK
|
| 311 |
|
|
|
| 312 |
|
|
PORT (
|
| 313 |
|
|
A : IN std_logic_vector(HiAddrBit downto 0) :=
|
| 314 |
|
|
(OTHERS => 'U');
|
| 315 |
|
|
DIn : IN std_logic_vector(7 downto 0) :=
|
| 316 |
|
|
(OTHERS => 'U');
|
| 317 |
|
|
DOut : OUT std_ulogic_vector(7 downto 0) :=
|
| 318 |
|
|
(OTHERS => 'Z');
|
| 319 |
|
|
CENeg : IN std_ulogic := 'U';
|
| 320 |
|
|
OENeg : IN std_ulogic := 'U';
|
| 321 |
|
|
WENeg : IN std_ulogic := 'U';
|
| 322 |
|
|
RESETNeg : IN std_ulogic := 'U';
|
| 323 |
|
|
ACC : IN std_ulogic := 'U';
|
| 324 |
|
|
|
| 325 |
|
|
RY : OUT std_ulogic := 'U'
|
| 326 |
|
|
);
|
| 327 |
|
|
PORT MAP (
|
| 328 |
|
|
A(21) => A21_ipd,
|
| 329 |
|
|
A(20) => A20_ipd,
|
| 330 |
|
|
A(19) => A19_ipd,
|
| 331 |
|
|
A(18) => A18_ipd,
|
| 332 |
|
|
A(17) => A17_ipd,
|
| 333 |
|
|
A(16) => A16_ipd,
|
| 334 |
|
|
A(15) => A15_ipd,
|
| 335 |
|
|
A(14) => A14_ipd,
|
| 336 |
|
|
A(13) => A13_ipd,
|
| 337 |
|
|
A(12) => A12_ipd,
|
| 338 |
|
|
A(11) => A11_ipd,
|
| 339 |
|
|
A(10) => A10_ipd,
|
| 340 |
|
|
A(9) => A9_ipd,
|
| 341 |
|
|
A(8) => A8_ipd,
|
| 342 |
|
|
A(7) => A7_ipd,
|
| 343 |
|
|
A(6) => A6_ipd,
|
| 344 |
|
|
A(5) => A5_ipd,
|
| 345 |
|
|
A(4) => A4_ipd,
|
| 346 |
|
|
A(3) => A3_ipd,
|
| 347 |
|
|
A(2) => A2_ipd,
|
| 348 |
|
|
A(1) => A1_ipd,
|
| 349 |
|
|
A(0) => A0_ipd,
|
| 350 |
|
|
|
| 351 |
|
|
DIn(7) => DQ7_ipd,
|
| 352 |
|
|
DIn(6) => DQ6_ipd,
|
| 353 |
|
|
DIn(5) => DQ5_ipd,
|
| 354 |
|
|
DIn(4) => DQ4_ipd,
|
| 355 |
|
|
DIn(3) => DQ3_ipd,
|
| 356 |
|
|
DIn(2) => DQ2_ipd,
|
| 357 |
|
|
DIn(1) => DQ1_ipd,
|
| 358 |
|
|
DIn(0) => DQ0_ipd,
|
| 359 |
|
|
|
| 360 |
|
|
DOut(7) => DQ7,
|
| 361 |
|
|
DOut(6) => DQ6,
|
| 362 |
|
|
DOut(5) => DQ5,
|
| 363 |
|
|
DOut(4) => DQ4,
|
| 364 |
|
|
DOut(3) => DQ3,
|
| 365 |
|
|
DOut(2) => DQ2,
|
| 366 |
|
|
DOut(1) => DQ1,
|
| 367 |
|
|
DOut(0) => DQ0,
|
| 368 |
|
|
|
| 369 |
|
|
CENeg => CENeg_ipd,
|
| 370 |
|
|
OENeg => OENeg_ipd,
|
| 371 |
|
|
WENeg => WENeg_ipd,
|
| 372 |
|
|
ACC => ACC_ipd,
|
| 373 |
|
|
RESETNeg => RESETNeg_ipd,
|
| 374 |
|
|
RY => RY
|
| 375 |
|
|
);
|
| 376 |
|
|
|
| 377 |
|
|
-- State Machine : State_Type
|
| 378 |
|
|
TYPE state_type IS (
|
| 379 |
|
|
RESET,
|
| 380 |
|
|
Z001,
|
| 381 |
|
|
CFI,
|
| 382 |
|
|
PREL_SETBWB,
|
| 383 |
|
|
PREL_ULBYPASS,
|
| 384 |
|
|
PREL_ULBYPASS_RESET,
|
| 385 |
|
|
AS,
|
| 386 |
|
|
AS_CFI,
|
| 387 |
|
|
A0SEEN,
|
| 388 |
|
|
C8,
|
| 389 |
|
|
C8_Z001,
|
| 390 |
|
|
C8_PREL,
|
| 391 |
|
|
OTP,
|
| 392 |
|
|
OTP_Z001,
|
| 393 |
|
|
OTP_PREL,
|
| 394 |
|
|
OTP_AS,
|
| 395 |
|
|
OTP_AS_CFI,
|
| 396 |
|
|
OTP_A0SEEN,
|
| 397 |
|
|
ERS,
|
| 398 |
|
|
SERS,
|
| 399 |
|
|
ESPS,
|
| 400 |
|
|
SERS_EXEC,
|
| 401 |
|
|
ESP,
|
| 402 |
|
|
ESP_CFI,
|
| 403 |
|
|
ESP_Z001,
|
| 404 |
|
|
ESP_PREL,
|
| 405 |
|
|
ESP_AS,
|
| 406 |
|
|
ESP_AS_CFI,
|
| 407 |
|
|
PGMS
|
| 408 |
|
|
);
|
| 409 |
|
|
|
| 410 |
|
|
--Flash Memory Array
|
| 411 |
|
|
TYPE SecType IS ARRAY (0 TO SecSize) OF
|
| 412 |
|
|
INTEGER RANGE -1 TO MaxData;
|
| 413 |
|
|
|
| 414 |
|
|
TYPE MemArray IS ARRAY (0 TO SecNum) OF
|
| 415 |
|
|
SecType;
|
| 416 |
|
|
|
| 417 |
|
|
TYPE SecSiType IS ARRAY ( 0 TO SecSiSize) OF
|
| 418 |
|
|
INTEGER RANGE -1 TO MaxData;
|
| 419 |
|
|
|
| 420 |
|
|
-- states
|
| 421 |
|
|
SIGNAL current_state : state_type; --
|
| 422 |
|
|
SIGNAL next_state : state_type; --
|
| 423 |
|
|
|
| 424 |
|
|
-- powerup
|
| 425 |
|
|
SIGNAL PoweredUp : std_logic := '0';
|
| 426 |
|
|
|
| 427 |
|
|
--zero delay signals
|
| 428 |
|
|
SIGNAL DOut_zd : std_logic_vector(7 downto 0):=(OTHERS=>'Z');
|
| 429 |
|
|
SIGNAL DOut_Pass : std_logic_vector(7 downto 0):=(OTHERS=>'Z');
|
| 430 |
|
|
SIGNAL RY_zd : std_logic := 'Z';
|
| 431 |
|
|
|
| 432 |
|
|
--FSM control signals
|
| 433 |
|
|
SIGNAL ULBYPASS : std_logic := '0'; --Unlock Bypass Active
|
| 434 |
|
|
SIGNAL ESP_ACT : std_logic := '0'; --Erase Suspend
|
| 435 |
|
|
SIGNAL OTP_ACT : std_logic := '0';
|
| 436 |
|
|
|
| 437 |
|
|
--Model should never hang!!!!!!!!!!!!!!!
|
| 438 |
|
|
SIGNAL HANG : std_logic := '0';
|
| 439 |
|
|
|
| 440 |
|
|
SIGNAL PDONE : std_logic := '1'; --Prog. Done
|
| 441 |
|
|
SIGNAL PSTART : std_logic := '0'; --Start Programming
|
| 442 |
|
|
|
| 443 |
|
|
--Program location is in protected sector
|
| 444 |
|
|
SIGNAL PERR : std_logic := '0';
|
| 445 |
|
|
|
| 446 |
|
|
SIGNAL EDONE : std_logic := '1'; --Ers. Done
|
| 447 |
|
|
SIGNAL ESTART : std_logic := '0'; --Start Erase
|
| 448 |
|
|
SIGNAL ESUSP : std_logic := '0'; --Suspend Erase
|
| 449 |
|
|
SIGNAL ERES : std_logic := '0'; --Resume Erase
|
| 450 |
|
|
--All sectors selected for erasure are protected
|
| 451 |
|
|
SIGNAL EERR : std_logic := '0';
|
| 452 |
|
|
--Sectors selected for erasure
|
| 453 |
|
|
SIGNAL ERS_QUEUE : std_logic_vector(SecNum downto 0) :=
|
| 454 |
|
|
(OTHERS => '0');
|
| 455 |
|
|
--Command Register
|
| 456 |
|
|
SIGNAL write : std_logic := '0';
|
| 457 |
|
|
SIGNAL read : std_logic := '0';
|
| 458 |
|
|
|
| 459 |
|
|
-- Access time variables
|
| 460 |
|
|
SHARED VARIABLE OPENLATCH : BOOLEAN;
|
| 461 |
|
|
SHARED VARIABLE FROMCE : BOOLEAN;
|
| 462 |
|
|
SHARED VARIABLE FROMOE : BOOLEAN;
|
| 463 |
|
|
|
| 464 |
|
|
SHARED VARIABLE AS_SecSi_FP : std_logic := '0';
|
| 465 |
|
|
SHARED VARIABLE AS_addr : NATURAL := 0;
|
| 466 |
|
|
SHARED VARIABLE AS_ID : BOOLEAN := FALSE;
|
| 467 |
|
|
SHARED VARIABLE AS_ID2 : BOOLEAN := FALSE;
|
| 468 |
|
|
|
| 469 |
|
|
--Sector Address
|
| 470 |
|
|
SIGNAL SecAddr : NATURAL RANGE 0 TO SecNum := 0;
|
| 471 |
|
|
|
| 472 |
|
|
SIGNAL SA : NATURAL RANGE 0 TO SecNum := 0;
|
| 473 |
|
|
|
| 474 |
|
|
--Address within sector
|
| 475 |
|
|
SIGNAL Address : NATURAL RANGE 0 TO SecSize := 0;
|
| 476 |
|
|
|
| 477 |
|
|
SIGNAL D_tmp : NATURAL RANGE 0 TO MaxData;
|
| 478 |
|
|
SIGNAL D_tmp1 : NATURAL RANGE 0 TO MaxData;
|
| 479 |
|
|
|
| 480 |
|
|
--A19:A11 Don't Care
|
| 481 |
|
|
SIGNAL Addr : NATURAL RANGE 0 TO 16#FFFF# := 0;
|
| 482 |
|
|
SIGNAL Mem_address : NATURAL;
|
| 483 |
|
|
--glitch protection
|
| 484 |
|
|
SIGNAL gWE_n : std_logic := '1';
|
| 485 |
|
|
SIGNAL gCE_n : std_logic := '1';
|
| 486 |
|
|
SIGNAL gOE_n : std_logic := '1';
|
| 487 |
|
|
SIGNAL RST : std_logic := '1';
|
| 488 |
|
|
|
| 489 |
|
|
SIGNAL reseted : std_logic := '0';
|
| 490 |
|
|
|
| 491 |
|
|
-- Mem(SecAddr)(Address)....
|
| 492 |
|
|
SHARED VARIABLE Mem : MemArray := (OTHERS =>(OTHERS=> MaxData));
|
| 493 |
|
|
|
| 494 |
|
|
SHARED VARIABLE Sec_Prot : std_logic_vector(SecNum downto 0) :=
|
| 495 |
|
|
(OTHERS => '0');
|
| 496 |
|
|
SHARED VARIABLE SecSi : SecSiType := (OTHERS => 0);
|
| 497 |
|
|
|
| 498 |
|
|
-- timing check violation
|
| 499 |
|
|
SIGNAL Viol : X01 := '0';
|
| 500 |
|
|
|
| 501 |
|
|
SIGNAL FactoryProt : std_logic := '0';
|
| 502 |
|
|
|
| 503 |
|
|
SIGNAL temp_data : INTEGER;
|
| 504 |
|
|
|
| 505 |
|
|
BEGIN
|
| 506 |
|
|
|
| 507 |
|
|
----------------------------------------------------------------------------
|
| 508 |
|
|
--Power Up time 100 ns;
|
| 509 |
|
|
---------------------------------------------------------------------------
|
| 510 |
|
|
PoweredUp <= '1' AFTER 100 ns;
|
| 511 |
|
|
|
| 512 |
|
|
RST <= RESETNeg AFTER 500 ns;
|
| 513 |
|
|
|
| 514 |
|
|
---------------------------------------------------------------------------
|
| 515 |
|
|
-- VITAL Timing Checks Procedures
|
| 516 |
|
|
---------------------------------------------------------------------------
|
| 517 |
|
|
VITALTimingCheck: PROCESS(A, Din, CENeg, OENeg, WENeg, RESETNeg)
|
| 518 |
|
|
-- Timing Check Variables
|
| 519 |
|
|
VARIABLE Tviol_A0_CENeg : X01 := '0';
|
| 520 |
|
|
VARIABLE TD_A0_CENeg : VitalTimingDataType;
|
| 521 |
|
|
|
| 522 |
|
|
VARIABLE Tviol_A0_WENeg : X01 := '0';
|
| 523 |
|
|
VARIABLE TD_A0_WENeg : VitalTimingDataType;
|
| 524 |
|
|
|
| 525 |
|
|
VARIABLE Tviol_DQ0_CENeg : X01 := '0';
|
| 526 |
|
|
VARIABLE TD_DQ0_CENeg : VitalTimingDataType;
|
| 527 |
|
|
|
| 528 |
|
|
VARIABLE Tviol_DQ0_WENeg : X01 := '0';
|
| 529 |
|
|
VARIABLE TD_DQ0_WENeg : VitalTimingDataType;
|
| 530 |
|
|
|
| 531 |
|
|
VARIABLE Tviol_CENeg_RESETNeg : X01 := '0';
|
| 532 |
|
|
VARIABLE TD_CENeg_RESETNeg : VitalTimingDataType;
|
| 533 |
|
|
|
| 534 |
|
|
VARIABLE Tviol_OENeg_RESETNeg : X01 := '0';
|
| 535 |
|
|
VARIABLE TD_OENeg_RESETNeg : VitalTimingDataType;
|
| 536 |
|
|
|
| 537 |
|
|
VARIABLE Tviol_OENeg_WENeg : X01 := '0';
|
| 538 |
|
|
VARIABLE TD_OENeg_WENeg : VitalTimingDataType;
|
| 539 |
|
|
|
| 540 |
|
|
VARIABLE Tviol_OENeg_WENeg_R : X01 := '0';
|
| 541 |
|
|
VARIABLE TD_OENeg_WENeg_R : VitalTimingDataType;
|
| 542 |
|
|
|
| 543 |
|
|
VARIABLE Pviol_RESETNeg : X01 := '0';
|
| 544 |
|
|
VARIABLE PD_RESETNeg : VitalPeriodDataType := VitalPeriodDataInit;
|
| 545 |
|
|
|
| 546 |
|
|
VARIABLE Pviol_CENeg : X01 := '0';
|
| 547 |
|
|
VARIABLE PD_CENeg : VitalPeriodDataType := VitalPeriodDataInit;
|
| 548 |
|
|
|
| 549 |
|
|
VARIABLE Pviol_WENeg : X01 := '0';
|
| 550 |
|
|
VARIABLE PD_WENeg : VitalPeriodDataType := VitalPeriodDataInit;
|
| 551 |
|
|
|
| 552 |
|
|
VARIABLE Pviol_A0 : X01 := '0';
|
| 553 |
|
|
VARIABLE PD_A0 : VitalPeriodDataType := VitalPeriodDataInit;
|
| 554 |
|
|
|
| 555 |
|
|
VARIABLE Violation : X01 := '0';
|
| 556 |
|
|
BEGIN
|
| 557 |
|
|
|
| 558 |
|
|
---------------------------------------------------------------------------
|
| 559 |
|
|
-- Timing Check Section
|
| 560 |
|
|
---------------------------------------------------------------------------
|
| 561 |
|
|
IF (TimingChecksOn) THEN
|
| 562 |
|
|
-- Setup/Hold Check between A and CENeg
|
| 563 |
|
|
VitalSetupHoldCheck (
|
| 564 |
|
|
TestSignal => A,
|
| 565 |
|
|
TestSignalName => "A",
|
| 566 |
|
|
RefSignal => CENeg,
|
| 567 |
|
|
RefSignalName => "CE#",
|
| 568 |
|
|
SetupHigh => tsetup_A0_WENeg,
|
| 569 |
|
|
SetupLow => tsetup_A0_WENeg,
|
| 570 |
|
|
HoldHigh => thold_A0_WENeg,
|
| 571 |
|
|
HoldLow => thold_A0_WENeg,
|
| 572 |
|
|
CheckEnabled => WENeg = '0' AND OENeg = '1',
|
| 573 |
|
|
RefTransition => '\',
|
| 574 |
|
|
HeaderMsg => InstancePath & PartID,
|
| 575 |
|
|
TimingData => TD_A0_CENeg,
|
| 576 |
|
|
Violation => Tviol_A0_CENeg
|
| 577 |
|
|
);
|
| 578 |
|
|
-- Setup/Hold Check between A and WENeg
|
| 579 |
|
|
VitalSetupHoldCheck (
|
| 580 |
|
|
TestSignal => A,
|
| 581 |
|
|
TestSignalName => "A",
|
| 582 |
|
|
RefSignal => WENeg,
|
| 583 |
|
|
RefSignalName => "WE#",
|
| 584 |
|
|
SetupHigh => tsetup_A0_WENeg,
|
| 585 |
|
|
SetupLow => tsetup_A0_WENeg,
|
| 586 |
|
|
HoldHigh => thold_A0_WENeg,
|
| 587 |
|
|
HoldLow => thold_A0_WENeg,
|
| 588 |
|
|
CheckEnabled => CENeg = '0' AND OENeg = '1',
|
| 589 |
|
|
RefTransition => '\',
|
| 590 |
|
|
HeaderMsg => InstancePath & PartID,
|
| 591 |
|
|
TimingData => TD_A0_WENeg,
|
| 592 |
|
|
Violation => Tviol_A0_WENeg
|
| 593 |
|
|
);
|
| 594 |
|
|
-- Setup/Hold Check between DQ and CENeg
|
| 595 |
|
|
VitalSetupHoldCheck (
|
| 596 |
|
|
TestSignal => DQ0,
|
| 597 |
|
|
TestSignalName => "DQ",
|
| 598 |
|
|
RefSignal => CENeg,
|
| 599 |
|
|
RefSignalName => "CE#",
|
| 600 |
|
|
SetupHigh => tsetup_DQ0_WENeg,
|
| 601 |
|
|
SetupLow => tsetup_DQ0_WENeg,
|
| 602 |
|
|
HoldHigh => thold_DQ0_CENeg,
|
| 603 |
|
|
HoldLow => thold_DQ0_CENeg,
|
| 604 |
|
|
CheckEnabled => WENeg = '0' AND OENeg = '1',
|
| 605 |
|
|
RefTransition => '/',
|
| 606 |
|
|
HeaderMsg => InstancePath & PartID,
|
| 607 |
|
|
TimingData => TD_DQ0_CENeg,
|
| 608 |
|
|
Violation => Tviol_DQ0_CENeg
|
| 609 |
|
|
);
|
| 610 |
|
|
-- Setup/Hold Check between DQ and WENeg
|
| 611 |
|
|
VitalSetupHoldCheck (
|
| 612 |
|
|
TestSignal => DQ0,
|
| 613 |
|
|
TestSignalName => "DQ",
|
| 614 |
|
|
RefSignal => WENeg,
|
| 615 |
|
|
RefSignalName => "WE#",
|
| 616 |
|
|
SetupHigh => tsetup_DQ0_WENeg,
|
| 617 |
|
|
SetupLow => tsetup_DQ0_WENeg,
|
| 618 |
|
|
HoldHigh => thold_DQ0_CENeg,
|
| 619 |
|
|
HoldLow => thold_DQ0_CENeg,
|
| 620 |
|
|
CheckEnabled => CENeg = '0' AND OENeg = '1',
|
| 621 |
|
|
RefTransition => '/',
|
| 622 |
|
|
HeaderMsg => InstancePath & PartID,
|
| 623 |
|
|
TimingData => TD_DQ0_WENeg,
|
| 624 |
|
|
Violation => Tviol_DQ0_WENeg
|
| 625 |
|
|
);
|
| 626 |
|
|
-- Hold Check between CENeg and RESETNeg
|
| 627 |
|
|
VitalSetupHoldCheck (
|
| 628 |
|
|
TestSignal => CENeg,
|
| 629 |
|
|
TestSignalName => "CE#",
|
| 630 |
|
|
RefSignal => RESETNeg,
|
| 631 |
|
|
RefSignalName => "RESET#",
|
| 632 |
|
|
HoldHigh => thold_CENeg_RESETNeg,
|
| 633 |
|
|
CheckEnabled => TRUE,
|
| 634 |
|
|
RefTransition => '/',
|
| 635 |
|
|
HeaderMsg => InstancePath & PartID,
|
| 636 |
|
|
TimingData => TD_CENeg_RESETNeg,
|
| 637 |
|
|
Violation => Tviol_CENeg_RESETNeg
|
| 638 |
|
|
);
|
| 639 |
|
|
-- Hold Check between OENeg and RESETNeg
|
| 640 |
|
|
VitalSetupHoldCheck (
|
| 641 |
|
|
TestSignal => OENeg,
|
| 642 |
|
|
TestSignalName => "OE#",
|
| 643 |
|
|
RefSignal => RESETNeg,
|
| 644 |
|
|
RefSignalName => "RESET#",
|
| 645 |
|
|
HoldHigh => thold_CENeg_RESETNeg,
|
| 646 |
|
|
CheckEnabled => TRUE,
|
| 647 |
|
|
RefTransition => '/',
|
| 648 |
|
|
HeaderMsg => InstancePath & PartID,
|
| 649 |
|
|
TimingData => TD_OENeg_RESETNeg,
|
| 650 |
|
|
Violation => Tviol_OENeg_RESETNeg
|
| 651 |
|
|
);
|
| 652 |
|
|
|
| 653 |
|
|
VitalSetupHoldCheck (
|
| 654 |
|
|
TestSignal => OENeg,
|
| 655 |
|
|
TestSignalName => "OE#",
|
| 656 |
|
|
RefSignal => WENeg,
|
| 657 |
|
|
RefSignalName => "WE#",
|
| 658 |
|
|
HoldHigh => thold_OENeg_WENeg_noedge_posedge,--toeh
|
| 659 |
|
|
HoldLow => thold_OENeg_WENeg_noedge_posedge,--toeh
|
| 660 |
|
|
CheckEnabled => PDONE = '0' OR EDONE = '0',--toggle
|
| 661 |
|
|
RefTransition => '/',
|
| 662 |
|
|
HeaderMsg => InstancePath & PartID,
|
| 663 |
|
|
TimingData => TD_OENeg_WENeg,
|
| 664 |
|
|
Violation => Tviol_OENeg_WENeg
|
| 665 |
|
|
);
|
| 666 |
|
|
VitalSetupHoldCheck (
|
| 667 |
|
|
TestSignal => OENeg,
|
| 668 |
|
|
TestSignalName => "OE#",
|
| 669 |
|
|
RefSignal => WENeg,
|
| 670 |
|
|
RefSignalName => "WE#",
|
| 671 |
|
|
HoldHigh => thold_OENeg_WENeg_noedge_negedge,--toeh
|
| 672 |
|
|
HoldLow => thold_OENeg_WENeg_noedge_negedge,--toeh
|
| 673 |
|
|
CheckEnabled => PDONE = '1' AND EDONE = '1', --read
|
| 674 |
|
|
RefTransition => '/',
|
| 675 |
|
|
HeaderMsg => InstancePath & PartID,
|
| 676 |
|
|
TimingData => TD_OENeg_WENeg_R,
|
| 677 |
|
|
Violation => Tviol_OENeg_WENeg_R
|
| 678 |
|
|
);
|
| 679 |
|
|
|
| 680 |
|
|
-- PulseWidth Check for RESETNeg
|
| 681 |
|
|
VitalPeriodPulseCheck (
|
| 682 |
|
|
TestSignal => RESETNeg,
|
| 683 |
|
|
TestSignalName => "RESET#",
|
| 684 |
|
|
PulseWidthLow => tpw_RESETNeg_negedge,
|
| 685 |
|
|
CheckEnabled => TRUE,
|
| 686 |
|
|
HeaderMsg => InstancePath & PartID,
|
| 687 |
|
|
PeriodData => PD_RESETNeg,
|
| 688 |
|
|
Violation => Pviol_RESETNeg
|
| 689 |
|
|
);
|
| 690 |
|
|
-- PulseWidth Check for WENeg
|
| 691 |
|
|
VitalPeriodPulseCheck (
|
| 692 |
|
|
TestSignal => WENeg,
|
| 693 |
|
|
TestSignalName => "WE#",
|
| 694 |
|
|
PulseWidthHigh => tpw_WENeg_posedge,
|
| 695 |
|
|
PulseWidthLow => tpw_WENeg_negedge,
|
| 696 |
|
|
CheckEnabled => TRUE,
|
| 697 |
|
|
HeaderMsg => InstancePath & PartID,
|
| 698 |
|
|
PeriodData => PD_WENeg,
|
| 699 |
|
|
Violation => Pviol_WENeg
|
| 700 |
|
|
);
|
| 701 |
|
|
-- PulseWidth Check for CENeg
|
| 702 |
|
|
VitalPeriodPulseCheck (
|
| 703 |
|
|
TestSignal => CENeg,
|
| 704 |
|
|
TestSignalName => "CE#",
|
| 705 |
|
|
PulseWidthHigh => tpw_WENeg_posedge,
|
| 706 |
|
|
PulseWidthLow => tpw_WENeg_negedge,
|
| 707 |
|
|
CheckEnabled => TRUE,
|
| 708 |
|
|
HeaderMsg => InstancePath & PartID,
|
| 709 |
|
|
PeriodData => PD_CENeg,
|
| 710 |
|
|
Violation => Pviol_CENeg
|
| 711 |
|
|
);
|
| 712 |
|
|
-- PulseWidth Check for A
|
| 713 |
|
|
VitalPeriodPulseCheck (
|
| 714 |
|
|
TestSignal => A(0),
|
| 715 |
|
|
TestSignalName => "A",
|
| 716 |
|
|
PulseWidthHigh => tpw_A0_negedge,
|
| 717 |
|
|
PulseWidthLow => tpw_A0_negedge,
|
| 718 |
|
|
CheckEnabled => TRUE,
|
| 719 |
|
|
HeaderMsg => InstancePath & PartID,
|
| 720 |
|
|
PeriodData => PD_A0,
|
| 721 |
|
|
Violation => Pviol_A0
|
| 722 |
|
|
);
|
| 723 |
|
|
|
| 724 |
|
|
Violation := Tviol_A0_CENeg OR
|
| 725 |
|
|
Tviol_A0_WENeg OR
|
| 726 |
|
|
Tviol_DQ0_WENeg OR
|
| 727 |
|
|
Tviol_DQ0_CENeg OR
|
| 728 |
|
|
Tviol_CENeg_RESETNeg OR
|
| 729 |
|
|
Tviol_OENeg_RESETNeg OR
|
| 730 |
|
|
Tviol_OENeg_WENeg_R OR
|
| 731 |
|
|
Tviol_OENeg_WENeg OR
|
| 732 |
|
|
Pviol_RESETNeg OR
|
| 733 |
|
|
Pviol_CENeg OR
|
| 734 |
|
|
Pviol_WENeg OR
|
| 735 |
|
|
Pviol_A0 ;
|
| 736 |
|
|
|
| 737 |
|
|
Viol <= Violation;
|
| 738 |
|
|
|
| 739 |
|
|
ASSERT Violation = '0'
|
| 740 |
|
|
REPORT InstancePath & partID & ": simulation may be" &
|
| 741 |
|
|
" inaccurate due to timing violations"
|
| 742 |
|
|
SEVERITY WARNING;
|
| 743 |
|
|
END IF;
|
| 744 |
|
|
END PROCESS VITALTimingCheck;
|
| 745 |
|
|
|
| 746 |
|
|
----------------------------------------------------------------------------
|
| 747 |
|
|
-- sequential process for reset control and FSM state transition
|
| 748 |
|
|
----------------------------------------------------------------------------
|
| 749 |
|
|
StateTransition : PROCESS(next_state, RESETNeg, RST, READY, PDone, EDone,
|
| 750 |
|
|
PoweredUp)
|
| 751 |
|
|
VARIABLE R : std_logic := '0'; --prog or erase in progress
|
| 752 |
|
|
VARIABLE E : std_logic := '0'; --reset timming error
|
| 753 |
|
|
BEGIN
|
| 754 |
|
|
IF PoweredUp='1' THEN
|
| 755 |
|
|
--Hardware reset timing control
|
| 756 |
|
|
IF falling_edge(RESETNeg) THEN
|
| 757 |
|
|
E := '0';
|
| 758 |
|
|
IF (PDONE='0' OR EDONE='0') THEN
|
| 759 |
|
|
--if program or erase in progress
|
| 760 |
|
|
READY_in <= '1';
|
| 761 |
|
|
R :='1';
|
| 762 |
|
|
ELSE
|
| 763 |
|
|
READY_in <= '0';
|
| 764 |
|
|
R:='0'; --prog or erase not in progress
|
| 765 |
|
|
END IF;
|
| 766 |
|
|
ELSIF rising_edge(RESETNeg) AND RST='1' THEN
|
| 767 |
|
|
--RESET# pulse < tRP
|
| 768 |
|
|
READY_in <= '0';
|
| 769 |
|
|
R := '0';
|
| 770 |
|
|
E := '1';
|
| 771 |
|
|
END IF;
|
| 772 |
|
|
|
| 773 |
|
|
IF RESETNeg='1' AND ( R='0' OR (R='1' AND READY='1')) THEN
|
| 774 |
|
|
current_state <= next_state;
|
| 775 |
|
|
READY_in <= '0';
|
| 776 |
|
|
E := '0';
|
| 777 |
|
|
R := '0';
|
| 778 |
|
|
reseted <= '1';
|
| 779 |
|
|
|
| 780 |
|
|
ELSIF (R='0' AND RESETNeg='0' AND RST='0')OR
|
| 781 |
|
|
(R='1' AND RESETNeg='0' AND RST='0' AND READY='0')OR
|
| 782 |
|
|
(R='1' AND RESETNeg='1' AND RST='0' AND READY='0')OR
|
| 783 |
|
|
(R='1' AND RESETNeg='1' AND RST='1' AND READY='0') THEN
|
| 784 |
|
|
--no state transition while RESET# low
|
| 785 |
|
|
|
| 786 |
|
|
current_state <= RESET; --reset start
|
| 787 |
|
|
reseted <= '0';
|
| 788 |
|
|
END IF;
|
| 789 |
|
|
|
| 790 |
|
|
ELSE
|
| 791 |
|
|
current_state <= RESET; -- reset
|
| 792 |
|
|
reseted <= '0';
|
| 793 |
|
|
E := '0';
|
| 794 |
|
|
R := '0';
|
| 795 |
|
|
END IF;
|
| 796 |
|
|
|
| 797 |
|
|
END PROCESS StateTransition;
|
| 798 |
|
|
|
| 799 |
|
|
---------------------------------------------------------------------------
|
| 800 |
|
|
--Glitch Protection: Inertial Delay does not propagate pulses <5ns
|
| 801 |
|
|
---------------------------------------------------------------------------
|
| 802 |
|
|
gWE_n <= WENeg AFTER 5 ns;
|
| 803 |
|
|
gCE_n <= CENeg AFTER 5 ns;
|
| 804 |
|
|
gOE_n <= OENeg AFTER 5 ns;
|
| 805 |
|
|
|
| 806 |
|
|
---------------------------------------------------------------------------
|
| 807 |
|
|
--Process that reports warning when changes on signals WE#, CE#, OE# are
|
| 808 |
|
|
--discarded
|
| 809 |
|
|
---------------------------------------------------------------------------
|
| 810 |
|
|
PulseWatch : PROCESS (WENeg, CENeg, OENeg, gWE_n, gCE_n, gOE_n)
|
| 811 |
|
|
BEGIN
|
| 812 |
|
|
IF NOW /= 0 ns THEN
|
| 813 |
|
|
IF (WENeg'EVENT AND (WENeg=gWE_n)) THEN
|
| 814 |
|
|
ASSERT false
|
| 815 |
|
|
REPORT "Glitch detected on WE# signals"
|
| 816 |
|
|
SEVERITY warning;
|
| 817 |
|
|
END IF;
|
| 818 |
|
|
IF (CENeg'EVENT AND (CENeg=gCE_n)) THEN
|
| 819 |
|
|
ASSERT false
|
| 820 |
|
|
REPORT "Glitch detected on CE# signals"
|
| 821 |
|
|
SEVERITY warning;
|
| 822 |
|
|
END IF;
|
| 823 |
|
|
IF (OENeg'EVENT AND (OENeg=gOE_n)) THEN
|
| 824 |
|
|
ASSERT false
|
| 825 |
|
|
REPORT "Glitch detected on OE# signals"
|
| 826 |
|
|
SEVERITY warning;
|
| 827 |
|
|
END IF;
|
| 828 |
|
|
END IF;
|
| 829 |
|
|
END PROCESS PulseWatch;
|
| 830 |
|
|
|
| 831 |
|
|
--latch address on rising edge and data on falling edge of write
|
| 832 |
|
|
write_dc: PROCESS (gWE_n, gCE_n, gOE_n, RESETNeg, reseted)
|
| 833 |
|
|
BEGIN
|
| 834 |
|
|
IF RESETNeg /= '0' AND reseted = '1' THEN
|
| 835 |
|
|
IF (gWE_n = '0') AND (gCE_n = '0') AND (gOE_n = '1') THEN
|
| 836 |
|
|
write <= '1';
|
| 837 |
|
|
ELSE
|
| 838 |
|
|
write <= '0';
|
| 839 |
|
|
END IF;
|
| 840 |
|
|
END IF;
|
| 841 |
|
|
|
| 842 |
|
|
IF ((gWE_n = '1') AND (gCE_n = '0') AND (gOE_n = '0') )THEN
|
| 843 |
|
|
read <= '1';
|
| 844 |
|
|
ELSE
|
| 845 |
|
|
read <= '0';
|
| 846 |
|
|
END IF;
|
| 847 |
|
|
|
| 848 |
|
|
END PROCESS write_dc;
|
| 849 |
|
|
|
| 850 |
|
|
---------------------------------------------------------------------------
|
| 851 |
|
|
--Latch address on falling edge of WE# or CE# what ever comes later
|
| 852 |
|
|
--Latches data on rising edge of WE# or CE# what ever comes first
|
| 853 |
|
|
-- also Write cycle decode
|
| 854 |
|
|
---------------------------------------------------------------------------
|
| 855 |
|
|
BusCycleDecode : PROCESS(A, Din, write, WENeg, CENeg, OENeg, reseted)
|
| 856 |
|
|
|
| 857 |
|
|
VARIABLE A_tmp : NATURAL RANGE 0 TO 16#FF#;
|
| 858 |
|
|
VARIABLE SA_tmp : NATURAL RANGE 0 TO SecNum;
|
| 859 |
|
|
VARIABLE A_tmp1 : NATURAL RANGE 0 TO SecSize;
|
| 860 |
|
|
VARIABLE Mem_tmp : NATURAL RANGE 0 TO MemSize;
|
| 861 |
|
|
|
| 862 |
|
|
VARIABLE CE : std_logic;
|
| 863 |
|
|
VARIABLE i : NATURAL;
|
| 864 |
|
|
BEGIN
|
| 865 |
|
|
IF reseted='1' THEN
|
| 866 |
|
|
IF (falling_edge(WENeg) AND CENeg='0' AND OENeg = '1' ) OR
|
| 867 |
|
|
(falling_edge(CENeg) AND WENeg /= OENeg ) OR
|
| 868 |
|
|
(falling_edge(OENeg) AND WENeg='1' AND CENeg = '0' ) OR
|
| 869 |
|
|
( A'EVENT AND WENeg = '1' AND CENeg='0' AND OENeg = '0' )
|
| 870 |
|
|
THEN
|
| 871 |
|
|
A_tmp := to_nat(A(7 downto 0));
|
| 872 |
|
|
SA_tmp := to_nat(A(HiAddrBit downto 16));
|
| 873 |
|
|
A_tmp1 := to_nat(A(15 downto 0));
|
| 874 |
|
|
Mem_tmp := to_nat(A(HiAddrBit downto 0));
|
| 875 |
|
|
AS_addr := to_nat(A(21));
|
| 876 |
|
|
|
| 877 |
|
|
ELSIF (rising_edge(WENeg) OR rising_edge(CENeg))
|
| 878 |
|
|
AND write = '1' THEN
|
| 879 |
|
|
D_tmp <= to_nat(Din);
|
| 880 |
|
|
END IF;
|
| 881 |
|
|
|
| 882 |
|
|
IF rising_edge(write) OR
|
| 883 |
|
|
falling_edge(OENeg) OR
|
| 884 |
|
|
falling_edge(CENeg) OR
|
| 885 |
|
|
(A'EVENT AND WENeg = '1' AND CENeg = '0' AND OENeg = '0') THEN
|
| 886 |
|
|
SecAddr <= SA_tmp;
|
| 887 |
|
|
Address <= A_tmp1;
|
| 888 |
|
|
Mem_address <= Mem_tmp;
|
| 889 |
|
|
Addr <= A_tmp;
|
| 890 |
|
|
CE := CENeg;
|
| 891 |
|
|
END IF;
|
| 892 |
|
|
END IF;
|
| 893 |
|
|
|
| 894 |
|
|
END PROCESS BusCycleDecode;
|
| 895 |
|
|
|
| 896 |
|
|
---------------------------------------------------------------------------
|
| 897 |
|
|
-- Timing control for the Program Operations
|
| 898 |
|
|
---------------------------------------------------------------------------
|
| 899 |
|
|
ProgTime :PROCESS(PSTART, OTP_ACT, ESP_ACT, reseted)
|
| 900 |
|
|
VARIABLE duration : time;
|
| 901 |
|
|
VARIABLE pob : time;
|
| 902 |
|
|
|
| 903 |
|
|
BEGIN
|
| 904 |
|
|
IF LongTimming THEN
|
| 905 |
|
|
pob := tdevice_POB;
|
| 906 |
|
|
ELSE
|
| 907 |
|
|
pob := tdevice_POB/1;
|
| 908 |
|
|
END IF;
|
| 909 |
|
|
IF rising_edge(reseted) THEN
|
| 910 |
|
|
PDONE <= '1'; -- reset done, programing terminated
|
| 911 |
|
|
ELSIF reseted = '1' THEN
|
| 912 |
|
|
IF rising_edge(PSTART) AND PDONE='1' THEN
|
| 913 |
|
|
IF (((Sec_Prot(SA) = '0' AND
|
| 914 |
|
|
(Ers_queue(SA) = '0' OR ESP_ACT = '0')) AND
|
| 915 |
|
|
(OTP_ACT = '0')) OR (OTP_ACT = '1' AND
|
| 916 |
|
|
FactoryProt = '0')) THEN
|
| 917 |
|
|
duration := pob + 5 ns;
|
| 918 |
|
|
PDONE <= '0', '1' AFTER duration;
|
| 919 |
|
|
ELSE
|
| 920 |
|
|
PERR <= '1', '0' AFTER 1005 ns;
|
| 921 |
|
|
END IF;
|
| 922 |
|
|
END IF;
|
| 923 |
|
|
END IF;
|
| 924 |
|
|
END PROCESS ProgTime;
|
| 925 |
|
|
|
| 926 |
|
|
---------------------------------------------------------------------------
|
| 927 |
|
|
-- Timing control for the Erase Operations
|
| 928 |
|
|
---------------------------------------------------------------------------
|
| 929 |
|
|
ErsTime :PROCESS(ESTART, ESUSP, ERES, Ers_Queue, reseted)
|
| 930 |
|
|
VARIABLE cnt : NATURAL RANGE 0 TO SecNum +1 := 0;
|
| 931 |
|
|
VARIABLE elapsed : time;
|
| 932 |
|
|
VARIABLE duration : time;
|
| 933 |
|
|
VARIABLE start : time;
|
| 934 |
|
|
VARIABLE seo : time;
|
| 935 |
|
|
BEGIN
|
| 936 |
|
|
IF LongTimming THEN
|
| 937 |
|
|
seo := tdevice_SEO;
|
| 938 |
|
|
ELSE
|
| 939 |
|
|
seo := tdevice_SEO/100;
|
| 940 |
|
|
END IF;
|
| 941 |
|
|
IF rising_edge(reseted) THEN
|
| 942 |
|
|
EDONE <= '1'; -- reset done, ERASE terminated
|
| 943 |
|
|
ELSIF reseted = '1' THEN
|
| 944 |
|
|
IF rising_edge(ESTART) AND EDONE = '1' THEN
|
| 945 |
|
|
cnt := 0;
|
| 946 |
|
|
FOR i IN Ers_Queue'RANGE LOOP
|
| 947 |
|
|
IF Ers_Queue(i) = '1' AND Sec_Prot(i) /= '1' THEN
|
| 948 |
|
|
cnt := cnt +1;
|
| 949 |
|
|
END IF;
|
| 950 |
|
|
END LOOP;
|
| 951 |
|
|
IF cnt > 0 THEN
|
| 952 |
|
|
elapsed := 0 ns;
|
| 953 |
|
|
duration := cnt* seo;
|
| 954 |
|
|
EDONE <= '0', '1' AFTER duration + 5 ns;
|
| 955 |
|
|
start := NOW;
|
| 956 |
|
|
ELSE
|
| 957 |
|
|
EERR <= '1', '0' AFTER 100005 ns;
|
| 958 |
|
|
END IF;
|
| 959 |
|
|
ELSIF rising_edge(ESUSP) AND EDONE = '0' THEN
|
| 960 |
|
|
elapsed := NOW - start;
|
| 961 |
|
|
duration := duration - elapsed;
|
| 962 |
|
|
EDONE <= '0';
|
| 963 |
|
|
ELSIF rising_edge(ERES) AND EDONE = '0' THEN
|
| 964 |
|
|
start := NOW;
|
| 965 |
|
|
EDONE <= '0', '1' AFTER duration;
|
| 966 |
|
|
END IF;
|
| 967 |
|
|
END IF;
|
| 968 |
|
|
END PROCESS;
|
| 969 |
|
|
|
| 970 |
|
|
---------------------------------------------------------------------------
|
| 971 |
|
|
-- Main Behavior Process
|
| 972 |
|
|
-- combinational process for next state generation
|
| 973 |
|
|
---------------------------------------------------------------------------
|
| 974 |
|
|
StateGen :PROCESS(write, Addr, D_tmp, ULBYPASS, PDONE, EDONE, HANG, CTMOUT,
|
| 975 |
|
|
START_T1, reseted, READY, PERR, EERR)
|
| 976 |
|
|
VARIABLE PATTERN_1 : boolean := FALSE;
|
| 977 |
|
|
VARIABLE PATTERN_2 : boolean := FALSE;
|
| 978 |
|
|
VARIABLE A_PAT_1 : boolean := FALSE;
|
| 979 |
|
|
VARIABLE A_PAT_2 : boolean := FALSE;
|
| 980 |
|
|
VARIABLE A_PAT_3 : boolean := FALSE;
|
| 981 |
|
|
VARIABLE DataByte : NATURAL RANGE 0 TO MaxData := 0;
|
| 982 |
|
|
BEGIN
|
| 983 |
|
|
-----------------------------------------------------------------------
|
| 984 |
|
|
-- Functionality Section
|
| 985 |
|
|
-----------------------------------------------------------------------
|
| 986 |
|
|
IF falling_edge(write) THEN
|
| 987 |
|
|
DataByte := D_tmp;
|
| 988 |
|
|
PATTERN_1 := DataByte = 16#AA# ;
|
| 989 |
|
|
PATTERN_2 := DataByte = 16#55# ;
|
| 990 |
|
|
A_PAT_1 := TRUE;
|
| 991 |
|
|
A_PAT_2 := (Address = 16#AAA#);
|
| 992 |
|
|
A_PAT_3 := (Address = 16#555#);
|
| 993 |
|
|
END IF;
|
| 994 |
|
|
IF reseted /= '1' THEN
|
| 995 |
|
|
next_state <= current_state;
|
| 996 |
|
|
ELSE
|
| 997 |
|
|
CASE current_state IS
|
| 998 |
|
|
WHEN RESET =>
|
| 999 |
|
|
IF falling_edge(write) THEN
|
| 1000 |
|
|
IF (PATTERN_1)THEN
|
| 1001 |
|
|
next_state <= Z001;
|
| 1002 |
|
|
ELSIF (DataByte=16#98#) THEN
|
| 1003 |
|
|
next_state <= CFI;
|
| 1004 |
|
|
ELSE
|
| 1005 |
|
|
next_state <= RESET;
|
| 1006 |
|
|
END IF;
|
| 1007 |
|
|
END IF;
|
| 1008 |
|
|
|
| 1009 |
|
|
WHEN Z001 =>
|
| 1010 |
|
|
IF falling_edge(write) THEN
|
| 1011 |
|
|
IF (PATTERN_2) THEN
|
| 1012 |
|
|
next_state <= PREL_SETBWB;
|
| 1013 |
|
|
ELSE
|
| 1014 |
|
|
next_state <= RESET;
|
| 1015 |
|
|
END IF;
|
| 1016 |
|
|
END IF;
|
| 1017 |
|
|
|
| 1018 |
|
|
WHEN CFI =>
|
| 1019 |
|
|
IF falling_edge(write) THEN
|
| 1020 |
|
|
IF (D_tmp=16#F0#) THEN
|
| 1021 |
|
|
next_state <= RESET;
|
| 1022 |
|
|
ELSE
|
| 1023 |
|
|
next_state <= CFI;
|
| 1024 |
|
|
END IF;
|
| 1025 |
|
|
END IF;
|
| 1026 |
|
|
|
| 1027 |
|
|
WHEN PREL_SETBWB =>
|
| 1028 |
|
|
IF falling_edge(write) THEN
|
| 1029 |
|
|
IF (A_PAT_1 AND (DataByte = 16#20#)) THEN
|
| 1030 |
|
|
next_state <= PREL_ULBYPASS;
|
| 1031 |
|
|
ELSIF (A_PAT_1 AND (DataByte = 16#90#)) THEN
|
| 1032 |
|
|
next_state <= AS;
|
| 1033 |
|
|
ELSIF (A_PAT_1 AND (DataByte = 16#88#)) THEN
|
| 1034 |
|
|
next_state <= OTP;
|
| 1035 |
|
|
ELSIF (A_PAT_1 AND (DataByte = 16#A0#)) THEN
|
| 1036 |
|
|
next_state <= A0SEEN;
|
| 1037 |
|
|
ELSIF (A_PAT_1 AND (DataByte = 16#80#)) THEN
|
| 1038 |
|
|
next_state <= C8;
|
| 1039 |
|
|
ELSE
|
| 1040 |
|
|
next_state <= RESET;
|
| 1041 |
|
|
END IF;
|
| 1042 |
|
|
END IF;
|
| 1043 |
|
|
|
| 1044 |
|
|
WHEN PREL_ULBYPASS =>
|
| 1045 |
|
|
IF falling_edge(write) THEN
|
| 1046 |
|
|
IF (DataByte = 16#90#) THEN
|
| 1047 |
|
|
next_state <= PREL_ULBYPASS_RESET;
|
| 1048 |
|
|
ELSIF (A_PAT_1 AND (DataByte = 16#A0#)) THEN
|
| 1049 |
|
|
next_state <= A0SEEN;
|
| 1050 |
|
|
ELSE
|
| 1051 |
|
|
next_state <= PREL_ULBYPASS;
|
| 1052 |
|
|
END IF;
|
| 1053 |
|
|
END IF;
|
| 1054 |
|
|
|
| 1055 |
|
|
WHEN PREL_ULBYPASS_RESET =>
|
| 1056 |
|
|
IF falling_edge(write) THEN
|
| 1057 |
|
|
IF (DataByte = 16#00#) THEN
|
| 1058 |
|
|
IF ESP_ACT = '1' THEN
|
| 1059 |
|
|
next_state <= ESP;
|
| 1060 |
|
|
ELSE
|
| 1061 |
|
|
next_state <= RESET;
|
| 1062 |
|
|
END IF;
|
| 1063 |
|
|
ELSE
|
| 1064 |
|
|
next_state <= PREL_ULBYPASS;
|
| 1065 |
|
|
END IF;
|
| 1066 |
|
|
END IF;
|
| 1067 |
|
|
|
| 1068 |
|
|
WHEN AS =>
|
| 1069 |
|
|
IF falling_edge(write) THEN
|
| 1070 |
|
|
IF (DataByte = 16#F0#) THEN
|
| 1071 |
|
|
next_state <= RESET;
|
| 1072 |
|
|
ELSIF (D_tmp=16#98#) THEN
|
| 1073 |
|
|
next_state <= AS_CFI;
|
| 1074 |
|
|
ELSE
|
| 1075 |
|
|
next_state <= AS;
|
| 1076 |
|
|
END IF;
|
| 1077 |
|
|
END IF;
|
| 1078 |
|
|
|
| 1079 |
|
|
WHEN AS_CFI =>
|
| 1080 |
|
|
IF falling_edge(write) THEN
|
| 1081 |
|
|
IF (D_tmp=16#F0#) THEN
|
| 1082 |
|
|
next_state <= AS;
|
| 1083 |
|
|
ELSE
|
| 1084 |
|
|
next_state <= AS_CFI;
|
| 1085 |
|
|
END IF;
|
| 1086 |
|
|
END IF;
|
| 1087 |
|
|
|
| 1088 |
|
|
WHEN A0SEEN =>
|
| 1089 |
|
|
IF falling_edge(write) THEN
|
| 1090 |
|
|
next_state <= PGMS;
|
| 1091 |
|
|
ELSE
|
| 1092 |
|
|
next_state <= A0SEEN;
|
| 1093 |
|
|
END IF;
|
| 1094 |
|
|
|
| 1095 |
|
|
WHEN OTP =>
|
| 1096 |
|
|
IF falling_edge(write) THEN
|
| 1097 |
|
|
IF PATTERN_1 THEN
|
| 1098 |
|
|
next_state <= OTP_Z001;
|
| 1099 |
|
|
ELSE
|
| 1100 |
|
|
next_state <= OTP;
|
| 1101 |
|
|
END IF;
|
| 1102 |
|
|
END IF;
|
| 1103 |
|
|
|
| 1104 |
|
|
WHEN OTP_Z001 =>
|
| 1105 |
|
|
IF falling_edge(write) THEN
|
| 1106 |
|
|
IF PATTERN_2 THEN
|
| 1107 |
|
|
next_state <= OTP_PREL;
|
| 1108 |
|
|
ELSE
|
| 1109 |
|
|
next_state <= OTP;
|
| 1110 |
|
|
END IF;
|
| 1111 |
|
|
END IF;
|
| 1112 |
|
|
|
| 1113 |
|
|
WHEN OTP_PREL =>
|
| 1114 |
|
|
IF falling_edge(write) THEN
|
| 1115 |
|
|
IF (DataByte = 16#90#) THEN
|
| 1116 |
|
|
next_state <= OTP_AS;
|
| 1117 |
|
|
ELSIF (DataByte = 16#A0#) THEN
|
| 1118 |
|
|
next_state <= OTP_A0SEEN;
|
| 1119 |
|
|
ELSE
|
| 1120 |
|
|
next_state <= OTP;
|
| 1121 |
|
|
END IF;
|
| 1122 |
|
|
END IF;
|
| 1123 |
|
|
|
| 1124 |
|
|
WHEN OTP_AS =>
|
| 1125 |
|
|
IF falling_edge(write) THEN
|
| 1126 |
|
|
IF (DataByte = 16#00#) THEN
|
| 1127 |
|
|
IF ESP_ACT = '1' THEN
|
| 1128 |
|
|
next_state <= ESP;
|
| 1129 |
|
|
ELSE
|
| 1130 |
|
|
next_state <= RESET;
|
| 1131 |
|
|
END IF;
|
| 1132 |
|
|
ELSIF (DataByte = 16#F0#) THEN
|
| 1133 |
|
|
next_state <= OTP;
|
| 1134 |
|
|
ELSIF (DataByte = 16#98#) THEN
|
| 1135 |
|
|
next_state <= OTP_AS_CFI;
|
| 1136 |
|
|
ELSE
|
| 1137 |
|
|
next_state <= OTP_AS;
|
| 1138 |
|
|
END IF;
|
| 1139 |
|
|
END IF;
|
| 1140 |
|
|
|
| 1141 |
|
|
WHEN OTP_AS_CFI =>
|
| 1142 |
|
|
IF falling_edge(write) THEN
|
| 1143 |
|
|
IF (DataByte = 16#F0#) THEN
|
| 1144 |
|
|
next_state <= OTP_AS;
|
| 1145 |
|
|
ELSE
|
| 1146 |
|
|
next_state <= OTP_AS_CFI;
|
| 1147 |
|
|
END IF;
|
| 1148 |
|
|
END IF;
|
| 1149 |
|
|
|
| 1150 |
|
|
WHEN OTP_A0SEEN =>
|
| 1151 |
|
|
IF falling_edge(write) THEN
|
| 1152 |
|
|
IF ((Address >= 16#FF00#) AND (Address <= 16#FFFF#)
|
| 1153 |
|
|
AND (SecAddr = 16#3F#)) THEN
|
| 1154 |
|
|
next_state <= PGMS;
|
| 1155 |
|
|
ELSE
|
| 1156 |
|
|
next_state <= OTP;
|
| 1157 |
|
|
END IF;
|
| 1158 |
|
|
END IF;
|
| 1159 |
|
|
|
| 1160 |
|
|
WHEN C8 =>
|
| 1161 |
|
|
IF falling_edge(write) THEN
|
| 1162 |
|
|
IF PATTERN_1 THEN
|
| 1163 |
|
|
next_state <= C8_Z001;
|
| 1164 |
|
|
ELSE
|
| 1165 |
|
|
next_state <= RESET;
|
| 1166 |
|
|
END IF;
|
| 1167 |
|
|
END IF;
|
| 1168 |
|
|
|
| 1169 |
|
|
WHEN C8_Z001 =>
|
| 1170 |
|
|
IF falling_edge(write) THEN
|
| 1171 |
|
|
IF PATTERN_2 THEN
|
| 1172 |
|
|
next_state <= C8_PREL;
|
| 1173 |
|
|
ELSE
|
| 1174 |
|
|
next_state <= RESET;
|
| 1175 |
|
|
END IF;
|
| 1176 |
|
|
END IF;
|
| 1177 |
|
|
|
| 1178 |
|
|
WHEN C8_PREL =>
|
| 1179 |
|
|
IF falling_edge(write) THEN
|
| 1180 |
|
|
IF A_PAT_1 AND DataByte = 16#10# THEN
|
| 1181 |
|
|
next_state <= ERS;
|
| 1182 |
|
|
ELSIF DataByte = 16#30# THEN
|
| 1183 |
|
|
next_state <= SERS;
|
| 1184 |
|
|
ELSE
|
| 1185 |
|
|
next_state <= RESET;
|
| 1186 |
|
|
END IF;
|
| 1187 |
|
|
END IF;
|
| 1188 |
|
|
|
| 1189 |
|
|
WHEN ERS =>
|
| 1190 |
|
|
IF rising_edge(EDONE) OR falling_edge(EERR) THEN
|
| 1191 |
|
|
next_state <= RESET;
|
| 1192 |
|
|
END IF;
|
| 1193 |
|
|
|
| 1194 |
|
|
WHEN SERS =>
|
| 1195 |
|
|
IF CTMOUT = '1' THEN
|
| 1196 |
|
|
next_state <= SERS_EXEC;
|
| 1197 |
|
|
ELSIF falling_edge(write) THEN
|
| 1198 |
|
|
IF (DataByte = 16#B0#) THEN
|
| 1199 |
|
|
next_state <= ESP;
|
| 1200 |
|
|
ELSIF (DataByte = 16#30#) THEN
|
| 1201 |
|
|
next_state <= SERS;
|
| 1202 |
|
|
ELSE
|
| 1203 |
|
|
next_state <= RESET;
|
| 1204 |
|
|
END IF;
|
| 1205 |
|
|
END IF;
|
| 1206 |
|
|
|
| 1207 |
|
|
WHEN ESPS =>
|
| 1208 |
|
|
IF (START_T1 = '1') THEN
|
| 1209 |
|
|
next_state <= ESP;
|
| 1210 |
|
|
END IF;
|
| 1211 |
|
|
|
| 1212 |
|
|
WHEN SERS_EXEC =>
|
| 1213 |
|
|
IF rising_edge(EDONE) OR falling_edge(EERR) THEN
|
| 1214 |
|
|
next_state <= RESET;
|
| 1215 |
|
|
ELSIF EERR /= '1' THEN
|
| 1216 |
|
|
IF falling_edge(write) THEN
|
| 1217 |
|
|
IF DataByte = 16#B0# THEN
|
| 1218 |
|
|
next_state <= ESPS;
|
| 1219 |
|
|
END IF;
|
| 1220 |
|
|
END IF;
|
| 1221 |
|
|
END IF;
|
| 1222 |
|
|
|
| 1223 |
|
|
WHEN ESP =>
|
| 1224 |
|
|
IF falling_edge(write) THEN
|
| 1225 |
|
|
IF DataByte = 16#30# THEN
|
| 1226 |
|
|
next_state <= SERS_EXEC;
|
| 1227 |
|
|
ELSE
|
| 1228 |
|
|
IF PATTERN_1 THEN
|
| 1229 |
|
|
next_state <= ESP_Z001;
|
| 1230 |
|
|
ELSIF D_tmp = 16#98# THEN
|
| 1231 |
|
|
next_state <= ESP_CFI;
|
| 1232 |
|
|
END IF;
|
| 1233 |
|
|
END IF;
|
| 1234 |
|
|
END IF;
|
| 1235 |
|
|
|
| 1236 |
|
|
WHEN ESP_CFI =>
|
| 1237 |
|
|
IF falling_edge(write) THEN
|
| 1238 |
|
|
IF D_tmp = 16#F0# THEN
|
| 1239 |
|
|
next_state <= ESP;
|
| 1240 |
|
|
ELSE
|
| 1241 |
|
|
next_state <= ESP_CFI;
|
| 1242 |
|
|
END IF;
|
| 1243 |
|
|
END IF;
|
| 1244 |
|
|
|
| 1245 |
|
|
WHEN ESP_Z001 =>
|
| 1246 |
|
|
IF falling_edge(write) THEN
|
| 1247 |
|
|
IF PATTERN_2 THEN
|
| 1248 |
|
|
next_state <= ESP_PREL;
|
| 1249 |
|
|
ELSE
|
| 1250 |
|
|
next_state <= ESP;
|
| 1251 |
|
|
END IF;
|
| 1252 |
|
|
END IF;
|
| 1253 |
|
|
|
| 1254 |
|
|
WHEN ESP_PREL =>
|
| 1255 |
|
|
IF falling_edge(write) THEN
|
| 1256 |
|
|
IF A_PAT_1 AND DataByte = 16#A0# THEN
|
| 1257 |
|
|
next_state <= A0SEEN;
|
| 1258 |
|
|
ELSIF A_PAT_1 AND DataByte = 16#20# THEN
|
| 1259 |
|
|
next_state <= PREL_ULBYPASS;
|
| 1260 |
|
|
ELSIF A_PAT_1 AND DataByte = 16#88# THEN
|
| 1261 |
|
|
next_state <= OTP;
|
| 1262 |
|
|
ELSIF A_PAT_1 AND DataByte = 16#90# THEN
|
| 1263 |
|
|
next_state <= ESP_AS;
|
| 1264 |
|
|
ELSE
|
| 1265 |
|
|
next_state <= ESP;
|
| 1266 |
|
|
END IF;
|
| 1267 |
|
|
END IF;
|
| 1268 |
|
|
|
| 1269 |
|
|
WHEN ESP_AS =>
|
| 1270 |
|
|
IF falling_edge(write) THEN
|
| 1271 |
|
|
IF DataByte = 16#F0# THEN
|
| 1272 |
|
|
next_state <= ESP;
|
| 1273 |
|
|
ELSIF (D_tmp=16#98#) THEN
|
| 1274 |
|
|
next_state <= ESP_AS_CFI;
|
| 1275 |
|
|
END IF;
|
| 1276 |
|
|
END IF;
|
| 1277 |
|
|
|
| 1278 |
|
|
WHEN ESP_AS_CFI =>
|
| 1279 |
|
|
IF falling_edge(write) THEN
|
| 1280 |
|
|
IF D_tmp = 16#F0# THEN
|
| 1281 |
|
|
next_state <= ESP_AS;
|
| 1282 |
|
|
ELSE
|
| 1283 |
|
|
next_state <= ESP_AS_CFI;
|
| 1284 |
|
|
END IF;
|
| 1285 |
|
|
END IF;
|
| 1286 |
|
|
|
| 1287 |
|
|
WHEN PGMS =>
|
| 1288 |
|
|
IF rising_edge(PDONE) OR falling_edge(PERR) THEN
|
| 1289 |
|
|
IF ULBYPASS = '1' THEN
|
| 1290 |
|
|
next_state <= PREL_ULBYPASS;
|
| 1291 |
|
|
ELSIF OTP_ACT = '1' THEN
|
| 1292 |
|
|
next_state <= OTP;
|
| 1293 |
|
|
ELSIF ESP_ACT = '1' THEN
|
| 1294 |
|
|
next_state <= ESP;
|
| 1295 |
|
|
ELSE
|
| 1296 |
|
|
next_state <= RESET;
|
| 1297 |
|
|
END IF;
|
| 1298 |
|
|
END IF;
|
| 1299 |
|
|
|
| 1300 |
|
|
END CASE;
|
| 1301 |
|
|
END IF;
|
| 1302 |
|
|
END PROCESS StateGen;
|
| 1303 |
|
|
|
| 1304 |
|
|
---------------------------------------------------------------------------
|
| 1305 |
|
|
--FSM Output generation and general funcionality
|
| 1306 |
|
|
---------------------------------------------------------------------------
|
| 1307 |
|
|
Functional : PROCESS(write, read, D_tmp, D_tmp1, Mem_address,
|
| 1308 |
|
|
PDONE, EDONE, HANG, START_T1, CTMOUT, RST, reseted,
|
| 1309 |
|
|
READY, gOE_n, current_state)
|
| 1310 |
|
|
|
| 1311 |
|
|
--Common Flash Interface Query codes
|
| 1312 |
|
|
TYPE CFItype IS ARRAY (16#10# TO 16#4F#) OF
|
| 1313 |
|
|
INTEGER RANGE -1 TO 16#FF#;
|
| 1314 |
|
|
VARIABLE CFI_array : CFItype := (OTHERS => -1);
|
| 1315 |
|
|
|
| 1316 |
|
|
--Program
|
| 1317 |
|
|
VARIABLE WData : INTEGER RANGE -1 TO MaxData;
|
| 1318 |
|
|
VARIABLE WAddr : INTEGER RANGE -1 TO SecSize;
|
| 1319 |
|
|
VARIABLE cnt : NATURAL RANGE 0 TO 31 := 0;
|
| 1320 |
|
|
|
| 1321 |
|
|
VARIABLE PATTERN_1 : boolean := FALSE;
|
| 1322 |
|
|
VARIABLE PATTERN_2 : boolean := FALSE;
|
| 1323 |
|
|
VARIABLE A_PAT_1 : boolean := FALSE;
|
| 1324 |
|
|
|
| 1325 |
|
|
VARIABLE A_PAT_2 : boolean := FALSE;
|
| 1326 |
|
|
VARIABLE A_PAT_3 : boolean := FALSE;
|
| 1327 |
|
|
VARIABLE oe : boolean := FALSE;
|
| 1328 |
|
|
--Status reg.
|
| 1329 |
|
|
VARIABLE Status : std_logic_vector(7 downto 0):= (OTHERS=>'0');
|
| 1330 |
|
|
|
| 1331 |
|
|
VARIABLE old_bit : std_logic_vector(7 downto 0);
|
| 1332 |
|
|
VARIABLE new_bit : std_logic_vector(7 downto 0);
|
| 1333 |
|
|
VARIABLE old_int : INTEGER RANGE -1 to MaxData;
|
| 1334 |
|
|
VARIABLE new_int : INTEGER RANGE -1 to MaxData;
|
| 1335 |
|
|
VARIABLE wr_cnt : NATURAL RANGE 0 TO 31;
|
| 1336 |
|
|
|
| 1337 |
|
|
--DATA Byte
|
| 1338 |
|
|
VARIABLE DataByte : NATURAL RANGE 0 TO MaxData := 0;
|
| 1339 |
|
|
|
| 1340 |
|
|
VARIABLE SecSiAddr : NATURAL RANGE 0 TO SecSiSize := 0;
|
| 1341 |
|
|
|
| 1342 |
|
|
VARIABLE temp : std_logic_vector(7 downto 0);
|
| 1343 |
|
|
|
| 1344 |
|
|
BEGIN
|
| 1345 |
|
|
-----------------------------------------------------------------------
|
| 1346 |
|
|
-- Functionality Section
|
| 1347 |
|
|
-----------------------------------------------------------------------
|
| 1348 |
|
|
IF falling_edge(write) THEN
|
| 1349 |
|
|
DataByte := D_tmp;
|
| 1350 |
|
|
PATTERN_1 := DataByte = 16#AA# ;
|
| 1351 |
|
|
PATTERN_2 := DataByte = 16#55# ;
|
| 1352 |
|
|
A_PAT_1 := TRUE;
|
| 1353 |
|
|
A_PAT_2 := (Address = 16#AAA#);
|
| 1354 |
|
|
A_PAT_3 := (Address = 16#555#);
|
| 1355 |
|
|
|
| 1356 |
|
|
END IF;
|
| 1357 |
|
|
oe:= rising_edge(read) OR (read = '1' AND Mem_address'EVENT);
|
| 1358 |
|
|
IF reseted = '1' THEN
|
| 1359 |
|
|
CASE current_state IS
|
| 1360 |
|
|
WHEN RESET =>
|
| 1361 |
|
|
ESP_ACT <= '0';
|
| 1362 |
|
|
OTP_ACT <= '0';
|
| 1363 |
|
|
ULBYPASS <= '0';
|
| 1364 |
|
|
CTMOUT_in <= '0';
|
| 1365 |
|
|
IF falling_edge(write) THEN
|
| 1366 |
|
|
IF A_PAT_2 AND PATTERN_1 THEN
|
| 1367 |
|
|
AS_SecSi_FP := '1';
|
| 1368 |
|
|
ELSE
|
| 1369 |
|
|
AS_SecSi_FP := '0';
|
| 1370 |
|
|
END IF;
|
| 1371 |
|
|
END IF;
|
| 1372 |
|
|
IF oe THEN
|
| 1373 |
|
|
IF Mem(SecAddr)(Address) = -1 THEN
|
| 1374 |
|
|
DOut_zd <= (OTHERS=>'X');
|
| 1375 |
|
|
ELSE
|
| 1376 |
|
|
DOut_zd <= to_slv(Mem(SecAddr)(Address),8);
|
| 1377 |
|
|
END IF;
|
| 1378 |
|
|
END IF;
|
| 1379 |
|
|
--ready signal active
|
| 1380 |
|
|
RY_zd <= '1';
|
| 1381 |
|
|
|
| 1382 |
|
|
WHEN Z001 =>
|
| 1383 |
|
|
IF falling_edge(write)THEN
|
| 1384 |
|
|
IF A_PAT_3 AND PATTERN_2 THEN
|
| 1385 |
|
|
null;
|
| 1386 |
|
|
ELSE
|
| 1387 |
|
|
AS_SecSi_FP := '0';
|
| 1388 |
|
|
END IF;
|
| 1389 |
|
|
END IF;
|
| 1390 |
|
|
|
| 1391 |
|
|
null;
|
| 1392 |
|
|
|
| 1393 |
|
|
WHEN PREL_SETBWB =>
|
| 1394 |
|
|
IF falling_edge(write) THEN
|
| 1395 |
|
|
IF (A_PAT_1 AND (DataByte = 16#20#)) THEN
|
| 1396 |
|
|
ULBYPASS <= '1';
|
| 1397 |
|
|
ELSIF (A_PAT_1 AND (DataByte = 16#90#)) THEN
|
| 1398 |
|
|
IF A_PAT_2 THEN
|
| 1399 |
|
|
null;
|
| 1400 |
|
|
ELSE
|
| 1401 |
|
|
AS_SecSi_FP := '0';
|
| 1402 |
|
|
END IF;
|
| 1403 |
|
|
IF AS_addr = 0 THEN
|
| 1404 |
|
|
AS_ID := TRUE;
|
| 1405 |
|
|
AS_ID2:= FALSE;
|
| 1406 |
|
|
ELSE
|
| 1407 |
|
|
AS_ID := FALSE;
|
| 1408 |
|
|
AS_ID2:= TRUE;
|
| 1409 |
|
|
END IF;
|
| 1410 |
|
|
ULBYPASS <= '0';
|
| 1411 |
|
|
ELSIF (A_PAT_1 AND (DataByte = 16#88#)) THEN
|
| 1412 |
|
|
ULBYPASS <= '0';
|
| 1413 |
|
|
OTP_ACT <= '1';
|
| 1414 |
|
|
END IF;
|
| 1415 |
|
|
END IF;
|
| 1416 |
|
|
|
| 1417 |
|
|
WHEN PREL_ULBYPASS =>
|
| 1418 |
|
|
ULBYPASS <= '1';
|
| 1419 |
|
|
IF falling_edge(write) THEN
|
| 1420 |
|
|
IF (A_PAT_1 AND (DataByte = 16#90#)) THEN
|
| 1421 |
|
|
ULBYPASS <= '0';
|
| 1422 |
|
|
END IF;
|
| 1423 |
|
|
END IF;
|
| 1424 |
|
|
--ready signal active
|
| 1425 |
|
|
RY_zd <= '1';
|
| 1426 |
|
|
|
| 1427 |
|
|
WHEN PREL_ULBYPASS_RESET =>
|
| 1428 |
|
|
IF falling_edge(write) AND (DataByte /= 16#00# ) THEN
|
| 1429 |
|
|
ULBYPASS <= '1';
|
| 1430 |
|
|
END IF;
|
| 1431 |
|
|
|
| 1432 |
|
|
WHEN A0SEEN =>
|
| 1433 |
|
|
IF falling_edge(write) THEN
|
| 1434 |
|
|
PSTART <= '1', '0' AFTER 1 ns;
|
| 1435 |
|
|
WData := DataByte;
|
| 1436 |
|
|
WAddr := Address;
|
| 1437 |
|
|
SA <= SecAddr;
|
| 1438 |
|
|
temp := to_slv(DataByte, 8);
|
| 1439 |
|
|
Status(7) := NOT temp(7);
|
| 1440 |
|
|
END IF;
|
| 1441 |
|
|
|
| 1442 |
|
|
WHEN OTP =>
|
| 1443 |
|
|
OTP_ACT <= '1';
|
| 1444 |
|
|
IF falling_edge(write) THEN
|
| 1445 |
|
|
IF A_PAT_2 AND PATTERN_1 THEN
|
| 1446 |
|
|
AS_SecSi_FP := '1';
|
| 1447 |
|
|
ELSE
|
| 1448 |
|
|
AS_SecSi_FP := '0';
|
| 1449 |
|
|
END IF;
|
| 1450 |
|
|
END IF;
|
| 1451 |
|
|
|
| 1452 |
|
|
IF oe THEN
|
| 1453 |
|
|
IF ((Address >= 16#FF00#) AND (Address <= 16#FFFF#)
|
| 1454 |
|
|
AND (SecAddr = 16#3F#)) THEN
|
| 1455 |
|
|
SecSiAddr := Address MOD (SecSiSize +1);
|
| 1456 |
|
|
IF SecSi(SecSiAddr)=-1 THEN
|
| 1457 |
|
|
DOut_zd <= (OTHERS=>'X');
|
| 1458 |
|
|
ELSE
|
| 1459 |
|
|
DOut_zd <= to_slv(SecSi(SecSiAddr),8);
|
| 1460 |
|
|
END IF;
|
| 1461 |
|
|
ELSE
|
| 1462 |
|
|
ASSERT false
|
| 1463 |
|
|
REPORT "Invalid address in SecSi region. "
|
| 1464 |
|
|
SEVERITY warning;
|
| 1465 |
|
|
END IF;
|
| 1466 |
|
|
END IF;
|
| 1467 |
|
|
-- ready signal active
|
| 1468 |
|
|
Ry_zd <= '1';
|
| 1469 |
|
|
|
| 1470 |
|
|
WHEN OTP_Z001 =>
|
| 1471 |
|
|
IF falling_edge(write) THEN
|
| 1472 |
|
|
IF A_PAT_3 AND PATTERN_2 THEN
|
| 1473 |
|
|
null;
|
| 1474 |
|
|
ELSE
|
| 1475 |
|
|
AS_SecSi_FP := '0';
|
| 1476 |
|
|
END IF;
|
| 1477 |
|
|
END IF;
|
| 1478 |
|
|
|
| 1479 |
|
|
WHEN OTP_PREL =>
|
| 1480 |
|
|
IF falling_edge(write) THEN
|
| 1481 |
|
|
IF (A_PAT_1 AND (DataByte = 16#90#))THEN
|
| 1482 |
|
|
IF A_PAT_2 THEN
|
| 1483 |
|
|
null;
|
| 1484 |
|
|
ELSE
|
| 1485 |
|
|
AS_SecSi_FP := '0';
|
| 1486 |
|
|
END IF;
|
| 1487 |
|
|
IF AS_addr = 0 THEN
|
| 1488 |
|
|
AS_ID := TRUE;
|
| 1489 |
|
|
AS_ID2:= FALSE;
|
| 1490 |
|
|
ELSE
|
| 1491 |
|
|
AS_ID := FALSE;
|
| 1492 |
|
|
AS_ID2:= TRUE;
|
| 1493 |
|
|
END IF;
|
| 1494 |
|
|
ULBYPASS <= '0';
|
| 1495 |
|
|
END IF;
|
| 1496 |
|
|
END IF;
|
| 1497 |
|
|
|
| 1498 |
|
|
WHEN OTP_A0SEEN =>
|
| 1499 |
|
|
IF falling_edge(write) THEN
|
| 1500 |
|
|
IF ((Address >= 16#FF00#) AND (Address <= 16#FFFF#)
|
| 1501 |
|
|
AND (SecAddr = 16#3F#)) THEN
|
| 1502 |
|
|
SecSiAddr := Address MOD (SecSiSize +1);
|
| 1503 |
|
|
OTP_ACT <= '1';
|
| 1504 |
|
|
PSTART <= '1', '0' AFTER 1 ns;
|
| 1505 |
|
|
WData := DataByte;
|
| 1506 |
|
|
WAddr := SecSiAddr;
|
| 1507 |
|
|
SA <= SecAddr;
|
| 1508 |
|
|
temp := to_slv(DataByte, 8);
|
| 1509 |
|
|
Status(7) := NOT temp(7);
|
| 1510 |
|
|
ELSE
|
| 1511 |
|
|
ASSERT false
|
| 1512 |
|
|
REPORT "Invalid program Address in SecSi"
|
| 1513 |
|
|
SEVERITY warning;
|
| 1514 |
|
|
END IF;
|
| 1515 |
|
|
END IF;
|
| 1516 |
|
|
|
| 1517 |
|
|
WHEN CFI | AS_CFI | ESP_CFI | ESP_AS_CFI | OTP_AS_CFI =>
|
| 1518 |
|
|
IF oe THEN
|
| 1519 |
|
|
IF ((Mem_address >= 16#10# AND Mem_address <= 16#3C#) OR
|
| 1520 |
|
|
(Mem_address >= 16#40# AND Mem_address <= 16#4F#))
|
| 1521 |
|
|
THEN
|
| 1522 |
|
|
IF (CFI_array(Address) /= -1) THEN
|
| 1523 |
|
|
DOut_zd <= to_slv(CFI_array(Mem_address),8);
|
| 1524 |
|
|
END IF;
|
| 1525 |
|
|
ELSE
|
| 1526 |
|
|
ASSERT FALSE
|
| 1527 |
|
|
REPORT "Invalid CFI query address"
|
| 1528 |
|
|
SEVERITY warning;
|
| 1529 |
|
|
DOut_zd <= (OTHERS =>'Z');
|
| 1530 |
|
|
END IF;
|
| 1531 |
|
|
END IF;
|
| 1532 |
|
|
|
| 1533 |
|
|
WHEN C8 =>
|
| 1534 |
|
|
IF falling_edge(write) THEN
|
| 1535 |
|
|
null;
|
| 1536 |
|
|
END IF;
|
| 1537 |
|
|
|
| 1538 |
|
|
WHEN C8_Z001 =>
|
| 1539 |
|
|
IF falling_edge(write) THEN
|
| 1540 |
|
|
null;
|
| 1541 |
|
|
END IF;
|
| 1542 |
|
|
|
| 1543 |
|
|
WHEN C8_PREL =>
|
| 1544 |
|
|
IF falling_edge(write) THEN
|
| 1545 |
|
|
IF A_PAT_1 AND DataByte = 16#10# THEN
|
| 1546 |
|
|
--Start Chip Erase
|
| 1547 |
|
|
ESTART <= '1', '0' AFTER 1 ns;
|
| 1548 |
|
|
ESUSP <= '0';
|
| 1549 |
|
|
ERES <= '0';
|
| 1550 |
|
|
Ers_Queue <= (OTHERS => '1');
|
| 1551 |
|
|
Status := (OTHERS => '0');
|
| 1552 |
|
|
ELSIF DataByte = 16#30# THEN
|
| 1553 |
|
|
--put selected sector to sec. ers. queue
|
| 1554 |
|
|
--start timeout
|
| 1555 |
|
|
Ers_Queue <= (OTHERS => '0');
|
| 1556 |
|
|
Ers_Queue(SecAddr) <= '1';
|
| 1557 |
|
|
CTMOUT_in <= '1';
|
| 1558 |
|
|
END IF;
|
| 1559 |
|
|
END IF;
|
| 1560 |
|
|
|
| 1561 |
|
|
WHEN ERS =>
|
| 1562 |
|
|
IF oe THEN
|
| 1563 |
|
|
-----------------------------------------------------------
|
| 1564 |
|
|
-- read status / embeded erase algorithm - Chip Erase
|
| 1565 |
|
|
-----------------------------------------------------------
|
| 1566 |
|
|
Status(7) := '0';
|
| 1567 |
|
|
Status(6) := NOT Status(6); --toggle
|
| 1568 |
|
|
Status(5) := '0';
|
| 1569 |
|
|
Status(3) := '1';
|
| 1570 |
|
|
Status(2) := NOT Status(2); --toggle
|
| 1571 |
|
|
|
| 1572 |
|
|
DOut_zd <= Status;
|
| 1573 |
|
|
END IF;
|
| 1574 |
|
|
IF EERR /= '1' THEN
|
| 1575 |
|
|
FOR i IN 0 TO SecNum LOOP
|
| 1576 |
|
|
IF Sec_Prot(i) /= '1' THEN
|
| 1577 |
|
|
Mem(i):= (OTHERS => -1);
|
| 1578 |
|
|
END IF;
|
| 1579 |
|
|
END LOOP;
|
| 1580 |
|
|
IF EDONE = '1' THEN
|
| 1581 |
|
|
FOR i IN 0 TO SecNum LOOP
|
| 1582 |
|
|
IF Sec_Prot(i) /= '1' THEN
|
| 1583 |
|
|
Mem(i):= (OTHERS => MaxData);
|
| 1584 |
|
|
END IF;
|
| 1585 |
|
|
END LOOP;
|
| 1586 |
|
|
END IF;
|
| 1587 |
|
|
END IF;
|
| 1588 |
|
|
-- busy signal active
|
| 1589 |
|
|
RY_zd <= '0';
|
| 1590 |
|
|
|
| 1591 |
|
|
WHEN SERS =>
|
| 1592 |
|
|
IF CTMOUT = '1' THEN
|
| 1593 |
|
|
CTMOUT_in <= '0';
|
| 1594 |
|
|
|
| 1595 |
|
|
START_T1_in <= '0';
|
| 1596 |
|
|
ESTART <= '1', '0' AFTER 1 ns;
|
| 1597 |
|
|
ESUSP <= '0';
|
| 1598 |
|
|
ERES <= '0';
|
| 1599 |
|
|
|
| 1600 |
|
|
ELSIF falling_edge(write) THEN
|
| 1601 |
|
|
IF (DataByte = 16#B0#) THEN
|
| 1602 |
|
|
--need to start erase process prior to suspend
|
| 1603 |
|
|
ESTART <= '1', '0' AFTER 1 ns;
|
| 1604 |
|
|
ERES <= '0';
|
| 1605 |
|
|
-- CTMOUT reset
|
| 1606 |
|
|
CTMOUT_in <= '0';
|
| 1607 |
|
|
ESUSP <= '1' AFTER 1 ns, '0' AFTER 2 ns;
|
| 1608 |
|
|
ELSIF (DataByte = 16#30#) THEN
|
| 1609 |
|
|
CTMOUT_in <= '0', '1' AFTER 1 ns;
|
| 1610 |
|
|
Ers_Queue(SecAddr) <= '1';
|
| 1611 |
|
|
ELSE
|
| 1612 |
|
|
CTMOUT_in <= '0';
|
| 1613 |
|
|
END IF;
|
| 1614 |
|
|
ELSIF oe THEN
|
| 1615 |
|
|
-----------------------------------------------------------
|
| 1616 |
|
|
--read status - sector erase timeout
|
| 1617 |
|
|
-----------------------------------------------------------
|
| 1618 |
|
|
Status(3) := '0';
|
| 1619 |
|
|
Status(7) := '1';
|
| 1620 |
|
|
DOut_zd <= Status;
|
| 1621 |
|
|
END IF;
|
| 1622 |
|
|
--ready signal active
|
| 1623 |
|
|
RY_zd <= '0';
|
| 1624 |
|
|
|
| 1625 |
|
|
WHEN ESPS =>
|
| 1626 |
|
|
IF (START_T1 = '1') THEN
|
| 1627 |
|
|
ESP_ACT <= '1';
|
| 1628 |
|
|
START_T1_in <= '0';
|
| 1629 |
|
|
ELSIF oe THEN
|
| 1630 |
|
|
-----------------------------------------------------------
|
| 1631 |
|
|
--read status / erase suspend timeout - stil erasing
|
| 1632 |
|
|
-----------------------------------------------------------
|
| 1633 |
|
|
IF Ers_Queue(SecAddr)='1' THEN
|
| 1634 |
|
|
Status(7) := '0';
|
| 1635 |
|
|
Status(2) := NOT Status(2); --toggle
|
| 1636 |
|
|
ELSE
|
| 1637 |
|
|
Status(7) := '1';
|
| 1638 |
|
|
END IF;
|
| 1639 |
|
|
Status(6) := NOT Status(6); --toggle
|
| 1640 |
|
|
Status(5) := '0';
|
| 1641 |
|
|
Status(3) := '1';
|
| 1642 |
|
|
|
| 1643 |
|
|
DOut_zd <= Status;
|
| 1644 |
|
|
|
| 1645 |
|
|
END IF;
|
| 1646 |
|
|
--busy signal active
|
| 1647 |
|
|
RY_zd <= '0';
|
| 1648 |
|
|
|
| 1649 |
|
|
WHEN SERS_EXEC =>
|
| 1650 |
|
|
IF oe THEN
|
| 1651 |
|
|
-----------------------------------------------------------
|
| 1652 |
|
|
--read status Erase Busy
|
| 1653 |
|
|
-----------------------------------------------------------
|
| 1654 |
|
|
IF Ers_Queue(SecAddr) = '1' THEN
|
| 1655 |
|
|
Status(7) := '0';
|
| 1656 |
|
|
Status(2) := NOT Status(2); --toggle
|
| 1657 |
|
|
ELSE
|
| 1658 |
|
|
Status(7) := '1';
|
| 1659 |
|
|
END IF;
|
| 1660 |
|
|
Status(6) := NOT Status(6); --toggle
|
| 1661 |
|
|
Status(5) := '0';
|
| 1662 |
|
|
Status(3) := '1';
|
| 1663 |
|
|
|
| 1664 |
|
|
DOut_zd <= Status;
|
| 1665 |
|
|
END IF;
|
| 1666 |
|
|
IF EERR /= '1' THEN
|
| 1667 |
|
|
FOR i IN Ers_Queue'RANGE LOOP
|
| 1668 |
|
|
IF Ers_Queue(i) = '1' AND Sec_Prot(i) /= '1' THEN
|
| 1669 |
|
|
Mem(i) := (OTHERS => -1);
|
| 1670 |
|
|
END IF;
|
| 1671 |
|
|
END LOOP;
|
| 1672 |
|
|
IF EDONE = '1' THEN
|
| 1673 |
|
|
FOR i IN Ers_Queue'RANGE LOOP
|
| 1674 |
|
|
IF Ers_Queue(i) = '1' AND Sec_Prot(i) /= '1' THEN
|
| 1675 |
|
|
Mem(i) := (OTHERS => MaxData);
|
| 1676 |
|
|
END IF;
|
| 1677 |
|
|
END LOOP;
|
| 1678 |
|
|
ELSIF falling_edge(write) THEN
|
| 1679 |
|
|
IF DataByte = 16#B0# THEN
|
| 1680 |
|
|
START_T1_in <= '1';
|
| 1681 |
|
|
ESUSP <= '1', '0' AFTER 1 ns;
|
| 1682 |
|
|
END IF;
|
| 1683 |
|
|
END IF;
|
| 1684 |
|
|
END IF;
|
| 1685 |
|
|
--busy signal active
|
| 1686 |
|
|
RY_zd <= '0';
|
| 1687 |
|
|
|
| 1688 |
|
|
WHEN ESP =>
|
| 1689 |
|
|
IF falling_edge(write) THEN
|
| 1690 |
|
|
IF A_PAT_2 AND PATTERN_1 THEN
|
| 1691 |
|
|
AS_SecSi_FP := '1';
|
| 1692 |
|
|
ELSE
|
| 1693 |
|
|
AS_SecSi_FP := '0';
|
| 1694 |
|
|
END IF;
|
| 1695 |
|
|
IF DataByte = 16#30# THEN
|
| 1696 |
|
|
--resume erase
|
| 1697 |
|
|
ERES <= '1', '0' AFTER 1 ns;
|
| 1698 |
|
|
END IF;
|
| 1699 |
|
|
ELSIF oe THEN
|
| 1700 |
|
|
IF Ers_Queue(SecAddr) = '1' AND Sec_Prot(SecAddr) /= '1'THEN
|
| 1701 |
|
|
-------------------------------------------------------
|
| 1702 |
|
|
--read status
|
| 1703 |
|
|
-------------------------------------------------------
|
| 1704 |
|
|
Status(7) := '1';
|
| 1705 |
|
|
-- Status(6) No toggle
|
| 1706 |
|
|
Status(5) := '0';
|
| 1707 |
|
|
Status(2) := NOT Status(2); --toggle
|
| 1708 |
|
|
DOut_zd <= Status;
|
| 1709 |
|
|
ELSE
|
| 1710 |
|
|
-------------------------------------------------------
|
| 1711 |
|
|
--read
|
| 1712 |
|
|
-------------------------------------------------------
|
| 1713 |
|
|
IF Mem(SecAddr)(Address) = -1 THEN
|
| 1714 |
|
|
DOut_zd <= (OTHERS=>'X');
|
| 1715 |
|
|
ELSE
|
| 1716 |
|
|
DOut_zd <= to_slv(Mem(SecAddr)(Address),8);
|
| 1717 |
|
|
END IF;
|
| 1718 |
|
|
END IF;
|
| 1719 |
|
|
END IF;
|
| 1720 |
|
|
--ready signal active
|
| 1721 |
|
|
RY_zd <= '1';
|
| 1722 |
|
|
|
| 1723 |
|
|
WHEN ESP_Z001 =>
|
| 1724 |
|
|
IF falling_edge(write) THEN
|
| 1725 |
|
|
IF A_PAT_3 AND PATTERN_2 THEN
|
| 1726 |
|
|
null;
|
| 1727 |
|
|
ELSE
|
| 1728 |
|
|
AS_SecSi_FP := '0';
|
| 1729 |
|
|
END IF;
|
| 1730 |
|
|
END IF;
|
| 1731 |
|
|
|
| 1732 |
|
|
WHEN ESP_PREL =>
|
| 1733 |
|
|
IF falling_edge(write) THEN
|
| 1734 |
|
|
IF (A_PAT_2 AND DataByte = 16#90#) THEN
|
| 1735 |
|
|
null;
|
| 1736 |
|
|
ELSE
|
| 1737 |
|
|
AS_SecSi_FP := '0';
|
| 1738 |
|
|
END IF;
|
| 1739 |
|
|
IF AS_addr = 0 THEN
|
| 1740 |
|
|
AS_ID := TRUE;
|
| 1741 |
|
|
AS_ID2:= FALSE;
|
| 1742 |
|
|
ELSE
|
| 1743 |
|
|
AS_ID := FALSE;
|
| 1744 |
|
|
AS_ID2:= TRUE;
|
| 1745 |
|
|
END IF;
|
| 1746 |
|
|
END IF;
|
| 1747 |
|
|
null;
|
| 1748 |
|
|
|
| 1749 |
|
|
WHEN AS | ESP_AS | OTP_AS =>
|
| 1750 |
|
|
IF falling_edge(write) THEN
|
| 1751 |
|
|
IF (DataByte = 16#00#) THEN
|
| 1752 |
|
|
OTP_ACT <= '0';
|
| 1753 |
|
|
IF ESP_ACT = '1' THEN
|
| 1754 |
|
|
ULBYPASS <= '0';
|
| 1755 |
|
|
END IF;
|
| 1756 |
|
|
ELSIF (DataByte = 16#F0#) THEN
|
| 1757 |
|
|
AS_ID := FALSE;
|
| 1758 |
|
|
AS_ID2 := FALSE;
|
| 1759 |
|
|
AS_SecSi_FP := '0';
|
| 1760 |
|
|
END IF;
|
| 1761 |
|
|
ELSIF oe THEN
|
| 1762 |
|
|
IF AS_addr = 0 THEN
|
| 1763 |
|
|
null;
|
| 1764 |
|
|
ELSE
|
| 1765 |
|
|
AS_ID := FALSE;
|
| 1766 |
|
|
END IF;
|
| 1767 |
|
|
IF ((Addr = 0) AND AS_ID ) THEN
|
| 1768 |
|
|
DOut_zd <= to_slv(1,8);
|
| 1769 |
|
|
ELSIF ((Addr = 1) AND AS_ID ) THEN
|
| 1770 |
|
|
DOut_zd <= to_slv(16#A3#,8);
|
| 1771 |
|
|
ELSIF (Addr = 2) AND (((SecAddr < 32) AND AS_ID)
|
| 1772 |
|
|
OR ((SecAddr > 31) AND AS_ID2)) THEN
|
| 1773 |
|
|
DOut_zd <= (OTHERS => '0');
|
| 1774 |
|
|
DOut_zd(0) <= Sec_Prot(SecAddr);
|
| 1775 |
|
|
ELSIF (Addr = 6 AND AS_SecSi_FP = '1') THEN
|
| 1776 |
|
|
IF FactoryProt = '1' THEN
|
| 1777 |
|
|
DOut_zd <= to_slv(16#99#,8);
|
| 1778 |
|
|
ELSE
|
| 1779 |
|
|
DOut_zd <= to_slv(16#19#,8);
|
| 1780 |
|
|
END IF;
|
| 1781 |
|
|
ELSE
|
| 1782 |
|
|
Dout_zd <= "ZZZZZZZZ";
|
| 1783 |
|
|
END IF;
|
| 1784 |
|
|
END IF;
|
| 1785 |
|
|
|
| 1786 |
|
|
WHEN PGMS =>
|
| 1787 |
|
|
IF oe THEN
|
| 1788 |
|
|
-----------------------------------------------------------
|
| 1789 |
|
|
--read status
|
| 1790 |
|
|
-----------------------------------------------------------
|
| 1791 |
|
|
Status(6) := NOT Status(6); --toggle
|
| 1792 |
|
|
Status(5) := '0';
|
| 1793 |
|
|
--Status(2) no toggle
|
| 1794 |
|
|
Status(1) := '0';
|
| 1795 |
|
|
DOut_zd <= Status;
|
| 1796 |
|
|
IF (SecAddr = SA) OR OTP_ACT = '1' THEN
|
| 1797 |
|
|
DOut_zd(7) <= Status(7);
|
| 1798 |
|
|
ELSE
|
| 1799 |
|
|
DOut_zd(7) <= NOT Status(7);
|
| 1800 |
|
|
END IF;
|
| 1801 |
|
|
|
| 1802 |
|
|
END IF;
|
| 1803 |
|
|
IF PERR /= '1' THEN
|
| 1804 |
|
|
new_int := WData;
|
| 1805 |
|
|
IF OTP_ACT /= '1' THEN
|
| 1806 |
|
|
old_int := Mem(SA)(WAddr);
|
| 1807 |
|
|
ELSE
|
| 1808 |
|
|
old_int := SecSi(Waddr);
|
| 1809 |
|
|
END IF;
|
| 1810 |
|
|
IF new_int>-1 THEN
|
| 1811 |
|
|
new_bit:=to_slv(new_int,8);
|
| 1812 |
|
|
IF old_int>-1 THEN
|
| 1813 |
|
|
old_bit:=to_slv(old_int,8);
|
| 1814 |
|
|
FOR j IN 0 TO 7 LOOP
|
| 1815 |
|
|
IF old_bit(j) = '0' THEN
|
| 1816 |
|
|
new_bit(j) := '0';
|
| 1817 |
|
|
END IF;
|
| 1818 |
|
|
END LOOP;
|
| 1819 |
|
|
new_int:=to_nat(new_bit);
|
| 1820 |
|
|
END IF;
|
| 1821 |
|
|
WData:= new_int;
|
| 1822 |
|
|
ELSE
|
| 1823 |
|
|
WData:= -1;
|
| 1824 |
|
|
END IF;
|
| 1825 |
|
|
IF OTP_ACT /= '1' THEN
|
| 1826 |
|
|
Mem(SA)(WAddr) := -1;
|
| 1827 |
|
|
ELSE
|
| 1828 |
|
|
SecSi(Waddr) := -1;
|
| 1829 |
|
|
END IF;
|
| 1830 |
|
|
IF HANG /= '1' AND PDONE='1' AND (NOT PERR'EVENT) THEN
|
| 1831 |
|
|
IF OTP_ACT /= '1' THEN
|
| 1832 |
|
|
Mem(SA)(WAddr) := WData;
|
| 1833 |
|
|
ELSE
|
| 1834 |
|
|
SecSi(Waddr) := Wdata;
|
| 1835 |
|
|
END IF;
|
| 1836 |
|
|
WData:= -1;
|
| 1837 |
|
|
END IF;
|
| 1838 |
|
|
END IF;
|
| 1839 |
|
|
--busy signal active
|
| 1840 |
|
|
RY_zd <= '0';
|
| 1841 |
|
|
END CASE;
|
| 1842 |
|
|
END IF;
|
| 1843 |
|
|
|
| 1844 |
|
|
--Output Disable Control
|
| 1845 |
|
|
IF (gOE_n = '1') OR (gCE_n = '1') OR (RESETNeg = '0' AND RST = '0') THEN
|
| 1846 |
|
|
DOut_zd <= (OTHERS=>'Z');
|
| 1847 |
|
|
END IF;
|
| 1848 |
|
|
|
| 1849 |
|
|
IF NOW = 0 ns THEN
|
| 1850 |
|
|
--CFI query identification string
|
| 1851 |
|
|
CFI_array(16#10#) := 16#51#;
|
| 1852 |
|
|
CFI_array(16#11#) := 16#52#;
|
| 1853 |
|
|
CFI_array(16#12#) := 16#59#;
|
| 1854 |
|
|
CFI_array(16#13#) := 16#02#;
|
| 1855 |
|
|
CFI_array(16#14#) := 16#00#;
|
| 1856 |
|
|
CFI_array(16#15#) := 16#40#;
|
| 1857 |
|
|
CFI_array(16#16#) := 16#00#;
|
| 1858 |
|
|
CFI_array(16#17#) := 16#00#;
|
| 1859 |
|
|
CFI_array(16#18#) := 16#00#;
|
| 1860 |
|
|
CFI_array(16#19#) := 16#00#;
|
| 1861 |
|
|
CFI_array(16#1A#) := 16#00#;
|
| 1862 |
|
|
--system interface string
|
| 1863 |
|
|
CFI_array(16#1B#) := 16#27#;
|
| 1864 |
|
|
CFI_array(16#1C#) := 16#36#;
|
| 1865 |
|
|
CFI_array(16#1D#) := 16#00#;
|
| 1866 |
|
|
CFI_array(16#1E#) := 16#00#;
|
| 1867 |
|
|
CFI_array(16#1F#) := 16#04#;
|
| 1868 |
|
|
CFI_array(16#20#) := 16#00#;
|
| 1869 |
|
|
CFI_array(16#21#) := 16#0A#;
|
| 1870 |
|
|
CFI_array(16#22#) := 16#00#;
|
| 1871 |
|
|
CFI_array(16#23#) := 16#05#;
|
| 1872 |
|
|
CFI_array(16#24#) := 16#00#;
|
| 1873 |
|
|
CFI_array(16#25#) := 16#04#;
|
| 1874 |
|
|
CFI_array(16#26#) := 16#00#;
|
| 1875 |
|
|
--device geometry definition
|
| 1876 |
|
|
CFI_array(16#27#) := 16#16#;
|
| 1877 |
|
|
CFI_array(16#28#) := 16#00#;
|
| 1878 |
|
|
CFI_array(16#29#) := 16#00#;
|
| 1879 |
|
|
CFI_array(16#2A#) := 16#00#;
|
| 1880 |
|
|
CFI_array(16#2B#) := 16#00#;
|
| 1881 |
|
|
CFI_array(16#2C#) := 16#01#;
|
| 1882 |
|
|
CFI_array(16#2D#) := 16#3F#;
|
| 1883 |
|
|
CFI_array(16#2E#) := 16#00#;
|
| 1884 |
|
|
CFI_array(16#2F#) := 16#20#;
|
| 1885 |
|
|
CFI_array(16#30#) := 16#01#;
|
| 1886 |
|
|
CFI_array(16#31#) := 16#00#;
|
| 1887 |
|
|
CFI_array(16#32#) := 16#00#;
|
| 1888 |
|
|
CFI_array(16#33#) := 16#00#;
|
| 1889 |
|
|
CFI_array(16#34#) := 16#00#;
|
| 1890 |
|
|
CFI_array(16#35#) := 16#00#;
|
| 1891 |
|
|
CFI_array(16#36#) := 16#00#;
|
| 1892 |
|
|
CFI_array(16#37#) := 16#00#;
|
| 1893 |
|
|
CFI_array(16#38#) := 16#00#;
|
| 1894 |
|
|
CFI_array(16#39#) := 16#00#;
|
| 1895 |
|
|
CFI_array(16#3A#) := 16#00#;
|
| 1896 |
|
|
CFI_array(16#3B#) := 16#00#;
|
| 1897 |
|
|
CFI_array(16#3C#) := 16#00#;
|
| 1898 |
|
|
|
| 1899 |
|
|
--primary vendor-specific extended query
|
| 1900 |
|
|
CFI_array(16#40#) := 16#50#;
|
| 1901 |
|
|
CFI_array(16#41#) := 16#52#;
|
| 1902 |
|
|
CFI_array(16#42#) := 16#49#;
|
| 1903 |
|
|
CFI_array(16#43#) := 16#31#;
|
| 1904 |
|
|
CFI_array(16#44#) := 16#31#;
|
| 1905 |
|
|
CFI_array(16#45#) := 16#01#;
|
| 1906 |
|
|
CFI_array(16#46#) := 16#02#;
|
| 1907 |
|
|
CFI_array(16#47#) := 16#01#;
|
| 1908 |
|
|
CFI_array(16#48#) := 16#01#;
|
| 1909 |
|
|
CFI_array(16#49#) := 16#04#;
|
| 1910 |
|
|
CFI_array(16#4A#) := 16#00#;
|
| 1911 |
|
|
CFI_array(16#4B#) := 16#00#;
|
| 1912 |
|
|
CFI_array(16#4C#) := 16#00#;
|
| 1913 |
|
|
CFI_array(16#4D#) := 16#B5#;
|
| 1914 |
|
|
CFI_array(16#4E#) := 16#C5#;
|
| 1915 |
|
|
CFI_array(16#4F#) := 16#00#;
|
| 1916 |
|
|
END IF;
|
| 1917 |
|
|
|
| 1918 |
|
|
END PROCESS Functional;
|
| 1919 |
|
|
|
| 1920 |
|
|
---------------------------------------------------------------------------
|
| 1921 |
|
|
---- File Read Section - Preload Control
|
| 1922 |
|
|
---------------------------------------------------------------------------
|
| 1923 |
|
|
MemPreload : PROCESS
|
| 1924 |
|
|
|
| 1925 |
|
|
-- text file input variables
|
| 1926 |
|
|
FILE mem_file : text is mem_file_name;
|
| 1927 |
|
|
FILE prot_file : text is prot_file_name;
|
| 1928 |
|
|
FILE secsi_file : text is secsi_file_name;
|
| 1929 |
|
|
|
| 1930 |
|
|
VARIABLE ind : NATURAL RANGE 0 TO SecSize:= 0;
|
| 1931 |
|
|
VARIABLE buf : line;
|
| 1932 |
|
|
|
| 1933 |
|
|
CONSTANT SecS : NATURAL := 16#10000#;
|
| 1934 |
|
|
CONSTANT MemSize : NATURAL := 16#3FFFFF#;
|
| 1935 |
|
|
|
| 1936 |
|
|
VARIABLE addr_ind : NATURAL;
|
| 1937 |
|
|
VARIABLE sec_ind : NATURAL;
|
| 1938 |
|
|
VARIABLE offset : NATURAL;
|
| 1939 |
|
|
variable temp_vector : std_logic_vector(3 downto 0);
|
| 1940 |
|
|
|
| 1941 |
|
|
BEGIN
|
| 1942 |
|
|
IF ( mem_file_name /= "none" AND UserPreload ) THEN
|
| 1943 |
|
|
-------------------------------------------------------------------
|
| 1944 |
|
|
-----s29al032d_00 memory preload file format ----------------------
|
| 1945 |
|
|
-------------------------------------------------------------------
|
| 1946 |
|
|
-- / - comment
|
| 1947 |
|
|
-- @aaaaaa - <aaaaaa> stands for address within Memory
|
| 1948 |
|
|
-- dd - <dd> is byte to be written at Mem(aaaaaa++)
|
| 1949 |
|
|
-- (aaaaaa is incremented at every load)
|
| 1950 |
|
|
-- only first 1-7 columns are loaded. NO empty lines !!!!!!!!!!!!
|
| 1951 |
|
|
-------------------------------------------------------------------
|
| 1952 |
|
|
addr_ind := 0;
|
| 1953 |
|
|
Mem := (OTHERS => (OTHERS => MaxData));
|
| 1954 |
|
|
|
| 1955 |
|
|
WHILE (not ENDFILE (mem_file)) LOOP
|
| 1956 |
|
|
READLINE (mem_file, buf);
|
| 1957 |
|
|
IF buf(1) = '/' THEN --comment
|
| 1958 |
|
|
NEXT;
|
| 1959 |
|
|
ELSIF buf(1) = '@' THEN --address
|
| 1960 |
|
|
addr_ind := h(buf(2 to 7));
|
| 1961 |
|
|
sec_ind := addr_ind / SecS;
|
| 1962 |
|
|
offset := addr_ind - ( sec_ind * SecS );
|
| 1963 |
|
|
ELSE
|
| 1964 |
|
|
IF addr_ind <= MemSize THEN
|
| 1965 |
|
|
Mem(sec_ind)(offset) := h(buf(1 to 2));
|
| 1966 |
|
|
addr_ind := (addr_ind + 1);
|
| 1967 |
|
|
sec_ind := addr_ind / SecS;
|
| 1968 |
|
|
offset := addr_ind - ( sec_ind * SecS );
|
| 1969 |
|
|
ELSE
|
| 1970 |
|
|
ASSERT FALSE
|
| 1971 |
|
|
REPORT " Memory address out of range"
|
| 1972 |
|
|
SEVERITY warning;
|
| 1973 |
|
|
END IF;
|
| 1974 |
|
|
END IF;
|
| 1975 |
|
|
END LOOP;
|
| 1976 |
|
|
END IF;
|
| 1977 |
|
|
|
| 1978 |
|
|
IF (prot_file_name /= "none" AND UserPreload ) THEN
|
| 1979 |
|
|
-------------------------------------------------------------------
|
| 1980 |
|
|
-----s29al032d_00 sector protect preload file format --------------
|
| 1981 |
|
|
-------------------------------------------------------------------
|
| 1982 |
|
|
-- / - comment
|
| 1983 |
|
|
-- @ss - <ss> stands for sector number
|
| 1984 |
|
|
-- d - <d> is bit to be written at SecProt(ss++)
|
| 1985 |
|
|
-- (sec is incremented at every load)
|
| 1986 |
|
|
-- only first 1-3 columns are loaded. NO empty lines !!!!!!!!!!!!
|
| 1987 |
|
|
-------------------------------------------------------------------
|
| 1988 |
|
|
-------------------------------------------------------------------
|
| 1989 |
|
|
ind := 0;
|
| 1990 |
|
|
Sec_Prot := (OTHERS => '0');
|
| 1991 |
|
|
|
| 1992 |
|
|
WHILE (not ENDFILE (prot_file)) LOOP
|
| 1993 |
|
|
-- Always load as top, convert if bottom
|
| 1994 |
|
|
READLINE (prot_file, buf);
|
| 1995 |
|
|
IF buf(1)='/' THEN --comment
|
| 1996 |
|
|
NEXT;
|
| 1997 |
|
|
ELSIF buf(1) = '@' THEN --address
|
| 1998 |
|
|
ind := h(buf(2 to 3));
|
| 1999 |
|
|
ELSE
|
| 2000 |
|
|
IF (buf(1) = '1') AND (ind <= SecNum) THEN
|
| 2001 |
|
|
Sec_Prot(ind) := '1';
|
| 2002 |
|
|
ELSE
|
| 2003 |
|
|
IF ind > SecNum THEN
|
| 2004 |
|
|
IF (buf(1) = '1') THEN
|
| 2005 |
|
|
FactoryProt <= '1';
|
| 2006 |
|
|
END IF;
|
| 2007 |
|
|
END IF;
|
| 2008 |
|
|
END IF;
|
| 2009 |
|
|
ind := ind + 1;
|
| 2010 |
|
|
END IF;
|
| 2011 |
|
|
END LOOP;
|
| 2012 |
|
|
FOR i IN 0 TO 15 LOOP
|
| 2013 |
|
|
IF Sec_Prot(4*i+3 DOWNTO 4*i) /= "0000" AND
|
| 2014 |
|
|
Sec_Prot(4*i+3 DOWNTO 4*i) /= "1111"
|
| 2015 |
|
|
THEN
|
| 2016 |
|
|
-- every 4-group sectors protect bit must equal
|
| 2017 |
|
|
REPORT "Bad preload " & to_int_str(i) &
|
| 2018 |
|
|
"th sector protect group"
|
| 2019 |
|
|
SEVERITY warning;
|
| 2020 |
|
|
END IF;
|
| 2021 |
|
|
END LOOP;
|
| 2022 |
|
|
END IF;
|
| 2023 |
|
|
|
| 2024 |
|
|
-- Secure Silicon Sector Region preload
|
| 2025 |
|
|
IF (SecSi_file_name /= "none" AND UserPreload ) THEN
|
| 2026 |
|
|
-------------------------------------------------------------------
|
| 2027 |
|
|
-----s29al032d_00 SecSi preload file format------------------------
|
| 2028 |
|
|
-------------------------------------------------------------------
|
| 2029 |
|
|
-- / - comment
|
| 2030 |
|
|
-- @aaaa - <aaaa> stands for address within sector
|
| 2031 |
|
|
-- dd - <dd> is byte to be written at SecSi(aaaa++)
|
| 2032 |
|
|
-- (aaaa is incremented at every load)
|
| 2033 |
|
|
-- only first 1-5 columns are loaded. NO empty lines !!!!!!!!!!!!
|
| 2034 |
|
|
--------------------------------------------------------------------
|
| 2035 |
|
|
SecSi := (OTHERS => MaxData);
|
| 2036 |
|
|
ind := 0;
|
| 2037 |
|
|
WHILE (not ENDFILE (SecSi_file)) LOOP
|
| 2038 |
|
|
READLINE (SecSi_file, buf);
|
| 2039 |
|
|
IF buf(1) = '/' THEN
|
| 2040 |
|
|
NEXT;
|
| 2041 |
|
|
ELSIF buf(1) = '@' THEN
|
| 2042 |
|
|
ind := h(buf(2 TO 3));
|
| 2043 |
|
|
ELSE
|
| 2044 |
|
|
IF ind <= SecSiSize THEN
|
| 2045 |
|
|
SecSi(ind) := h(buf(1 TO 2));
|
| 2046 |
|
|
ind := ind + 1;
|
| 2047 |
|
|
END IF;
|
| 2048 |
|
|
END IF;
|
| 2049 |
|
|
END LOOP;
|
| 2050 |
|
|
END IF;
|
| 2051 |
|
|
WAIT ;
|
| 2052 |
|
|
END PROCESS MemPreload;
|
| 2053 |
|
|
|
| 2054 |
|
|
DOutPassThrough : PROCESS(DOut_zd)
|
| 2055 |
|
|
VARIABLE ValidData : std_logic_vector(7 downto 0);
|
| 2056 |
|
|
VARIABLE CEDQ_t : TIME;
|
| 2057 |
|
|
VARIABLE OEDQ_t : TIME;
|
| 2058 |
|
|
VARIABLE ADDRDQ_t : TIME;
|
| 2059 |
|
|
|
| 2060 |
|
|
BEGIN
|
| 2061 |
|
|
IF DOut_zd(0) /= 'Z' THEN
|
| 2062 |
|
|
OPENLATCH := TRUE;
|
| 2063 |
|
|
CEDQ_t := -CENeg'LAST_EVENT + tpd_CENeg_DQ0(trz0);
|
| 2064 |
|
|
OEDQ_t := -OENeg'LAST_EVENT + tpd_OENeg_DQ0(trz0);
|
| 2065 |
|
|
ADDRDQ_t := -A'LAST_EVENT + tpd_A0_DQ0(tr01);
|
| 2066 |
|
|
FROMOE := (OEDQ_t >= CEDQ_t) AND (OEDQ_t > 0 ns);
|
| 2067 |
|
|
FROMCE := (CEDQ_t > OEDQ_t) AND (CEDQ_t > 0 ns);
|
| 2068 |
|
|
ValidData := "XXXXXXXX";
|
| 2069 |
|
|
IF ((ADDRDQ_t > 0 ns) AND
|
| 2070 |
|
|
(((ADDRDQ_t > CEDQ_t) AND FROMCE) OR
|
| 2071 |
|
|
((ADDRDQ_t > OEDQ_t) AND FROMOE))) THEN
|
| 2072 |
|
|
DOut_Pass <= ValidData,
|
| 2073 |
|
|
DOut_zd AFTER ADDRDQ_t;
|
| 2074 |
|
|
ELSE
|
| 2075 |
|
|
DOut_Pass <= DOut_zd;
|
| 2076 |
|
|
END IF;
|
| 2077 |
|
|
ELSE
|
| 2078 |
|
|
CEDQ_t := -CENeg'LAST_EVENT + tpd_CENeg_DQ0(tr0z);
|
| 2079 |
|
|
OEDQ_t := -OENeg'LAST_EVENT + tpd_OENeg_DQ0(tr0z);
|
| 2080 |
|
|
FROMOE := (OEDQ_t <= CEDQ_t) AND (OEDQ_t > 0 ns);
|
| 2081 |
|
|
FROMCE := (CEDQ_t < OEDQ_t) AND (CEDQ_t > 0 ns);
|
| 2082 |
|
|
DOut_Pass <= DOut_zd;
|
| 2083 |
|
|
OPENLATCH := FALSE;
|
| 2084 |
|
|
END IF;
|
| 2085 |
|
|
END PROCESS DOutPassThrough;
|
| 2086 |
|
|
|
| 2087 |
|
|
-----------------------------------------------------------------------
|
| 2088 |
|
|
-- Path Delay Section
|
| 2089 |
|
|
-----------------------------------------------------------------------
|
| 2090 |
|
|
RY_OUT: PROCESS(RY_zd)
|
| 2091 |
|
|
|
| 2092 |
|
|
VARIABLE RY_GlitchData : VitalGlitchDataType;
|
| 2093 |
|
|
VARIABLE RYData : std_logic;
|
| 2094 |
|
|
BEGIN
|
| 2095 |
|
|
IF RY_zd = '1' THEN
|
| 2096 |
|
|
RYData := 'Z';
|
| 2097 |
|
|
ELSE
|
| 2098 |
|
|
RYData := RY_zd;
|
| 2099 |
|
|
END IF;
|
| 2100 |
|
|
VitalPathDelay01Z(
|
| 2101 |
|
|
OutSignal => RY,
|
| 2102 |
|
|
OutSignalName => "RY/BY#",
|
| 2103 |
|
|
OutTemp => RYData,
|
| 2104 |
|
|
Mode => VitalTransport,
|
| 2105 |
|
|
GlitchData => RY_GlitchData,
|
| 2106 |
|
|
Paths => (
|
| 2107 |
|
|
|
| 2108 |
|
|
PathDelay => tpd_WENeg_RY,
|
| 2109 |
|
|
PathCondition => TRUE),
|
| 2110 |
|
|
1 => (InputChangeTime => WENeg'LAST_EVENT,
|
| 2111 |
|
|
PathDelay => tpd_WENeg_RY,
|
| 2112 |
|
|
PathCondition => TRUE),
|
| 2113 |
|
|
2 => (InputChangeTime => READY'LAST_EVENT,
|
| 2114 |
|
|
PathDelay => VitalZeroDelay01Z,
|
| 2115 |
|
|
PathCondition => EDONE = '1'),
|
| 2116 |
|
|
3 => (InputChangeTime => EDONE'LAST_EVENT,
|
| 2117 |
|
|
PathDelay => VitalZeroDelay01Z,
|
| 2118 |
|
|
PathCondition => EDONE = '1'),
|
| 2119 |
|
|
4 => (InputChangeTime => PDONE'LAST_EVENT,
|
| 2120 |
|
|
PathDelay => VitalZeroDelay01Z,
|
| 2121 |
|
|
PathCondition => PDONE = '1')
|
| 2122 |
|
|
)
|
| 2123 |
|
|
);
|
| 2124 |
|
|
END PROCESS RY_Out;
|
| 2125 |
|
|
|
| 2126 |
|
|
---------------------------------------------------------------------------
|
| 2127 |
|
|
-- Path Delay Section for DOut signal
|
| 2128 |
|
|
---------------------------------------------------------------------------
|
| 2129 |
|
|
D_Out_PathDelay_Gen : FOR i IN 0 TO 7 GENERATE
|
| 2130 |
|
|
PROCESS(DOut_Pass(i))
|
| 2131 |
|
|
VARIABLE D0_GlitchData : VitalGlitchDataType;
|
| 2132 |
|
|
|
| 2133 |
|
|
BEGIN
|
| 2134 |
|
|
VitalPathDelay01Z(
|
| 2135 |
|
|
OutSignal => DOut(i),
|
| 2136 |
|
|
OutSignalName => "DOut",
|
| 2137 |
|
|
OutTemp => DOut_Pass(i),
|
| 2138 |
|
|
GlitchData => D0_GlitchData,
|
| 2139 |
|
|
IgnoreDefaultDelay => TRUE,
|
| 2140 |
|
|
Mode => VitalTransport,
|
| 2141 |
|
|
RejectFastPath => FALSE,
|
| 2142 |
|
|
Paths => (
|
| 2143 |
|
|
|
| 2144 |
|
|
PathDelay => tpd_CENeg_DQ0,
|
| 2145 |
|
|
PathCondition => (NOT OPENLATCH AND NOT FROMOE)
|
| 2146 |
|
|
OR (OPENLATCH AND FROMCE)),
|
| 2147 |
|
|
1 => (InputChangeTime => OENeg'LAST_EVENT,
|
| 2148 |
|
|
PathDelay => tpd_OENeg_DQ0,
|
| 2149 |
|
|
PathCondition => (NOT OPENLATCH AND NOT FROMCE) OR
|
| 2150 |
|
|
(OPENLATCH AND FROMOE)),
|
| 2151 |
|
|
2 => (InputChangeTime => A'LAST_EVENT,
|
| 2152 |
|
|
PathDelay => VitalExtendToFillDelay(tpd_A0_DQ0),
|
| 2153 |
|
|
PathCondition => (NOT FROMOE) AND (NOT FROMCE)),
|
| 2154 |
|
|
3 => (InputChangeTime => RESETNeg'LAST_EVENT,
|
| 2155 |
|
|
PathDelay => tpd_RESETNeg_DQ0,
|
| 2156 |
|
|
PathCondition => RESETNeg='0')
|
| 2157 |
|
|
)
|
| 2158 |
|
|
);
|
| 2159 |
|
|
END PROCESS;
|
| 2160 |
|
|
END GENERATE D_Out_PathDelay_Gen;
|
| 2161 |
|
|
END BLOCK behavior;
|
| 2162 |
|
|
END vhdl_behavioral;
|
