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qaztronic |
// --------------------------------------------------------------------
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//
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// --------------------------------------------------------------------
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`include "timescale.v"
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module tb_dut(
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input tb_clk,
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input tb_rst
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);
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wire [3:0] boot_strap = 4'b0010;
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// --------------------------------------------------------------------
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// de1 wires
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wire [1:0] clock_24;
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wire [1:0] clock_27;
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wire clock_50;
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wire ext_clock;
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wire [3:0] key;
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wire [9:0] sw;
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wire [6:0] hex0;
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wire [6:0] hex1;
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wire [6:0] hex2;
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wire [6:0] hex3;
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wire [7:0] ledg;
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wire [9:0] ledr;
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wire uart_txd;
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wire uart_rxd;
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wire [15:0] dram_dq;
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wire [11:0] dram_addr;
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wire dram_ldqm;
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wire dram_udqm;
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wire dram_we_n;
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wire dram_cas_n;
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wire dram_ras_n;
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wire dram_cs_n;
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wire dram_ba_0;
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wire dram_ba_1;
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wire dram_clk;
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wire dram_cke;
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wire [7:0] fl_dq;
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wire [21:0] fl_addr;
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wire fl_we_n;
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wire fl_rst_n;
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wire fl_oe_n;
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wire fl_ce_n;
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wire [15:0] sram_dq;
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wire [17:0] sram_addr;
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wire sram_ub_n;
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wire sram_lb_n;
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wire sram_we_n;
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wire sram_ce_n;
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wire sram_oe_n;
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wire sd_dat;
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wire sd_dat3;
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wire sd_cmd;
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wire sd_clk;
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wire i2c_sdat;
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wire i2c_sclk;
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wire ps2_dat;
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wire ps2_clk;
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wire tdi;
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wire tck;
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wire tcs;
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wire tdo;
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wire vga_hs;
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wire vga_vs;
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wire [3:0] vga_r;
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wire [3:0] vga_g;
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wire [3:0] vga_b;
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wire aud_adclrck;
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wire aud_adcdat;
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wire aud_daclrck;
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wire aud_dacdat;
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wire aud_bclk;
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wire aud_xck;
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wire [35:0] gpio_0;
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wire [35:0] gpio_1;
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// --------------------------------------------------------------------
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// fpga top
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assign clock_24 = {1'b0, tb_clk};
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assign sw = {6'b000000, boot_strap};
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assign key = {3'b000, ~tb_rst};
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top
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i_top(
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//////////////////////// Clock Input ////////////////////////
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.clock_24( clock_24 ), // 24 MHz
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.clock_27(clock_27), // 27 MHz
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.clock_50(clock_50), // 50 MHz
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.ext_clock(ext_clock), // External Clock
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//////////////////////// Push Button ////////////////////////
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.key( key ), // Pushbutton[3:0]
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//////////////////////// DPDT Switch ////////////////////////
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.sw( sw ), // Toggle Switch[9:0]
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//////////////////////// 7-SEG Dispaly ////////////////////////
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.hex0(hex0), // Seven Segment Digit 0
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.hex1(hex1), // Seven Segment Digit 1
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.hex2(hex2), // Seven Segment Digit 2
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.hex3(hex3), // Seven Segment Digit 3
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//////////////////////////// LED ////////////////////////////
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.ledg(ledg), // LED Green[7:0]
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.ledr(ledr), // LED Red[9:0]
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//////////////////////////// UART ////////////////////////////
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.uart_txd(uart_txd), // UART Transmitter
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.uart_rxd(uart_rxd), // UART Receiver
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/////////////////////// SDRAM Interface ////////////////////////
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.dram_dq(dram_dq), // SDRAM Data bus 16 Bits
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.dram_addr(dram_addr), // SDRAM Address bus 12 Bits
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.dram_ldqm(dram_ldqm), // SDRAM Low-byte Data Mask
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.dram_udqm(dram_udqm), // SDRAM High-byte Data Mask
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.dram_we_n(dram_we_n), // SDRAM Write Enable
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.dram_cas_n(dram_cas_n), // SDRAM Column Address Strobe
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.dram_ras_n(dram_ras_n), // SDRAM Row Address Strobe
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.dram_cs_n(dram_cs_n), // SDRAM Chip Select
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.dram_ba_0(dram_ba_0), // SDRAM Bank Address 0
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.dram_ba_1(dram_ba_1), // SDRAM Bank Address 0
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.dram_clk(dram_clk), // SDRAM Clock
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.dram_cke(dram_cke), // SDRAM Clock Enable
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//////////////////////// Flash Interface ////////////////////////
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.fl_dq(fl_dq), // FLASH Data bus 8 Bits
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.fl_addr(fl_addr), // FLASH Address bus 22 Bits
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.fl_we_n(fl_we_n), // FLASH Write Enable
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.fl_rst_n(fl_rst_n), // FLASH Reset
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.fl_oe_n(fl_oe_n), // FLASH Output Enable
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.fl_ce_n(fl_ce_n), // FLASH Chip Enable
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//////////////////////// SRAM Interface ////////////////////////
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.sram_dq(sram_dq), // SRAM Data bus 16 Bits
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.sram_addr(sram_addr), // SRAM Address bus 18 Bits
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.sram_ub_n(sram_ub_n), // SRAM High-byte Data Mask
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.sram_lb_n(sram_lb_n), // SRAM Low-byte Data Mask
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.sram_we_n(sram_we_n), // SRAM Write Enable
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.sram_ce_n(sram_ce_n), // SRAM Chip Enable
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.sram_oe_n(sram_oe_n), // SRAM Output Enable
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//////////////////// SD Card Interface ////////////////////////
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.sd_dat(sd_dat), // SD Card Data
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.sd_dat3(sd_dat3), // SD Card Data 3
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.sd_cmd(sd_cmd), // SD Card Command Signal
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.sd_clk(sd_clk), // SD Card Clock
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//////////////////////// I2C ////////////////////////////////
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.i2c_sdat(i2c_sdat), // I2C Data
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.i2c_sclk(i2c_sclk), // I2C Clock
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//////////////////////// PS2 ////////////////////////////////
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.ps2_dat(ps2_dat), // PS2 Data
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.ps2_clk(ps2_clk), // PS2 Clock
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//////////////////// USB JTAG link ////////////////////////////
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.tdi(tdi), // CPLD -> FPGA (data in)
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.tck(tck), // CPLD -> FPGA (clk)
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.tcs(tcs), // CPLD -> FPGA (CS)
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.tdo(tdo), // FPGA -> CPLD (data out)
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//////////////////////// VGA ////////////////////////////
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.vga_hs(vga_hs), // VGA H_SYNC
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.vga_vs(vga_vs), // VGA V_SYNC
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.vga_r(vga_r), // VGA Red[3:0]
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.vga_g(vga_g), // VGA Green[3:0]
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.vga_b(vga_b), // VGA Blue[3:0]
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//////////////////// Audio CODEC ////////////////////////////
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.aud_adclrck(aud_adclrck), // Audio CODEC ADC LR Clock
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.aud_adcdat(aud_adcdat), // Audio CODEC ADC Data
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.aud_daclrck(aud_daclrck), // Audio CODEC DAC LR Clock
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.aud_dacdat(aud_dacdat), // Audio CODEC DAC Data
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.aud_bclk(aud_bclk), // Audio CODEC Bit-Stream Clock
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.aud_xck(aud_xck), // Audio CODEC Chip Clock
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//////////////////////// GPIO ////////////////////////////////
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.gpio_0(gpio_0), // GPIO Connection 0
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.gpio_1(gpio_1) // GPIO Connection 1
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);
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// --------------------------------------------------------------------
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// IS61LV25616
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IS61LV25616 i_IS61LV25616 (
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.A(sram_addr),
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.IO(sram_dq),
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.CE_(sram_ce_n),
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.OE_(sram_oe_n),
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.WE_(sram_we_n),
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.LB_(sram_lb_n),
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.UB_(sram_ub_n)
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);
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// --------------------------------------------------------------------
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// s29al032d_00
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s29al032d_00 #( .UserPreload(1'b1), .mem_file_name( "../../../sw/load_this_to_ram/boot_rom_2.txt" ) )
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i_s29al032d_00(
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.A21(fl_addr[21]),
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.A20(fl_addr[20]),
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.A19(fl_addr[19]),
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.A18(fl_addr[18]),
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.A17(fl_addr[17]),
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.A16(fl_addr[16]),
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.A15(fl_addr[15]),
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.A14(fl_addr[14]),
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.A13(fl_addr[13]),
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.A12(fl_addr[12]),
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.A11(fl_addr[11]),
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.A10(fl_addr[10]),
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.A9(fl_addr[9]),
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.A8(fl_addr[8]),
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.A7(fl_addr[7]),
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.A6(fl_addr[6]),
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.A5(fl_addr[5]),
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.A4(fl_addr[4]),
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.A3(fl_addr[3]),
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.A2(fl_addr[2]),
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.A1(fl_addr[1]),
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.A0(fl_addr[0]),
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.DQ7(fl_dq[7]),
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.DQ6(fl_dq[6]),
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.DQ5(fl_dq[5]),
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.DQ4(fl_dq[4]),
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.DQ3(fl_dq[3]),
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.DQ2(fl_dq[2]),
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.DQ1(fl_dq[1]),
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.DQ0(fl_dq[0]),
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.CENeg(fl_ce_n),
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.OENeg(fl_oe_n),
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.WENeg(fl_we_n),
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.RESETNeg(fl_rst_n),
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.ACC(),
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.RY()
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);
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endmodule
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