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1 21 qaztronic 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 
////  OR1200's definitions                                        ////
4 
////                                                              ////
5 
////  This file is part of the OpenRISC 1200 project              ////
6 
////  http://www.opencores.org/cores/or1k/                        ////
7 
////                                                              ////
8 
////  Description                                                 ////
9 
////  Parameters of the OR1200 core                               ////
10 
////                                                              ////
11 
////  To Do:                                                      ////
12 
////   - add parameters that are missing                          ////
13 
////                                                              ////
14 
////  Author(s):                                                  ////
15 
////      - Damjan Lampret, lampret@opencores.org                 ////
16 
////                                                              ////
17 
//////////////////////////////////////////////////////////////////////
18 
////                                                              ////
19 
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20 
////                                                              ////
21 
//// This source file may be used and distributed without         ////
22 
//// restriction provided that this copyright statement is not    ////
23 
//// removed from the file and that any derivative work contains  ////
24 
//// the original copyright notice and the associated disclaimer. ////
25 
////                                                              ////
26 
//// This source file is free software; you can redistribute it   ////
27 
//// and/or modify it under the terms of the GNU Lesser General   ////
28 
//// Public License as published by the Free Software Foundation; ////
29 
//// either version 2.1 of the License, or (at your option) any   ////
30 
//// later version.                                               ////
31 
////                                                              ////
32 
//// This source is distributed in the hope that it will be       ////
33 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36 
//// details.                                                     ////
37 
////                                                              ////
38 
//// You should have received a copy of the GNU Lesser General    ////
39 
//// Public License along with this source; if not, download it   ////
40 
//// from http://www.opencores.org/lgpl.shtml                     ////
41 
////                                                              ////
42 
//////////////////////////////////////////////////////////////////////
43 
//
44 
// CVS Revision History
45 
//
46 
// $Log: or1200_defines.v,v $
47 
// Revision 1.1  2009/03/25 22:16:56  kenagy
48 
// no message
49 
//
50 
// Revision 1.1  2009/02/19 23:49:39  kenagy
51 
// no message
52 
//
53 
// Revision 1.1  2009/02/19 20:11:32  kenagy
54 
// no message
55 
//
56 
// Revision 1.3  2008/08/12 17:03:09  kenagy
57 
// no message
58 
//
59 
// Revision 1.2  2008/07/29 00:53:21  kenagy
60 
// no message
61 
//
62 
// Revision 1.1  2008/06/28 00:57:51  kenagy
63 
// no message
64 
//
65 
// Revision 1.45  2006/04/09 01:32:29  lampret
66 
// See OR1200_MAC_SHIFTBY in or1200_defines.v for explanation of the change. Since now no more 28 bits shift for l.macrc insns however for backward compatbility it is possible to set arbitry number of shifts.
67 
//
68 
// Revision 1.44  2005/10/19 11:37:56  jcastillo
69 
// Added support for RAMB16 Xilinx4/Spartan3 primitives
70 
//
71 
// Revision 1.43  2005/01/07 09:23:39  andreje
72 
// l.ff1 and l.cmov instructions added
73 
//
74 
// Revision 1.42  2004/06/08 18:17:36  lampret
75 
// Non-functional changes. Coding style fixes.
76 
//
77 
// Revision 1.41  2004/05/09 20:03:20  lampret
78 
// By default l.cust5 insns are disabled
79 
//
80 
// Revision 1.40  2004/05/09 19:49:04  lampret
81 
// Added some l.cust5 custom instructions as example
82 
//
83 
// Revision 1.39  2004/04/08 11:00:46  simont
84 
// Add support for 512B instruction cache.
85 
//
86 
// Revision 1.38  2004/04/05 08:29:57  lampret
87 
// Merged branch_qmem into main tree.
88 
//
89 
// Revision 1.35.4.6  2004/02/11 01:40:11  lampret
90 
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
91 
//
92 
// Revision 1.35.4.5  2004/01/15 06:46:38  markom
93 
// interface to debug changed; no more opselect; stb-ack protocol
94 
//
95 
// Revision 1.35.4.4  2004/01/11 22:45:46  andreje
96 
// Separate instruction and data QMEM decoders, QMEM acknowledge and byte-select added
97 
//
98 
// Revision 1.35.4.3  2003/12/17 13:43:38  simons
99 
// Exception prefix configuration changed.
100 
//
101 
// Revision 1.35.4.2  2003/12/05 00:05:03  lampret
102 
// Static exception prefix.
103 
//
104 
// Revision 1.35.4.1  2003/07/08 15:36:37  lampret
105 
// Added embedded memory QMEM.
106 
//
107 
// Revision 1.35  2003/04/24 00:16:07  lampret
108 
// No functional changes. Added defines to disable implementation of multiplier/MAC
109 
//
110 
// Revision 1.34  2003/04/20 22:23:57  lampret
111 
// No functional change. Only added customization for exception vectors.
112 
//
113 
// Revision 1.33  2003/04/07 20:56:07  lampret
114 
// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description.
115 
//
116 
// Revision 1.32  2003/04/07 01:26:57  lampret
117 
// RFRAM defines comments updated. Altera LPM option added.
118 
//
119 
// Revision 1.31  2002/12/08 08:57:56  lampret
120 
// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
121 
//
122 
// Revision 1.30  2002/10/28 15:09:22  mohor
123 
// Previous check-in was done by mistake.
124 
//
125 
// Revision 1.29  2002/10/28 15:03:50  mohor
126 
// Signal scanb_sen renamed to scanb_en.
127 
//
128 
// Revision 1.28  2002/10/17 20:04:40  lampret
129 
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
130 
//
131 
// Revision 1.27  2002/09/16 03:13:23  lampret
132 
// Removed obsolete comment.
133 
//
134 
// Revision 1.26  2002/09/08 05:52:16  lampret
135 
// Added optional l.div/l.divu insns. By default they are disabled.
136 
//
137 
// Revision 1.25  2002/09/07 19:16:10  lampret
138 
// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].
139 
//
140 
// Revision 1.24  2002/09/07 05:42:02  lampret
141 
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
142 
//
143 
// Revision 1.23  2002/09/04 00:50:34  lampret
144 
// Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v.
145 
//
146 
// Revision 1.22  2002/09/03 22:28:21  lampret
147 
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
148 
//
149 
// Revision 1.21  2002/08/22 02:18:55  lampret
150 
// Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.
151 
//
152 
// Revision 1.20  2002/08/18 21:59:45  lampret
153 
// Disable SB until it is tested
154 
//
155 
// Revision 1.19  2002/08/18 19:53:08  lampret
156 
// Added store buffer.
157 
//
158 
// Revision 1.18  2002/08/15 06:04:11  lampret
159 
// Fixed Xilinx trace buffer address. REported by Taylor Su.
160 
//
161 
// Revision 1.17  2002/08/12 05:31:44  lampret
162 
// Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section.
163 
//
164 
// Revision 1.16  2002/07/14 22:17:17  lampret
165 
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
166 
//
167 
// Revision 1.15  2002/06/08 16:20:21  lampret
168 
// Added defines for enabling generic FF based memory macro for register file.
169 
//
170 
// Revision 1.14  2002/03/29 16:24:06  lampret
171 
// Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives
172 
//
173 
// Revision 1.13  2002/03/29 15:16:55  lampret
174 
// Some of the warnings fixed.
175 
//
176 
// Revision 1.12  2002/03/28 19:25:42  lampret
177 
// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.
178 
//
179 
// Revision 1.11  2002/03/28 19:13:17  lampret
180 
// Updated defines.
181 
//
182 
// Revision 1.10  2002/03/14 00:30:24  lampret
183 
// Added alternative for critical path in DU.
184 
//
185 
// Revision 1.9  2002/03/11 01:26:26  lampret
186 
// Fixed async loop. Changed multiplier type for ASIC.
187 
//
188 
// Revision 1.8  2002/02/11 04:33:17  lampret
189 
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
190 
//
191 
// Revision 1.7  2002/02/01 19:56:54  lampret
192 
// Fixed combinational loops.
193 
//
194 
// Revision 1.6  2002/01/19 14:10:22  lampret
195 
// Fixed OR1200_XILINX_RAM32X1D.
196 
//
197 
// Revision 1.5  2002/01/18 07:56:00  lampret
198 
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
199 
//
200 
// Revision 1.4  2002/01/14 09:44:12  lampret
201 
// Default ASIC configuration does not sample WB inputs.
202 
//
203 
// Revision 1.3  2002/01/08 00:51:08  lampret
204 
// Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be.
205 
//
206 
// Revision 1.2  2002/01/03 21:23:03  lampret
207 
// Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target.
208 
//
209 
// Revision 1.1  2002/01/03 08:16:15  lampret
210 
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
211 
//
212 
// Revision 1.20  2001/12/04 05:02:36  lampret
213 
// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32
214 
//
215 
// Revision 1.19  2001/11/27 19:46:57  lampret
216 
// Now FPGA and ASIC target are separate.
217 
//
218 
// Revision 1.18  2001/11/23 21:42:31  simons
219 
// Program counter divided to PPC and NPC.
220 
//
221 
// Revision 1.17  2001/11/23 08:38:51  lampret
222 
// Changed DSR/DRR behavior and exception detection.
223 
//
224 
// Revision 1.16  2001/11/20 21:30:38  lampret
225 
// Added OR1200_REGISTERED_INPUTS.
226 
//
227 
// Revision 1.15  2001/11/19 14:29:48  simons
228 
// Cashes disabled.
229 
//
230 
// Revision 1.14  2001/11/13 10:02:21  lampret
231 
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
232 
//
233 
// Revision 1.13  2001/11/12 01:45:40  lampret
234 
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
235 
//
236 
// Revision 1.12  2001/11/10 03:43:57  lampret
237 
// Fixed exceptions.
238 
//
239 
// Revision 1.11  2001/11/02 18:57:14  lampret
240 
// Modified virtual silicon instantiations.
241 
//
242 
// Revision 1.10  2001/10/21 17:57:16  lampret
243 
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
244 
//
245 
// Revision 1.9  2001/10/19 23:28:46  lampret
246 
// Fixed some synthesis warnings. Configured with caches and MMUs.
247 
//
248 
// Revision 1.8  2001/10/14 13:12:09  lampret
249 
// MP3 version.
250 
//
251 
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
252 
// no message
253 
//
254 
// Revision 1.3  2001/08/17 08:01:19  lampret
255 
// IC enable/disable.
256 
//
257 
// Revision 1.2  2001/08/13 03:36:20  lampret
258 
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
259 
//
260 
// Revision 1.1  2001/08/09 13:39:33  lampret
261 
// Major clean-up.
262 
//
263 
// Revision 1.2  2001/07/22 03:31:54  lampret
264 
// Fixed RAM's oen bug. Cache bypass under development.
265 
//
266 
// Revision 1.1  2001/07/20 00:46:03  lampret
267 
// Development version of RTL. Libraries are missing.
268 
//
269 
//
270 
 
271 
//
272 
// Dump VCD
273 
//
274 
//`define OR1200_VCD_DUMP
275 
 
276 
//
277 
// Generate debug messages during simulation
278 
//
279 
//`define OR1200_VERBOSE
280 
 
281 
//  `define OR1200_ASIC
282 
////////////////////////////////////////////////////////
283 
//
284 
// Typical configuration for an ASIC
285 
//
286 
`ifdef OR1200_ASIC
287 
 
288 
//
289 
// Target ASIC memories
290 
//
291 
//`define OR1200_ARTISAN_SSP
292 
//`define OR1200_ARTISAN_SDP
293 
//`define OR1200_ARTISAN_STP
294 
`define OR1200_VIRTUALSILICON_SSP
295 
//`define OR1200_VIRTUALSILICON_STP_T1
296 
//`define OR1200_VIRTUALSILICON_STP_T2
297 
 
298 
//
299 
// Do not implement Data cache
300 
//
301 
//`define OR1200_NO_DC
302 
 
303 
//
304 
// Do not implement Insn cache
305 
//
306 
//`define OR1200_NO_IC
307 
 
308 
//
309 
// Do not implement Data MMU
310 
//
311 
//`define OR1200_NO_DMMU
312 
 
313 
//
314 
// Do not implement Insn MMU
315 
//
316 
//`define OR1200_NO_IMMU
317 
 
318 
//
319 
// Select between ASIC optimized and generic multiplier
320 
//
321 
//`define OR1200_ASIC_MULTP2_32X32
322 
`define OR1200_GENERIC_MULTP2_32X32
323 
 
324 
//
325 
// Size/type of insn/data cache if implemented
326 
//
327 
// `define OR1200_IC_1W_512B
328 
// `define OR1200_IC_1W_4KB
329 
`define OR1200_IC_1W_8KB
330 
// `define OR1200_DC_1W_4KB
331 
`define OR1200_DC_1W_8KB
332 
 
333 
`else
334 
 
335 
 
336 
/////////////////////////////////////////////////////////
337 
//
338 
// Typical configuration for an FPGA
339 
//
340 
 
341 
//
342 
// Target FPGA memories
343 
//
344 
//`define OR1200_ALTERA_LPM
345 
//`define OR1200_XILINX_RAMB16
346 
//`define OR1200_XILINX_RAMB4
347 
//`define OR1200_XILINX_RAM32X1D
348 
//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
349 
 
350 
//
351 
// Do not implement Data cache
352 
//
353 
`define OR1200_NO_DC
354 
 
355 
//
356 
// Do not implement Insn cache
357 
//
358 
`define OR1200_NO_IC
359 
 
360 
//
361 
// Do not implement Data MMU
362 
//
363 
`define OR1200_NO_DMMU
364 
 
365 
//
366 
// Do not implement Insn MMU
367 
//
368 
`define OR1200_NO_IMMU
369 
 
370 
//
371 
// Select between ASIC and generic multiplier
372 
//
373 
// (Generic seems to trigger a bug in the Cadence Ncsim simulator)
374 
//
375 
//`define OR1200_ASIC_MULTP2_32X32
376 
`define OR1200_GENERIC_MULTP2_32X32
377 
 
378 
//
379 
// Size/type of insn/data cache if implemented
380 
// (consider available FPGA memory resources)
381 
//
382 
//`define OR1200_IC_1W_512B
383 
`define OR1200_IC_1W_4KB
384 
//`define OR1200_IC_1W_8KB
385 
`define OR1200_DC_1W_4KB
386 
//`define OR1200_DC_1W_8KB
387 
 
388 
`endif
389 
 
390 
 
391 
//////////////////////////////////////////////////////////
392 
//
393 
// Do not change below unless you know what you are doing
394 
//
395 
 
396 
//
397 
// Enable RAM BIST
398 
//
399 
// At the moment this only works for Virtual Silicon
400 
// single port RAMs. For other RAMs it has not effect.
401 
// Special wrapper for VS RAMs needs to be provided
402 
// with scan flops to facilitate bist scan.
403 
//
404 
//`define OR1200_BIST
405 
 
406 
//
407 
// Register OR1200 WISHBONE outputs
408 
// (must be defined/enabled)
409 
//
410 
`define OR1200_REGISTERED_OUTPUTS
411 
 
412 
//
413 
// Register OR1200 WISHBONE inputs
414 
//
415 
// (must be undefined/disabled)
416 
//
417 
//`define OR1200_REGISTERED_INPUTS
418 
 
419 
//
420 
// Disable bursts if they are not supported by the
421 
// memory subsystem (only affect cache line fill)
422 
//
423 
//`define OR1200_NO_BURSTS
424 
//
425 
 
426 
//
427 
// WISHBONE retry counter range
428 
//
429 
// 2^value range for retry counter. Retry counter
430 
// is activated whenever *wb_rty_i is asserted and
431 
// until retry counter expires, corresponding
432 
// WISHBONE interface is deactivated.
433 
//
434 
// To disable retry counters and *wb_rty_i all together,
435 
// undefine this macro.
436 
//
437 
//`define OR1200_WB_RETRY 7
438 
 
439 
//
440 
// WISHBONE Consecutive Address Burst
441 
//
442 
// This was used prior to WISHBONE B3 specification
443 
// to identify bursts. It is no longer needed but
444 
// remains enabled for compatibility with old designs.
445 
//
446 
// To remove *wb_cab_o ports undefine this macro.
447 
//
448 
`define OR1200_WB_CAB
449 
 
450 
//
451 
// WISHBONE B3 compatible interface
452 
//
453 
// This follows the WISHBONE B3 specification.
454 
// It is not enabled by default because most
455 
// designs still don't use WB b3.
456 
//
457 
// To enable *wb_cti_o/*wb_bte_o ports,
458 
// define this macro.
459 
//
460 
//`define OR1200_WB_B3
461 
 
462 
//
463 
// Enable additional synthesis directives if using
464 
// _Synopsys_ synthesis tool
465 
//
466 
//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
467 
 
468 
//
469 
// Enables default statement in some case blocks
470 
// and disables Synopsys synthesis directive full_case
471 
//
472 
// By default it is enabled. When disabled it
473 
// can increase clock frequency.
474 
//
475 
`define OR1200_CASE_DEFAULT
476 
 
477 
//
478 
// Operand width / register file address width
479 
//
480 
// (DO NOT CHANGE)
481 
//
482 
`define OR1200_OPERAND_WIDTH            32
483 
`define OR1200_REGFILE_ADDR_WIDTH       5
484 
 
485 
//
486 
// l.add/l.addi/l.and and optional l.addc/l.addic
487 
// also set (compare) flag when result of their
488 
// operation equals zero
489 
//
490 
// At the time of writing this, default or32
491 
// C/C++ compiler doesn't generate code that
492 
// would benefit from this optimization.
493 
//
494 
// By default this optimization is disabled to
495 
// save area.
496 
//
497 
//`define OR1200_ADDITIONAL_FLAG_MODIFIERS
498 
 
499 
//
500 
// Implement l.addc/l.addic instructions
501 
//
502 
// By default implementation of l.addc/l.addic
503 
// instructions is enabled in case you need them.
504 
// If you don't use them, then disable implementation
505 
// to save area.
506 
//
507 
`define OR1200_IMPL_ADDC
508 
 
509 
//
510 
// Implement carry bit SR[CY]
511 
//
512 
// By default implementation of SR[CY] is enabled
513 
// to be compliant with the simulator. However
514 
// SR[CY] is explicitly only used by l.addc/l.addic
515 
// instructions and if these two insns are not
516 
// implemented there is not much point having SR[CY].
517 
//
518 
`define OR1200_IMPL_CY
519 
 
520 
//
521 
// Implement optional l.div/l.divu instructions
522 
//
523 
// By default divide instructions are not implemented
524 
// to save area and increase clock frequency. or32 C/C++
525 
// compiler can use soft library for division.
526 
//
527 
// To implement divide, multiplier needs to be implemented.
528 
//
529 
//`define OR1200_IMPL_DIV
530 
 
531 
//
532 
// Implement rotate in the ALU
533 
//
534 
// At the time of writing this, or32
535 
// C/C++ compiler doesn't generate rotate
536 
// instructions. However or32 assembler
537 
// can assemble code that uses rotate insn.
538 
// This means that rotate instructions
539 
// must be used manually inserted.
540 
//
541 
// By default implementation of rotate
542 
// is disabled to save area and increase
543 
// clock frequency.
544 
//
545 
//`define OR1200_IMPL_ALU_ROTATE
546 
 
547 
//
548 
// Type of ALU compare to implement
549 
//
550 
// Try either one to find what yields
551 
// higher clock frequencyin your case.
552 
//
553 
//`define OR1200_IMPL_ALU_COMP1
554 
`define OR1200_IMPL_ALU_COMP2
555 
 
556 
//
557 
// Implement multiplier
558 
//
559 
// By default multiplier is implemented
560 
//
561 
`define OR1200_MULT_IMPLEMENTED
562 
 
563 
//
564 
// Implement multiply-and-accumulate
565 
//
566 
// By default MAC is implemented. To
567 
// implement MAC, multiplier needs to be
568 
// implemented.
569 
//
570 
`define OR1200_MAC_IMPLEMENTED
571 
 
572 
//
573 
// Low power, slower multiplier
574 
//
575 
// Select between low-power (larger) multiplier
576 
// and faster multiplier. The actual difference
577 
// is only AND logic that prevents distribution
578 
// of operands into the multiplier when instruction
579 
// in execution is not multiply instruction
580 
//
581 
//`define OR1200_LOWPWR_MULT
582 
 
583 
//
584 
// Clock ratio RISC clock versus WB clock
585 
//
586 
// If you plan to run WB:RISC clock fixed to 1:1, disable
587 
// both defines
588 
//
589 
// For WB:RISC 1:2 or 1:1, enable OR1200_CLKDIV_2_SUPPORTED
590 
// and use clmode to set ratio
591 
//
592 
// For WB:RISC 1:4, 1:2 or 1:1, enable both defines and use
593 
// clmode to set ratio
594 
//
595 
// `define OR1200_CLKDIV_2_SUPPORTED    -- qaz
596 
//`define OR1200_CLKDIV_4_SUPPORTED
597 
 
598 
//
599 
// Type of register file RAM
600 
//
601 
// Memory macro w/ two ports (see or1200_tpram_32x32.v)
602 
//`define OR1200_RFRAM_TWOPORT
603 
//
604 
// Memory macro dual port (see or1200_dpram_32x32.v)
605 
//`define OR1200_RFRAM_DUALPORT
606 
//
607 
// Generic (flip-flop based) register file (see or1200_rfram_generic.v)
608 
`define OR1200_RFRAM_GENERIC
609 
 
610 
//
611 
// Type of mem2reg aligner to implement.
612 
//
613 
// Once OR1200_IMPL_MEM2REG2 yielded faster
614 
// circuit, however with today tools it will
615 
// most probably give you slower circuit.
616 
//
617 
`define OR1200_IMPL_MEM2REG1
618 
//`define OR1200_IMPL_MEM2REG2
619 
 
620 
//
621 
// ALUOPs
622 
//
623 
`define OR1200_ALUOP_WIDTH      4
624 
`define OR1200_ALUOP_NOP        4'd4
625 
/* Order defined by arith insns that have two source operands both in regs
626 
   (see binutils/include/opcode/or32.h) */
627 
`define OR1200_ALUOP_ADD        4'd0
628 
`define OR1200_ALUOP_ADDC       4'd1
629 
`define OR1200_ALUOP_SUB        4'd2
630 
`define OR1200_ALUOP_AND        4'd3
631 
`define OR1200_ALUOP_OR         4'd4
632 
`define OR1200_ALUOP_XOR        4'd5
633 
`define OR1200_ALUOP_MUL        4'd6
634 
`define OR1200_ALUOP_CUST5      4'd7
635 
`define OR1200_ALUOP_SHROT      4'd8
636 
`define OR1200_ALUOP_DIV        4'd9
637 
`define OR1200_ALUOP_DIVU       4'd10
638 
/* Order not specifically defined. */
639 
`define OR1200_ALUOP_IMM        4'd11
640 
`define OR1200_ALUOP_MOVHI      4'd12
641 
`define OR1200_ALUOP_COMP       4'd13
642 
`define OR1200_ALUOP_MTSR       4'd14
643 
`define OR1200_ALUOP_MFSR       4'd15
644 
`define OR1200_ALUOP_CMOV 4'd14
645 
`define OR1200_ALUOP_FF1  4'd15
646 
//
647 
// MACOPs
648 
//
649 
`define OR1200_MACOP_WIDTH      2
650 
`define OR1200_MACOP_NOP        2'b00
651 
`define OR1200_MACOP_MAC        2'b01
652 
`define OR1200_MACOP_MSB        2'b10
653 
 
654 
//
655 
// Shift/rotate ops
656 
//
657 
`define OR1200_SHROTOP_WIDTH    2
658 
`define OR1200_SHROTOP_NOP      2'd0
659 
`define OR1200_SHROTOP_SLL      2'd0
660 
`define OR1200_SHROTOP_SRL      2'd1
661 
`define OR1200_SHROTOP_SRA      2'd2
662 
`define OR1200_SHROTOP_ROR      2'd3
663 
 
664 
// Execution cycles per instruction
665 
`define OR1200_MULTICYCLE_WIDTH 2
666 
`define OR1200_ONE_CYCLE                2'd0
667 
`define OR1200_TWO_CYCLES               2'd1
668 
 
669 
// Operand MUX selects
670 
`define OR1200_SEL_WIDTH                2
671 
`define OR1200_SEL_RF                   2'd0
672 
`define OR1200_SEL_IMM                  2'd1
673 
`define OR1200_SEL_EX_FORW              2'd2
674 
`define OR1200_SEL_WB_FORW              2'd3
675 
 
676 
//
677 
// BRANCHOPs
678 
//
679 
`define OR1200_BRANCHOP_WIDTH           3
680 
`define OR1200_BRANCHOP_NOP             3'd0
681 
`define OR1200_BRANCHOP_J               3'd1
682 
`define OR1200_BRANCHOP_JR              3'd2
683 
`define OR1200_BRANCHOP_BAL             3'd3
684 
`define OR1200_BRANCHOP_BF              3'd4
685 
`define OR1200_BRANCHOP_BNF             3'd5
686 
`define OR1200_BRANCHOP_RFE             3'd6
687 
 
688 
//
689 
// LSUOPs
690 
//
691 
// Bit 0: sign extend
692 
// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword
693 
// Bit 3: 0 load, 1 store
694 
`define OR1200_LSUOP_WIDTH              4
695 
`define OR1200_LSUOP_NOP                4'b0000
696 
`define OR1200_LSUOP_LBZ                4'b0010
697 
`define OR1200_LSUOP_LBS                4'b0011
698 
`define OR1200_LSUOP_LHZ                4'b0100
699 
`define OR1200_LSUOP_LHS                4'b0101
700 
`define OR1200_LSUOP_LWZ                4'b0110
701 
`define OR1200_LSUOP_LWS                4'b0111
702 
`define OR1200_LSUOP_LD         4'b0001
703 
`define OR1200_LSUOP_SD         4'b1000
704 
`define OR1200_LSUOP_SB         4'b1010
705 
`define OR1200_LSUOP_SH         4'b1100
706 
`define OR1200_LSUOP_SW         4'b1110
707 
 
708 
// FETCHOPs
709 
`define OR1200_FETCHOP_WIDTH            1
710 
`define OR1200_FETCHOP_NOP              1'b0
711 
`define OR1200_FETCHOP_LW               1'b1
712 
 
713 
//
714 
// Register File Write-Back OPs
715 
//
716 
// Bit 0: register file write enable
717 
// Bits 2-1: write-back mux selects
718 
`define OR1200_RFWBOP_WIDTH             3
719 
`define OR1200_RFWBOP_NOP               3'b000
720 
`define OR1200_RFWBOP_ALU               3'b001
721 
`define OR1200_RFWBOP_LSU               3'b011
722 
`define OR1200_RFWBOP_SPRS              3'b101
723 
`define OR1200_RFWBOP_LR                3'b111
724 
 
725 
// Compare instructions
726 
`define OR1200_COP_SFEQ       3'b000
727 
`define OR1200_COP_SFNE       3'b001
728 
`define OR1200_COP_SFGT       3'b010
729 
`define OR1200_COP_SFGE       3'b011
730 
`define OR1200_COP_SFLT       3'b100
731 
`define OR1200_COP_SFLE       3'b101
732 
`define OR1200_COP_X          3'b111
733 
`define OR1200_SIGNED_COMPARE 'd3
734 
`define OR1200_COMPOP_WIDTH     4
735 
 
736 
//
737 
// TAGs for instruction bus
738 
//
739 
`define OR1200_ITAG_IDLE        4'h0    // idle bus
740 
`define OR1200_ITAG_NI          4'h1    // normal insn
741 
`define OR1200_ITAG_BE          4'hb    // Bus error exception
742 
`define OR1200_ITAG_PE          4'hc    // Page fault exception
743 
`define OR1200_ITAG_TE          4'hd    // TLB miss exception
744 
 
745 
//
746 
// TAGs for data bus
747 
//
748 
`define OR1200_DTAG_IDLE        4'h0    // idle bus
749 
`define OR1200_DTAG_ND          4'h1    // normal data
750 
`define OR1200_DTAG_AE          4'ha    // Alignment exception
751 
`define OR1200_DTAG_BE          4'hb    // Bus error exception
752 
`define OR1200_DTAG_PE          4'hc    // Page fault exception
753 
`define OR1200_DTAG_TE          4'hd    // TLB miss exception
754 
 
755 
 
756 
//////////////////////////////////////////////
757 
//
758 
// ORBIS32 ISA specifics
759 
//
760 
 
761 
// SHROT_OP position in machine word
762 
`define OR1200_SHROTOP_POS              7:6
763 
 
764 
// ALU instructions multicycle field in machine word
765 
`define OR1200_ALUMCYC_POS              9:8
766 
 
767 
//
768 
// Instruction opcode groups (basic)
769 
//
770 
`define OR1200_OR32_J                 6'b000000
771 
`define OR1200_OR32_JAL               6'b000001
772 
`define OR1200_OR32_BNF               6'b000011
773 
`define OR1200_OR32_BF                6'b000100
774 
`define OR1200_OR32_NOP               6'b000101
775 
`define OR1200_OR32_MOVHI             6'b000110
776 
`define OR1200_OR32_XSYNC             6'b001000
777 
`define OR1200_OR32_RFE               6'b001001
778 
/* */
779 
`define OR1200_OR32_JR                6'b010001
780 
`define OR1200_OR32_JALR              6'b010010
781 
`define OR1200_OR32_MACI              6'b010011
782 
/* */
783 
`define OR1200_OR32_LWZ               6'b100001
784 
`define OR1200_OR32_LBZ               6'b100011
785 
`define OR1200_OR32_LBS               6'b100100
786 
`define OR1200_OR32_LHZ               6'b100101
787 
`define OR1200_OR32_LHS               6'b100110
788 
`define OR1200_OR32_ADDI              6'b100111
789 
`define OR1200_OR32_ADDIC             6'b101000
790 
`define OR1200_OR32_ANDI              6'b101001
791 
`define OR1200_OR32_ORI               6'b101010
792 
`define OR1200_OR32_XORI              6'b101011
793 
`define OR1200_OR32_MULI              6'b101100
794 
`define OR1200_OR32_MFSPR             6'b101101
795 
`define OR1200_OR32_SH_ROTI           6'b101110
796 
`define OR1200_OR32_SFXXI             6'b101111
797 
/* */
798 
`define OR1200_OR32_MTSPR             6'b110000
799 
`define OR1200_OR32_MACMSB            6'b110001
800 
/* */
801 
`define OR1200_OR32_SW                6'b110101
802 
`define OR1200_OR32_SB                6'b110110
803 
`define OR1200_OR32_SH                6'b110111
804 
`define OR1200_OR32_ALU               6'b111000
805 
`define OR1200_OR32_SFXX              6'b111001
806 
//`define OR1200_OR32_CUST5             6'b111100
807 
 
808 
 
809 
/////////////////////////////////////////////////////
810 
//
811 
// Exceptions
812 
//
813 
 
814 
//
815 
// Exception vectors per OR1K architecture:
816 
// 0xPPPPP100 - reset
817 
// 0xPPPPP200 - bus error
818 
// ... etc
819 
// where P represents exception prefix.
820 
//
821 
// Exception vectors can be customized as per
822 
// the following formula:
823 
// 0xPPPPPNVV - exception N
824 
//
825 
// P represents exception prefix
826 
// N represents exception N
827 
// VV represents length of the individual vector space,
828 
//   usually it is 8 bits wide and starts with all bits zero
829 
//
830 
 
831 
//
832 
// PPPPP and VV parts
833 
//
834 
// Sum of these two defines needs to be 28
835 
//
836 
`define OR1200_EXCEPT_EPH0_P 20'h00000
837 
`define OR1200_EXCEPT_EPH1_P 20'hF0000
838 
`define OR1200_EXCEPT_V            8'h00
839 
 
840 
//
841 
// N part width
842 
//
843 
`define OR1200_EXCEPT_WIDTH 4
844 
 
845 
//
846 
// Definition of exception vectors
847 
//
848 
// To avoid implementation of a certain exception,
849 
// simply comment out corresponding line
850 
//
851 
`define OR1200_EXCEPT_UNUSED            `OR1200_EXCEPT_WIDTH'hf
852 
`define OR1200_EXCEPT_TRAP              `OR1200_EXCEPT_WIDTH'he
853 
`define OR1200_EXCEPT_BREAK             `OR1200_EXCEPT_WIDTH'hd
854 
`define OR1200_EXCEPT_SYSCALL           `OR1200_EXCEPT_WIDTH'hc
855 
`define OR1200_EXCEPT_RANGE             `OR1200_EXCEPT_WIDTH'hb
856 
`define OR1200_EXCEPT_ITLBMISS          `OR1200_EXCEPT_WIDTH'ha
857 
`define OR1200_EXCEPT_DTLBMISS          `OR1200_EXCEPT_WIDTH'h9
858 
`define OR1200_EXCEPT_INT               `OR1200_EXCEPT_WIDTH'h8
859 
`define OR1200_EXCEPT_ILLEGAL           `OR1200_EXCEPT_WIDTH'h7
860 
`define OR1200_EXCEPT_ALIGN             `OR1200_EXCEPT_WIDTH'h6
861 
`define OR1200_EXCEPT_TICK              `OR1200_EXCEPT_WIDTH'h5
862 
`define OR1200_EXCEPT_IPF               `OR1200_EXCEPT_WIDTH'h4
863 
`define OR1200_EXCEPT_DPF               `OR1200_EXCEPT_WIDTH'h3
864 
`define OR1200_EXCEPT_BUSERR            `OR1200_EXCEPT_WIDTH'h2
865 
`define OR1200_EXCEPT_RESET             `OR1200_EXCEPT_WIDTH'h1
866 
`define OR1200_EXCEPT_NONE              `OR1200_EXCEPT_WIDTH'h0
867 
 
868 
 
869 
/////////////////////////////////////////////////////
870 
//
871 
// SPR groups
872 
//
873 
 
874 
// Bits that define the group
875 
`define OR1200_SPR_GROUP_BITS   15:11
876 
 
877 
// Width of the group bits
878 
`define OR1200_SPR_GROUP_WIDTH  5
879 
 
880 
// Bits that define offset inside the group
881 
`define OR1200_SPR_OFS_BITS 10:0
882 
 
883 
// List of groups
884 
`define OR1200_SPR_GROUP_SYS    5'd00
885 
`define OR1200_SPR_GROUP_DMMU   5'd01
886 
`define OR1200_SPR_GROUP_IMMU   5'd02
887 
`define OR1200_SPR_GROUP_DC     5'd03
888 
`define OR1200_SPR_GROUP_IC     5'd04
889 
`define OR1200_SPR_GROUP_MAC    5'd05
890 
`define OR1200_SPR_GROUP_DU     5'd06
891 
`define OR1200_SPR_GROUP_PM     5'd08
892 
`define OR1200_SPR_GROUP_PIC    5'd09
893 
`define OR1200_SPR_GROUP_TT     5'd10
894 
 
895 
 
896 
/////////////////////////////////////////////////////
897 
//
898 
// System group
899 
//
900 
 
901 
//
902 
// System registers
903 
//
904 
`define OR1200_SPR_CFGR         7'd0
905 
`define OR1200_SPR_RF           6'd32   // 1024 >> 5
906 
`define OR1200_SPR_NPC          11'd16
907 
`define OR1200_SPR_SR           11'd17
908 
`define OR1200_SPR_PPC          11'd18
909 
`define OR1200_SPR_EPCR         11'd32
910 
`define OR1200_SPR_EEAR         11'd48
911 
`define OR1200_SPR_ESR          11'd64
912 
 
913 
//
914 
// SR bits
915 
//
916 
`define OR1200_SR_WIDTH 16
917 
`define OR1200_SR_SM   0
918 
`define OR1200_SR_TEE  1
919 
`define OR1200_SR_IEE  2
920 
`define OR1200_SR_DCE  3
921 
`define OR1200_SR_ICE  4
922 
`define OR1200_SR_DME  5
923 
`define OR1200_SR_IME  6
924 
`define OR1200_SR_LEE  7
925 
`define OR1200_SR_CE   8
926 
`define OR1200_SR_F    9
927 
`define OR1200_SR_CY   10       // Unused
928 
`define OR1200_SR_OV   11       // Unused
929 
`define OR1200_SR_OVE  12       // Unused
930 
`define OR1200_SR_DSX  13       // Unused
931 
`define OR1200_SR_EPH  14
932 
`define OR1200_SR_FO   15
933 
`define OR1200_SR_CID  31:28    // Unimplemented
934 
 
935 
//
936 
// Bits that define offset inside the group
937 
//
938 
`define OR1200_SPROFS_BITS 10:0
939 
 
940 
//
941 
// Default Exception Prefix
942 
//
943 
// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)
944 
// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)
945 
//
946 
`define OR1200_SR_EPH_DEF       1'b0
947 
 
948 
/////////////////////////////////////////////////////
949 
//
950 
// Power Management (PM)
951 
//
952 
 
953 
// Define it if you want PM implemented
954 
// `define OR1200_PM_IMPLEMENTED    -- qaz
955 
 
956 
// Bit positions inside PMR (don't change)
957 
`define OR1200_PM_PMR_SDF 3:0
958 
`define OR1200_PM_PMR_DME 4
959 
`define OR1200_PM_PMR_SME 5
960 
`define OR1200_PM_PMR_DCGE 6
961 
`define OR1200_PM_PMR_UNUSED 31:7
962 
 
963 
// PMR offset inside PM group of registers
964 
`define OR1200_PM_OFS_PMR 11'b0
965 
 
966 
// PM group
967 
`define OR1200_SPRGRP_PM 5'd8
968 
 
969 
// Define if PMR can be read/written at any address inside PM group
970 
`define OR1200_PM_PARTIAL_DECODING
971 
 
972 
// Define if reading PMR is allowed
973 
`define OR1200_PM_READREGS
974 
 
975 
// Define if unused PMR bits should be zero
976 
`define OR1200_PM_UNUSED_ZERO
977 
 
978 
 
979 
/////////////////////////////////////////////////////
980 
//
981 
// Debug Unit (DU)
982 
//
983 
 
984 
// Define it if you want DU implemented
985 
// `define OR1200_DU_IMPLEMENTED    -- qaz
986 
 
987 
//
988 
// Define if you want HW Breakpoints
989 
// (if HW breakpoints are not implemented
990 
// only default software trapping is
991 
// possible with l.trap insn - this is
992 
// however already enough for use
993 
// with or32 gdb)
994 
//
995 
//`define OR1200_DU_HWBKPTS
996 
 
997 
// Number of DVR/DCR pairs if HW breakpoints enabled
998 
`define OR1200_DU_DVRDCR_PAIRS 8
999 
 
1000 
// Define if you want trace buffer
1001 
//`define OR1200_DU_TB_IMPLEMENTED
1002 
 
1003 
//
1004 
// Address offsets of DU registers inside DU group
1005 
//
1006 
// To not implement a register, doq not define its address
1007 
//
1008 
`ifdef OR1200_DU_HWBKPTS
1009 
`define OR1200_DU_DVR0          11'd0
1010 
`define OR1200_DU_DVR1          11'd1
1011 
`define OR1200_DU_DVR2          11'd2
1012 
`define OR1200_DU_DVR3          11'd3
1013 
`define OR1200_DU_DVR4          11'd4
1014 
`define OR1200_DU_DVR5          11'd5
1015 
`define OR1200_DU_DVR6          11'd6
1016 
`define OR1200_DU_DVR7          11'd7
1017 
`define OR1200_DU_DCR0          11'd8
1018 
`define OR1200_DU_DCR1          11'd9
1019 
`define OR1200_DU_DCR2          11'd10
1020 
`define OR1200_DU_DCR3          11'd11
1021 
`define OR1200_DU_DCR4          11'd12
1022 
`define OR1200_DU_DCR5          11'd13
1023 
`define OR1200_DU_DCR6          11'd14
1024 
`define OR1200_DU_DCR7          11'd15
1025 
`endif
1026 
`define OR1200_DU_DMR1          11'd16
1027 
`ifdef OR1200_DU_HWBKPTS
1028 
`define OR1200_DU_DMR2          11'd17
1029 
`define OR1200_DU_DWCR0         11'd18
1030 
`define OR1200_DU_DWCR1         11'd19
1031 
`endif
1032 
`define OR1200_DU_DSR           11'd20
1033 
`define OR1200_DU_DRR           11'd21
1034 
`ifdef OR1200_DU_TB_IMPLEMENTED
1035 
`define OR1200_DU_TBADR         11'h0ff
1036 
`define OR1200_DU_TBIA          11'h1xx
1037 
`define OR1200_DU_TBIM          11'h2xx
1038 
`define OR1200_DU_TBAR          11'h3xx
1039 
`define OR1200_DU_TBTS          11'h4xx
1040 
`endif
1041 
 
1042 
// Position of offset bits inside SPR address
1043 
`define OR1200_DUOFS_BITS       10:0
1044 
 
1045 
// DCR bits
1046 
`define OR1200_DU_DCR_DP        0
1047 
`define OR1200_DU_DCR_CC        3:1
1048 
`define OR1200_DU_DCR_SC        4
1049 
`define OR1200_DU_DCR_CT        7:5
1050 
 
1051 
// DMR1 bits
1052 
`define OR1200_DU_DMR1_CW0      1:0
1053 
`define OR1200_DU_DMR1_CW1      3:2
1054 
`define OR1200_DU_DMR1_CW2      5:4
1055 
`define OR1200_DU_DMR1_CW3      7:6
1056 
`define OR1200_DU_DMR1_CW4      9:8
1057 
`define OR1200_DU_DMR1_CW5      11:10
1058 
`define OR1200_DU_DMR1_CW6      13:12
1059 
`define OR1200_DU_DMR1_CW7      15:14
1060 
`define OR1200_DU_DMR1_CW8      17:16
1061 
`define OR1200_DU_DMR1_CW9      19:18
1062 
`define OR1200_DU_DMR1_CW10     21:20
1063 
`define OR1200_DU_DMR1_ST       22
1064 
`define OR1200_DU_DMR1_BT       23
1065 
`define OR1200_DU_DMR1_DXFW     24
1066 
`define OR1200_DU_DMR1_ETE      25
1067 
 
1068 
// DMR2 bits
1069 
`define OR1200_DU_DMR2_WCE0     0
1070 
`define OR1200_DU_DMR2_WCE1     1
1071 
`define OR1200_DU_DMR2_AWTC     12:2
1072 
`define OR1200_DU_DMR2_WGB      23:13
1073 
 
1074 
// DWCR bits
1075 
`define OR1200_DU_DWCR_COUNT    15:0
1076 
`define OR1200_DU_DWCR_MATCH    31:16
1077 
 
1078 
// DSR bits
1079 
`define OR1200_DU_DSR_WIDTH     14
1080 
`define OR1200_DU_DSR_RSTE      0
1081 
`define OR1200_DU_DSR_BUSEE     1
1082 
`define OR1200_DU_DSR_DPFE      2
1083 
`define OR1200_DU_DSR_IPFE      3
1084 
`define OR1200_DU_DSR_TTE       4
1085 
`define OR1200_DU_DSR_AE        5
1086 
`define OR1200_DU_DSR_IIE       6
1087 
`define OR1200_DU_DSR_IE        7
1088 
`define OR1200_DU_DSR_DME       8
1089 
`define OR1200_DU_DSR_IME       9
1090 
`define OR1200_DU_DSR_RE        10
1091 
`define OR1200_DU_DSR_SCE       11
1092 
`define OR1200_DU_DSR_BE        12
1093 
`define OR1200_DU_DSR_TE        13
1094 
 
1095 
// DRR bits
1096 
`define OR1200_DU_DRR_RSTE      0
1097 
`define OR1200_DU_DRR_BUSEE     1
1098 
`define OR1200_DU_DRR_DPFE      2
1099 
`define OR1200_DU_DRR_IPFE      3
1100 
`define OR1200_DU_DRR_TTE       4
1101 
`define OR1200_DU_DRR_AE        5
1102 
`define OR1200_DU_DRR_IIE       6
1103 
`define OR1200_DU_DRR_IE        7
1104 
`define OR1200_DU_DRR_DME       8
1105 
`define OR1200_DU_DRR_IME       9
1106 
`define OR1200_DU_DRR_RE        10
1107 
`define OR1200_DU_DRR_SCE       11
1108 
`define OR1200_DU_DRR_BE        12
1109 
`define OR1200_DU_DRR_TE        13
1110 
 
1111 
// Define if reading DU regs is allowed
1112 
`define OR1200_DU_READREGS
1113 
 
1114 
// Define if unused DU registers bits should be zero
1115 
`define OR1200_DU_UNUSED_ZERO
1116 
 
1117 
// Define if IF/LSU status is not needed by devel i/f
1118 
`define OR1200_DU_STATUS_UNIMPLEMENTED
1119 
 
1120 
/////////////////////////////////////////////////////
1121 
//
1122 
// Programmable Interrupt Controller (PIC)
1123 
//
1124 
 
1125 
// Define it if you want PIC implemented
1126 
// `define OR1200_PIC_IMPLEMENTED   -- qaz
1127 
 
1128 
// Define number of interrupt inputs (2-31)
1129 
`define OR1200_PIC_INTS 20
1130 
 
1131 
// Address offsets of PIC registers inside PIC group
1132 
`define OR1200_PIC_OFS_PICMR 2'd0
1133 
`define OR1200_PIC_OFS_PICSR 2'd2
1134 
 
1135 
// Position of offset bits inside SPR address
1136 
`define OR1200_PICOFS_BITS 1:0
1137 
 
1138 
// Define if you want these PIC registers to be implemented
1139 
`define OR1200_PIC_PICMR
1140 
`define OR1200_PIC_PICSR
1141 
 
1142 
// Define if reading PIC registers is allowed
1143 
`define OR1200_PIC_READREGS
1144 
 
1145 
// Define if unused PIC register bits should be zero
1146 
`define OR1200_PIC_UNUSED_ZERO
1147 
 
1148 
 
1149 
/////////////////////////////////////////////////////
1150 
//
1151 
// Tick Timer (TT)
1152 
//
1153 
 
1154 
// Define it if you want TT implemented
1155 
// `define OR1200_TT_IMPLEMENTED    -- qaz
1156 
 
1157 
// Address offsets of TT registers inside TT group
1158 
`define OR1200_TT_OFS_TTMR 1'd0
1159 
`define OR1200_TT_OFS_TTCR 1'd1
1160 
 
1161 
// Position of offset bits inside SPR group
1162 
`define OR1200_TTOFS_BITS 0
1163 
 
1164 
// Define if you want these TT registers to be implemented
1165 
`define OR1200_TT_TTMR
1166 
`define OR1200_TT_TTCR
1167 
 
1168 
// TTMR bits
1169 
`define OR1200_TT_TTMR_TP 27:0
1170 
`define OR1200_TT_TTMR_IP 28
1171 
`define OR1200_TT_TTMR_IE 29
1172 
`define OR1200_TT_TTMR_M 31:30
1173 
 
1174 
// Define if reading TT registers is allowed
1175 
`define OR1200_TT_READREGS
1176 
 
1177 
 
1178 
//////////////////////////////////////////////
1179 
//
1180 
// MAC
1181 
//
1182 
`define OR1200_MAC_ADDR         0        // MACLO 0xxxxxxxx1, MACHI 0xxxxxxxx0
1183 
`define OR1200_MAC_SPR_WE               // Define if MACLO/MACHI are SPR writable
1184 
 
1185 
//
1186 
// Shift {MACHI,MACLO} into destination register when executing l.macrc
1187 
//
1188 
// According to architecture manual there is no shift, so default value is 0.
1189 
//
1190 
// However the implementation has deviated in this from the arch manual and had hard coded shift by 28 bits which
1191 
// is a useful optimization for MP3 decoding (if using libmad fixed point library). Shifts are no longer
1192 
// default setup, but if you need to remain backward compatible, define your shift bits, which were normally
1193 
// dest_GPR = {MACHI,MACLO}[59:28]
1194 
`define OR1200_MAC_SHIFTBY      0        // 0 = According to arch manual, 28 = obsolete backward compatibility
1195 
 
1196 
 
1197 
//////////////////////////////////////////////
1198 
//
1199 
// Data MMU (DMMU)
1200 
//
1201 
 
1202 
//
1203 
// Address that selects between TLB TR and MR
1204 
//
1205 
`define OR1200_DTLB_TM_ADDR     7
1206 
 
1207 
//
1208 
// DTLBMR fields
1209 
//
1210 
`define OR1200_DTLBMR_V_BITS    0
1211 
`define OR1200_DTLBMR_CID_BITS  4:1
1212 
`define OR1200_DTLBMR_RES_BITS  11:5
1213 
`define OR1200_DTLBMR_VPN_BITS  31:13
1214 
 
1215 
//
1216 
// DTLBTR fields
1217 
//
1218 
`define OR1200_DTLBTR_CC_BITS   0
1219 
`define OR1200_DTLBTR_CI_BITS   1
1220 
`define OR1200_DTLBTR_WBC_BITS  2
1221 
`define OR1200_DTLBTR_WOM_BITS  3
1222 
`define OR1200_DTLBTR_A_BITS    4
1223 
`define OR1200_DTLBTR_D_BITS    5
1224 
`define OR1200_DTLBTR_URE_BITS  6
1225 
`define OR1200_DTLBTR_UWE_BITS  7
1226 
`define OR1200_DTLBTR_SRE_BITS  8
1227 
`define OR1200_DTLBTR_SWE_BITS  9
1228 
`define OR1200_DTLBTR_RES_BITS  11:10
1229 
`define OR1200_DTLBTR_PPN_BITS  31:13
1230 
 
1231 
//
1232 
// DTLB configuration
1233 
//
1234 
`define OR1200_DMMU_PS          13                                      // 13 for 8KB page size
1235 
`define OR1200_DTLB_INDXW       6                                       // 6 for 64 entry DTLB  7 for 128 entries
1236 
`define OR1200_DTLB_INDXL       `OR1200_DMMU_PS                         // 13                   13
1237 
`define OR1200_DTLB_INDXH       `OR1200_DMMU_PS+`OR1200_DTLB_INDXW-1    // 18                   19
1238 
`define OR1200_DTLB_INDX        `OR1200_DTLB_INDXH:`OR1200_DTLB_INDXL   // 18:13                19:13
1239 
`define OR1200_DTLB_TAGW        32-`OR1200_DTLB_INDXW-`OR1200_DMMU_PS   // 13                   12
1240 
`define OR1200_DTLB_TAGL        `OR1200_DTLB_INDXH+1                    // 19                   20
1241 
`define OR1200_DTLB_TAG         31:`OR1200_DTLB_TAGL                    // 31:19                31:20
1242 
`define OR1200_DTLBMRW          `OR1200_DTLB_TAGW+1                     // +1 because of V bit
1243 
`define OR1200_DTLBTRW          32-`OR1200_DMMU_PS+5                    // +5 because of protection bits and CI
1244 
 
1245 
//
1246 
// Cache inhibit while DMMU is not enabled/implemented
1247 
//
1248 
// cache inhibited 0GB-4GB              1'b1
1249 
// cache inhibited 0GB-2GB              !dcpu_adr_i[31]
1250 
// cache inhibited 0GB-1GB 2GB-3GB      !dcpu_adr_i[30]
1251 
// cache inhibited 1GB-2GB 3GB-4GB      dcpu_adr_i[30]
1252 
// cache inhibited 2GB-4GB (default)    dcpu_adr_i[31]
1253 
// cached 0GB-4GB                       1'b0
1254 
//
1255 
`define OR1200_DMMU_CI                  dcpu_adr_i[31]
1256 
 
1257 
 
1258 
//////////////////////////////////////////////
1259 
//
1260 
// Insn MMU (IMMU)
1261 
//
1262 
 
1263 
//
1264 
// Address that selects between TLB TR and MR
1265 
//
1266 
`define OR1200_ITLB_TM_ADDR     7
1267 
 
1268 
//
1269 
// ITLBMR fields
1270 
//
1271 
`define OR1200_ITLBMR_V_BITS    0
1272 
`define OR1200_ITLBMR_CID_BITS  4:1
1273 
`define OR1200_ITLBMR_RES_BITS  11:5
1274 
`define OR1200_ITLBMR_VPN_BITS  31:13
1275 
 
1276 
//
1277 
// ITLBTR fields
1278 
//
1279 
`define OR1200_ITLBTR_CC_BITS   0
1280 
`define OR1200_ITLBTR_CI_BITS   1
1281 
`define OR1200_ITLBTR_WBC_BITS  2
1282 
`define OR1200_ITLBTR_WOM_BITS  3
1283 
`define OR1200_ITLBTR_A_BITS    4
1284 
`define OR1200_ITLBTR_D_BITS    5
1285 
`define OR1200_ITLBTR_SXE_BITS  6
1286 
`define OR1200_ITLBTR_UXE_BITS  7
1287 
`define OR1200_ITLBTR_RES_BITS  11:8
1288 
`define OR1200_ITLBTR_PPN_BITS  31:13
1289 
 
1290 
//
1291 
// ITLB configuration
1292 
//
1293 
`define OR1200_IMMU_PS          13                                      // 13 for 8KB page size
1294 
`define OR1200_ITLB_INDXW       6                                       // 6 for 64 entry ITLB  7 for 128 entries
1295 
`define OR1200_ITLB_INDXL       `OR1200_IMMU_PS                         // 13                   13
1296 
`define OR1200_ITLB_INDXH       `OR1200_IMMU_PS+`OR1200_ITLB_INDXW-1    // 18                   19
1297 
`define OR1200_ITLB_INDX        `OR1200_ITLB_INDXH:`OR1200_ITLB_INDXL   // 18:13                19:13
1298 
`define OR1200_ITLB_TAGW        32-`OR1200_ITLB_INDXW-`OR1200_IMMU_PS   // 13                   12
1299 
`define OR1200_ITLB_TAGL        `OR1200_ITLB_INDXH+1                    // 19                   20
1300 
`define OR1200_ITLB_TAG         31:`OR1200_ITLB_TAGL                    // 31:19                31:20
1301 
`define OR1200_ITLBMRW          `OR1200_ITLB_TAGW+1                     // +1 because of V bit
1302 
`define OR1200_ITLBTRW          32-`OR1200_IMMU_PS+3                    // +3 because of protection bits and CI
1303 
 
1304 
//
1305 
// Cache inhibit while IMMU is not enabled/implemented
1306 
// Note: all combinations that use icpu_adr_i cause async loop
1307 
//
1308 
// cache inhibited 0GB-4GB              1'b1
1309 
// cache inhibited 0GB-2GB              !icpu_adr_i[31]
1310 
// cache inhibited 0GB-1GB 2GB-3GB      !icpu_adr_i[30]
1311 
// cache inhibited 1GB-2GB 3GB-4GB      icpu_adr_i[30]
1312 
// cache inhibited 2GB-4GB (default)    icpu_adr_i[31]
1313 
// cached 0GB-4GB                       1'b0
1314 
//
1315 
`define OR1200_IMMU_CI                  1'b0
1316 
 
1317 
 
1318 
/////////////////////////////////////////////////
1319 
//
1320 
// Insn cache (IC)
1321 
//
1322 
 
1323 
// 3 for 8 bytes, 4 for 16 bytes etc
1324 
`define OR1200_ICLS             4
1325 
 
1326 
//
1327 
// IC configurations
1328 
//
1329 
`ifdef OR1200_IC_1W_512B
1330 
`define OR1200_ICSIZE   9     // 512
1331 
`define OR1200_ICINDX   `OR1200_ICSIZE-2 // 7
1332 
`define OR1200_ICINDXH  `OR1200_ICSIZE-1 // 8
1333 
`define OR1200_ICTAGL   `OR1200_ICINDXH+1 // 9
1334 
`define OR1200_ICTAG    `OR1200_ICSIZE-`OR1200_ICLS // 5
1335 
`define OR1200_ICTAG_W  24
1336 
`endif
1337 
`ifdef OR1200_IC_1W_4KB
1338 
`define OR1200_ICSIZE                   12                      // 4096
1339 
`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 10
1340 
`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 11
1341 
`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 12
1342 
`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS     // 8
1343 
`define OR1200_ICTAG_W                  21
1344 
`endif
1345 
`ifdef OR1200_IC_1W_8KB
1346 
`define OR1200_ICSIZE                   13                      // 8192
1347 
`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 11
1348 
`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 12
1349 
`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 13
1350 
`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS     // 9
1351 
`define OR1200_ICTAG_W                  20
1352 
`endif
1353 
 
1354 
 
1355 
/////////////////////////////////////////////////
1356 
//
1357 
// Data cache (DC)
1358 
//
1359 
 
1360 
// 3 for 8 bytes, 4 for 16 bytes etc
1361 
`define OR1200_DCLS             4
1362 
 
1363 
// Define to perform store refill (potential performance penalty)
1364 
// `define OR1200_DC_STORE_REFILL
1365 
 
1366 
//
1367 
// DC configurations
1368 
//
1369 
`ifdef OR1200_DC_1W_4KB
1370 
`define OR1200_DCSIZE                   12                      // 4096
1371 
`define OR1200_DCINDX                   `OR1200_DCSIZE-2        // 10
1372 
`define OR1200_DCINDXH                  `OR1200_DCSIZE-1        // 11
1373 
`define OR1200_DCTAGL                   `OR1200_DCINDXH+1       // 12
1374 
`define OR1200_DCTAG                    `OR1200_DCSIZE-`OR1200_DCLS     // 8
1375 
`define OR1200_DCTAG_W                  21
1376 
`endif
1377 
`ifdef OR1200_DC_1W_8KB
1378 
`define OR1200_DCSIZE                   13                      // 8192
1379 
`define OR1200_DCINDX                   `OR1200_DCSIZE-2        // 11
1380 
`define OR1200_DCINDXH                  `OR1200_DCSIZE-1        // 12
1381 
`define OR1200_DCTAGL                   `OR1200_DCINDXH+1       // 13
1382 
`define OR1200_DCTAG                    `OR1200_DCSIZE-`OR1200_DCLS     // 9
1383 
`define OR1200_DCTAG_W                  20
1384 
`endif
1385 
 
1386 
/////////////////////////////////////////////////
1387 
//
1388 
// Store buffer (SB)
1389 
//
1390 
 
1391 
//
1392 
// Store buffer
1393 
//
1394 
// It will improve performance by "caching" CPU stores
1395 
// using store buffer. This is most important for function
1396 
// prologues because DC can only work in write though mode
1397 
// and all stores would have to complete external WB writes
1398 
// to memory.
1399 
// Store buffer is between DC and data BIU.
1400 
// All stores will be stored into store buffer and immediately
1401 
// completed by the CPU, even though actual external writes
1402 
// will be performed later. As a consequence store buffer masks
1403 
// all data bus errors related to stores (data bus errors
1404 
// related to loads are delivered normally).
1405 
// All pending CPU loads will wait until store buffer is empty to
1406 
// ensure strict memory model. Right now this is necessary because
1407 
// we don't make destinction between cached and cache inhibited
1408 
// address space, so we simply empty store buffer until loads
1409 
// can begin.
1410 
//
1411 
// It makes design a bit bigger, depending what is the number of
1412 
// entries in SB FIFO. Number of entries can be changed further
1413 
// down.
1414 
//
1415 
//`define OR1200_SB_IMPLEMENTED
1416 
 
1417 
//
1418 
// Number of store buffer entries
1419 
//
1420 
// Verified number of entries are 4 and 8 entries
1421 
// (2 and 3 for OR1200_SB_LOG). OR1200_SB_ENTRIES must
1422 
// always match 2**OR1200_SB_LOG.
1423 
// To disable store buffer, undefine
1424 
// OR1200_SB_IMPLEMENTED.
1425 
//
1426 
`define OR1200_SB_LOG           2       // 2 or 3
1427 
`define OR1200_SB_ENTRIES       4       // 4 or 8
1428 
 
1429 
 
1430 
/////////////////////////////////////////////////
1431 
//
1432 
// Quick Embedded Memory (QMEM)
1433 
//
1434 
 
1435 
//
1436 
// Quick Embedded Memory
1437 
//
1438 
// Instantiation of dedicated insn/data memory (RAM or ROM).
1439 
// Insn fetch has effective throughput 1insn / clock cycle.
1440 
// Data load takes two clock cycles / access, data store
1441 
// takes 1 clock cycle / access (if there is no insn fetch)).
1442 
// Memory instantiation is shared between insn and data,
1443 
// meaning if insn fetch are performed, data load/store
1444 
// performance will be lower.
1445 
//
1446 
// Main reason for QMEM is to put some time critical functions
1447 
// into this memory and to have predictable and fast access
1448 
// to these functions. (soft fpu, context switch, exception
1449 
// handlers, stack, etc)
1450 
//
1451 
// It makes design a bit bigger and slower. QMEM sits behind
1452 
// IMMU/DMMU so all addresses are physical (so the MMUs can be
1453 
// used with QMEM and QMEM is seen by the CPU just like any other
1454 
// memory in the system). IC/DC are sitting behind QMEM so the
1455 
// whole design timing might be worse with QMEM implemented.
1456 
//
1457 
// `define OR1200_QMEM_IMPLEMENTED
1458 
 
1459 
//
1460 
// Base address and mask of QMEM
1461 
//
1462 
// Base address defines first address of QMEM. Mask defines
1463 
// QMEM range in address space. Actual size of QMEM is however
1464 
// determined with instantiated RAM/ROM. However bigger
1465 
// mask will reserve more address space for QMEM, but also
1466 
// make design faster, while more tight mask will take
1467 
// less address space but also make design slower. If
1468 
// instantiated RAM/ROM is smaller than space reserved with
1469 
// the mask, instatiated RAM/ROM will also be shadowed
1470 
// at higher addresses in reserved space.
1471 
//
1472 
`define OR1200_QMEM_IADDR       32'hffe0_0000
1473 
`define OR1200_QMEM_IMASK       32'hfff0_0000   // Max QMEM size 1MB
1474 
`define OR1200_QMEM_DADDR  32'hffe0_0000
1475 
`define OR1200_QMEM_DMASK  32'hfff0_0000 // Max QMEM size 1MB
1476 
 
1477 
//
1478 
// QMEM interface byte-select capability
1479 
//
1480 
// To enable qmem_sel* ports, define this macro.
1481 
//
1482 
//`define OR1200_QMEM_BSEL
1483 
 
1484 
//
1485 
// QMEM interface acknowledge
1486 
//
1487 
// To enable qmem_ack port, define this macro.
1488 
//
1489 
//`define OR1200_QMEM_ACK
1490 
 
1491 
/////////////////////////////////////////////////////
1492 
//
1493 
// VR, UPR and Configuration Registers
1494 
//
1495 
//
1496 
// VR, UPR and configuration registers are optional. If
1497 
// implemented, operating system can automatically figure
1498 
// out how to use the processor because it knows
1499 
// what units are available in the processor and how they
1500 
// are configured.
1501 
//
1502 
// This section must be last in or1200_defines.v file so
1503 
// that all units are already configured and thus
1504 
// configuration registers are properly set.
1505 
//
1506 
 
1507 
// Define if you want configuration registers implemented
1508 
`define OR1200_CFGR_IMPLEMENTED
1509 
 
1510 
// Define if you want full address decode inside SYS group
1511 
`define OR1200_SYS_FULL_DECODE
1512 
 
1513 
// Offsets of VR, UPR and CFGR registers
1514 
`define OR1200_SPRGRP_SYS_VR            4'h0
1515 
`define OR1200_SPRGRP_SYS_UPR           4'h1
1516 
`define OR1200_SPRGRP_SYS_CPUCFGR       4'h2
1517 
`define OR1200_SPRGRP_SYS_DMMUCFGR      4'h3
1518 
`define OR1200_SPRGRP_SYS_IMMUCFGR      4'h4
1519 
`define OR1200_SPRGRP_SYS_DCCFGR        4'h5
1520 
`define OR1200_SPRGRP_SYS_ICCFGR        4'h6
1521 
`define OR1200_SPRGRP_SYS_DCFGR 4'h7
1522 
 
1523 
// VR fields
1524 
`define OR1200_VR_REV_BITS              5:0
1525 
`define OR1200_VR_RES1_BITS             15:6
1526 
`define OR1200_VR_CFG_BITS              23:16
1527 
`define OR1200_VR_VER_BITS              31:24
1528 
 
1529 
// VR values
1530 
`define OR1200_VR_REV                   6'h01
1531 
`define OR1200_VR_RES1                  10'h000
1532 
`define OR1200_VR_CFG                   8'h00
1533 
`define OR1200_VR_VER                   8'h12
1534 
 
1535 
// UPR fields
1536 
`define OR1200_UPR_UP_BITS              0
1537 
`define OR1200_UPR_DCP_BITS             1
1538 
`define OR1200_UPR_ICP_BITS             2
1539 
`define OR1200_UPR_DMP_BITS             3
1540 
`define OR1200_UPR_IMP_BITS             4
1541 
`define OR1200_UPR_MP_BITS              5
1542 
`define OR1200_UPR_DUP_BITS             6
1543 
`define OR1200_UPR_PCUP_BITS            7
1544 
`define OR1200_UPR_PMP_BITS             8
1545 
`define OR1200_UPR_PICP_BITS            9
1546 
`define OR1200_UPR_TTP_BITS             10
1547 
`define OR1200_UPR_RES1_BITS            23:11
1548 
`define OR1200_UPR_CUP_BITS             31:24
1549 
 
1550 
// UPR values
1551 
`define OR1200_UPR_UP                   1'b1
1552 
`ifdef OR1200_NO_DC
1553 
`define OR1200_UPR_DCP                  1'b0
1554 
`else
1555 
`define OR1200_UPR_DCP                  1'b1
1556 
`endif
1557 
`ifdef OR1200_NO_IC
1558 
`define OR1200_UPR_ICP                  1'b0
1559 
`else
1560 
`define OR1200_UPR_ICP                  1'b1
1561 
`endif
1562 
`ifdef OR1200_NO_DMMU
1563 
`define OR1200_UPR_DMP                  1'b0
1564 
`else
1565 
`define OR1200_UPR_DMP                  1'b1
1566 
`endif
1567 
`ifdef OR1200_NO_IMMU
1568 
`define OR1200_UPR_IMP                  1'b0
1569 
`else
1570 
`define OR1200_UPR_IMP                  1'b1
1571 
`endif
1572 
`define OR1200_UPR_MP                   1'b1    // MAC always present
1573 
`ifdef OR1200_DU_IMPLEMENTED
1574 
`define OR1200_UPR_DUP                  1'b1
1575 
`else
1576 
`define OR1200_UPR_DUP                  1'b0
1577 
`endif
1578 
`define OR1200_UPR_PCUP                 1'b0    // Performance counters not present
1579 
`ifdef OR1200_DU_IMPLEMENTED
1580 
`define OR1200_UPR_PMP                  1'b1
1581 
`else
1582 
`define OR1200_UPR_PMP                  1'b0
1583 
`endif
1584 
`ifdef OR1200_DU_IMPLEMENTED
1585 
`define OR1200_UPR_PICP                 1'b1
1586 
`else
1587 
`define OR1200_UPR_PICP                 1'b0
1588 
`endif
1589 
`ifdef OR1200_DU_IMPLEMENTED
1590 
`define OR1200_UPR_TTP                  1'b1
1591 
`else
1592 
`define OR1200_UPR_TTP                  1'b0
1593 
`endif
1594 
`define OR1200_UPR_RES1                 13'h0000
1595 
`define OR1200_UPR_CUP                  8'h00
1596 
 
1597 
// CPUCFGR fields
1598 
`define OR1200_CPUCFGR_NSGF_BITS        3:0
1599 
`define OR1200_CPUCFGR_HGF_BITS 4
1600 
`define OR1200_CPUCFGR_OB32S_BITS       5
1601 
`define OR1200_CPUCFGR_OB64S_BITS       6
1602 
`define OR1200_CPUCFGR_OF32S_BITS       7
1603 
`define OR1200_CPUCFGR_OF64S_BITS       8
1604 
`define OR1200_CPUCFGR_OV64S_BITS       9
1605 
`define OR1200_CPUCFGR_RES1_BITS        31:10
1606 
 
1607 
// CPUCFGR values
1608 
`define OR1200_CPUCFGR_NSGF             4'h0
1609 
`define OR1200_CPUCFGR_HGF              1'b0
1610 
`define OR1200_CPUCFGR_OB32S            1'b1
1611 
`define OR1200_CPUCFGR_OB64S            1'b0
1612 
`define OR1200_CPUCFGR_OF32S            1'b0
1613 
`define OR1200_CPUCFGR_OF64S            1'b0
1614 
`define OR1200_CPUCFGR_OV64S            1'b0
1615 
`define OR1200_CPUCFGR_RES1             22'h000000
1616 
 
1617 
// DMMUCFGR fields
1618 
`define OR1200_DMMUCFGR_NTW_BITS        1:0
1619 
`define OR1200_DMMUCFGR_NTS_BITS        4:2
1620 
`define OR1200_DMMUCFGR_NAE_BITS        7:5
1621 
`define OR1200_DMMUCFGR_CRI_BITS        8
1622 
`define OR1200_DMMUCFGR_PRI_BITS        9
1623 
`define OR1200_DMMUCFGR_TEIRI_BITS      10
1624 
`define OR1200_DMMUCFGR_HTR_BITS        11
1625 
`define OR1200_DMMUCFGR_RES1_BITS       31:12
1626 
 
1627 
// DMMUCFGR values
1628 
`ifdef OR1200_NO_DMMU
1629 
`define OR1200_DMMUCFGR_NTW             2'h0    // Irrelevant
1630 
`define OR1200_DMMUCFGR_NTS             3'h0    // Irrelevant
1631 
`define OR1200_DMMUCFGR_NAE             3'h0    // Irrelevant
1632 
`define OR1200_DMMUCFGR_CRI             1'b0    // Irrelevant
1633 
`define OR1200_DMMUCFGR_PRI             1'b0    // Irrelevant
1634 
`define OR1200_DMMUCFGR_TEIRI           1'b0    // Irrelevant
1635 
`define OR1200_DMMUCFGR_HTR             1'b0    // Irrelevant
1636 
`define OR1200_DMMUCFGR_RES1            20'h00000
1637 
`else
1638 
`define OR1200_DMMUCFGR_NTW             2'h0    // 1 TLB way
1639 
`define OR1200_DMMUCFGR_NTS 3'h`OR1200_DTLB_INDXW       // Num TLB sets
1640 
`define OR1200_DMMUCFGR_NAE             3'h0    // No ATB entries
1641 
`define OR1200_DMMUCFGR_CRI             1'b0    // No control register
1642 
`define OR1200_DMMUCFGR_PRI             1'b0    // No protection reg
1643 
`define OR1200_DMMUCFGR_TEIRI           1'b1    // TLB entry inv reg impl.
1644 
`define OR1200_DMMUCFGR_HTR             1'b0    // No HW TLB reload
1645 
`define OR1200_DMMUCFGR_RES1            20'h00000
1646 
`endif
1647 
 
1648 
// IMMUCFGR fields
1649 
`define OR1200_IMMUCFGR_NTW_BITS        1:0
1650 
`define OR1200_IMMUCFGR_NTS_BITS        4:2
1651 
`define OR1200_IMMUCFGR_NAE_BITS        7:5
1652 
`define OR1200_IMMUCFGR_CRI_BITS        8
1653 
`define OR1200_IMMUCFGR_PRI_BITS        9
1654 
`define OR1200_IMMUCFGR_TEIRI_BITS      10
1655 
`define OR1200_IMMUCFGR_HTR_BITS        11
1656 
`define OR1200_IMMUCFGR_RES1_BITS       31:12
1657 
 
1658 
// IMMUCFGR values
1659 
`ifdef OR1200_NO_IMMU
1660 
`define OR1200_IMMUCFGR_NTW             2'h0    // Irrelevant
1661 
`define OR1200_IMMUCFGR_NTS             3'h0    // Irrelevant
1662 
`define OR1200_IMMUCFGR_NAE             3'h0    // Irrelevant
1663 
`define OR1200_IMMUCFGR_CRI             1'b0    // Irrelevant
1664 
`define OR1200_IMMUCFGR_PRI             1'b0    // Irrelevant
1665 
`define OR1200_IMMUCFGR_TEIRI           1'b0    // Irrelevant
1666 
`define OR1200_IMMUCFGR_HTR             1'b0    // Irrelevant
1667 
`define OR1200_IMMUCFGR_RES1            20'h00000
1668 
`else
1669 
`define OR1200_IMMUCFGR_NTW             2'h0    // 1 TLB way
1670 
`define OR1200_IMMUCFGR_NTS 3'h`OR1200_ITLB_INDXW       // Num TLB sets
1671 
`define OR1200_IMMUCFGR_NAE             3'h0    // No ATB entry
1672 
`define OR1200_IMMUCFGR_CRI             1'b0    // No control reg
1673 
`define OR1200_IMMUCFGR_PRI             1'b0    // No protection reg
1674 
`define OR1200_IMMUCFGR_TEIRI           1'b1    // TLB entry inv reg impl
1675 
`define OR1200_IMMUCFGR_HTR             1'b0    // No HW TLB reload
1676 
`define OR1200_IMMUCFGR_RES1            20'h00000
1677 
`endif
1678 
 
1679 
// DCCFGR fields
1680 
`define OR1200_DCCFGR_NCW_BITS          2:0
1681 
`define OR1200_DCCFGR_NCS_BITS          6:3
1682 
`define OR1200_DCCFGR_CBS_BITS          7
1683 
`define OR1200_DCCFGR_CWS_BITS          8
1684 
`define OR1200_DCCFGR_CCRI_BITS         9
1685 
`define OR1200_DCCFGR_CBIRI_BITS        10
1686 
`define OR1200_DCCFGR_CBPRI_BITS        11
1687 
`define OR1200_DCCFGR_CBLRI_BITS        12
1688 
`define OR1200_DCCFGR_CBFRI_BITS        13
1689 
`define OR1200_DCCFGR_CBWBRI_BITS       14
1690 
`define OR1200_DCCFGR_RES1_BITS 31:15
1691 
 
1692 
// DCCFGR values
1693 
`ifdef OR1200_NO_DC
1694 
`define OR1200_DCCFGR_NCW               3'h0    // Irrelevant
1695 
`define OR1200_DCCFGR_NCS               4'h0    // Irrelevant
1696 
`define OR1200_DCCFGR_CBS               1'b0    // Irrelevant
1697 
`define OR1200_DCCFGR_CWS               1'b0    // Irrelevant
1698 
`define OR1200_DCCFGR_CCRI              1'b1    // Irrelevant
1699 
`define OR1200_DCCFGR_CBIRI             1'b1    // Irrelevant
1700 
`define OR1200_DCCFGR_CBPRI             1'b0    // Irrelevant
1701 
`define OR1200_DCCFGR_CBLRI             1'b0    // Irrelevant
1702 
`define OR1200_DCCFGR_CBFRI             1'b1    // Irrelevant
1703 
`define OR1200_DCCFGR_CBWBRI            1'b0    // Irrelevant
1704 
`define OR1200_DCCFGR_RES1              17'h00000
1705 
`else
1706 
`define OR1200_DCCFGR_NCW               3'h0    // 1 cache way
1707 
`define OR1200_DCCFGR_NCS (`OR1200_DCTAG)       // Num cache sets
1708 
`define OR1200_DCCFGR_CBS (`OR1200_DCLS-4)      // 16 byte cache block
1709 
`define OR1200_DCCFGR_CWS               1'b0    // Write-through strategy
1710 
`define OR1200_DCCFGR_CCRI              1'b1    // Cache control reg impl.
1711 
`define OR1200_DCCFGR_CBIRI             1'b1    // Cache block inv reg impl.
1712 
`define OR1200_DCCFGR_CBPRI             1'b0    // Cache block prefetch reg not impl.
1713 
`define OR1200_DCCFGR_CBLRI             1'b0    // Cache block lock reg not impl.
1714 
`define OR1200_DCCFGR_CBFRI             1'b1    // Cache block flush reg impl.
1715 
`define OR1200_DCCFGR_CBWBRI            1'b0    // Cache block WB reg not impl.
1716 
`define OR1200_DCCFGR_RES1              17'h00000
1717 
`endif
1718 
 
1719 
// ICCFGR fields
1720 
`define OR1200_ICCFGR_NCW_BITS          2:0
1721 
`define OR1200_ICCFGR_NCS_BITS          6:3
1722 
`define OR1200_ICCFGR_CBS_BITS          7
1723 
`define OR1200_ICCFGR_CWS_BITS          8
1724 
`define OR1200_ICCFGR_CCRI_BITS         9
1725 
`define OR1200_ICCFGR_CBIRI_BITS        10
1726 
`define OR1200_ICCFGR_CBPRI_BITS        11
1727 
`define OR1200_ICCFGR_CBLRI_BITS        12
1728 
`define OR1200_ICCFGR_CBFRI_BITS        13
1729 
`define OR1200_ICCFGR_CBWBRI_BITS       14
1730 
`define OR1200_ICCFGR_RES1_BITS 31:15
1731 
 
1732 
// ICCFGR values
1733 
`ifdef OR1200_NO_IC
1734 
`define OR1200_ICCFGR_NCW               3'h0    // Irrelevant
1735 
`define OR1200_ICCFGR_NCS               4'h0    // Irrelevant
1736 
`define OR1200_ICCFGR_CBS               1'b0    // Irrelevant
1737 
`define OR1200_ICCFGR_CWS               1'b0    // Irrelevant
1738 
`define OR1200_ICCFGR_CCRI              1'b0    // Irrelevant
1739 
`define OR1200_ICCFGR_CBIRI             1'b0    // Irrelevant
1740 
`define OR1200_ICCFGR_CBPRI             1'b0    // Irrelevant
1741 
`define OR1200_ICCFGR_CBLRI             1'b0    // Irrelevant
1742 
`define OR1200_ICCFGR_CBFRI             1'b0    // Irrelevant
1743 
`define OR1200_ICCFGR_CBWBRI            1'b0    // Irrelevant
1744 
`define OR1200_ICCFGR_RES1              17'h00000
1745 
`else
1746 
`define OR1200_ICCFGR_NCW               3'h0    // 1 cache way
1747 
`define OR1200_ICCFGR_NCS (`OR1200_ICTAG)       // Num cache sets
1748 
`define OR1200_ICCFGR_CBS (`OR1200_ICLS-4)      // 16 byte cache block
1749 
`define OR1200_ICCFGR_CWS               1'b0    // Irrelevant
1750 
`define OR1200_ICCFGR_CCRI              1'b1    // Cache control reg impl.
1751 
`define OR1200_ICCFGR_CBIRI             1'b1    // Cache block inv reg impl.
1752 
`define OR1200_ICCFGR_CBPRI             1'b0    // Cache block prefetch reg not impl.
1753 
`define OR1200_ICCFGR_CBLRI             1'b0    // Cache block lock reg not impl.
1754 
`define OR1200_ICCFGR_CBFRI             1'b1    // Cache block flush reg impl.
1755 
`define OR1200_ICCFGR_CBWBRI            1'b0    // Irrelevant
1756 
`define OR1200_ICCFGR_RES1              17'h00000
1757 
`endif
1758 
 
1759 
// DCFGR fields
1760 
`define OR1200_DCFGR_NDP_BITS           2:0
1761 
`define OR1200_DCFGR_WPCI_BITS          3
1762 
`define OR1200_DCFGR_RES1_BITS          31:4
1763 
 
1764 
// DCFGR values
1765 
`ifdef OR1200_DU_HWBKPTS
1766 
`define OR1200_DCFGR_NDP        3'h`OR1200_DU_DVRDCR_PAIRS // # of DVR/DCR pairs
1767 
`ifdef OR1200_DU_DWCR0
1768 
`define OR1200_DCFGR_WPCI               1'b1
1769 
`else
1770 
`define OR1200_DCFGR_WPCI               1'b0    // WP counters not impl.
1771 
`endif
1772 
`else
1773 
`define OR1200_DCFGR_NDP                3'h0    // Zero DVR/DCR pairs
1774 
`define OR1200_DCFGR_WPCI               1'b0    // WP counters not impl.
1775 
`endif
1776 
`define OR1200_DCFGR_RES1               28'h0000000
1777 
 

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