OpenCores
URL https://opencores.org/ocsvn/or1200_soc/or1200_soc/trunk

Subversion Repositories or1200_soc

[/] [or1200_soc/] [trunk/] [boards/] [de1_board/] [src/] [or1200_defines.v] - Blame information for rev 24

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 21 qaztronic 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 
////  OR1200's definitions                                        ////
4 
////                                                              ////
5 
////  This file is part of the OpenRISC 1200 project              ////
6 
////  http://www.opencores.org/cores/or1k/                        ////
7 
////                                                              ////
8 
////  Description                                                 ////
9 
////  Parameters of the OR1200 core                               ////
10 
////                                                              ////
11 
////  To Do:                                                      ////
12 
////   - add parameters that are missing                          ////
13 
////                                                              ////
14 
////  Author(s):                                                  ////
15 
////      - Damjan Lampret, lampret@opencores.org                 ////
16 
////                                                              ////
17 
//////////////////////////////////////////////////////////////////////
18 
////                                                              ////
19 
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20 
////                                                              ////
21 
//// This source file may be used and distributed without         ////
22 
//// restriction provided that this copyright statement is not    ////
23 
//// removed from the file and that any derivative work contains  ////
24 
//// the original copyright notice and the associated disclaimer. ////
25 
////                                                              ////
26 
//// This source file is free software; you can redistribute it   ////
27 
//// and/or modify it under the terms of the GNU Lesser General   ////
28 
//// Public License as published by the Free Software Foundation; ////
29 
//// either version 2.1 of the License, or (at your option) any   ////
30 
//// later version.                                               ////
31 
////                                                              ////
32 
//// This source is distributed in the hope that it will be       ////
33 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36 
//// details.                                                     ////
37 
////                                                              ////
38 
//// You should have received a copy of the GNU Lesser General    ////
39 
//// Public License along with this source; if not, download it   ////
40 
//// from http://www.opencores.org/lgpl.shtml                     ////
41 
////                                                              ////
42 
//////////////////////////////////////////////////////////////////////
43 
//
44 
// CVS Revision History
45 
//
46 
// $Log: or1200_defines.v,v $
47 24 qaztronic 
// Revision 1.2  2010/02/15 19:26:03  kenagy
48 
// no message
49 
//
50 21 qaztronic 
// Revision 1.1  2009/03/25 22:16:56  kenagy
51 
// no message
52 
//
53 
// Revision 1.1  2009/02/19 23:49:39  kenagy
54 
// no message
55 
//
56 
// Revision 1.1  2009/02/19 20:11:32  kenagy
57 
// no message
58 
//
59 
// Revision 1.3  2008/08/12 17:03:09  kenagy
60 
// no message
61 
//
62 
// Revision 1.2  2008/07/29 00:53:21  kenagy
63 
// no message
64 
//
65 
// Revision 1.1  2008/06/28 00:57:51  kenagy
66 
// no message
67 
//
68 
// Revision 1.45  2006/04/09 01:32:29  lampret
69 
// See OR1200_MAC_SHIFTBY in or1200_defines.v for explanation of the change. Since now no more 28 bits shift for l.macrc insns however for backward compatbility it is possible to set arbitry number of shifts.
70 
//
71 
// Revision 1.44  2005/10/19 11:37:56  jcastillo
72 
// Added support for RAMB16 Xilinx4/Spartan3 primitives
73 
//
74 
// Revision 1.43  2005/01/07 09:23:39  andreje
75 
// l.ff1 and l.cmov instructions added
76 
//
77 
// Revision 1.42  2004/06/08 18:17:36  lampret
78 
// Non-functional changes. Coding style fixes.
79 
//
80 
// Revision 1.41  2004/05/09 20:03:20  lampret
81 
// By default l.cust5 insns are disabled
82 
//
83 
// Revision 1.40  2004/05/09 19:49:04  lampret
84 
// Added some l.cust5 custom instructions as example
85 
//
86 
// Revision 1.39  2004/04/08 11:00:46  simont
87 
// Add support for 512B instruction cache.
88 
//
89 
// Revision 1.38  2004/04/05 08:29:57  lampret
90 
// Merged branch_qmem into main tree.
91 
//
92 
// Revision 1.35.4.6  2004/02/11 01:40:11  lampret
93 
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
94 
//
95 
// Revision 1.35.4.5  2004/01/15 06:46:38  markom
96 
// interface to debug changed; no more opselect; stb-ack protocol
97 
//
98 
// Revision 1.35.4.4  2004/01/11 22:45:46  andreje
99 
// Separate instruction and data QMEM decoders, QMEM acknowledge and byte-select added
100 
//
101 
// Revision 1.35.4.3  2003/12/17 13:43:38  simons
102 
// Exception prefix configuration changed.
103 
//
104 
// Revision 1.35.4.2  2003/12/05 00:05:03  lampret
105 
// Static exception prefix.
106 
//
107 
// Revision 1.35.4.1  2003/07/08 15:36:37  lampret
108 
// Added embedded memory QMEM.
109 
//
110 
// Revision 1.35  2003/04/24 00:16:07  lampret
111 
// No functional changes. Added defines to disable implementation of multiplier/MAC
112 
//
113 
// Revision 1.34  2003/04/20 22:23:57  lampret
114 
// No functional change. Only added customization for exception vectors.
115 
//
116 
// Revision 1.33  2003/04/07 20:56:07  lampret
117 
// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description.
118 
//
119 
// Revision 1.32  2003/04/07 01:26:57  lampret
120 
// RFRAM defines comments updated. Altera LPM option added.
121 
//
122 
// Revision 1.31  2002/12/08 08:57:56  lampret
123 
// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
124 
//
125 
// Revision 1.30  2002/10/28 15:09:22  mohor
126 
// Previous check-in was done by mistake.
127 
//
128 
// Revision 1.29  2002/10/28 15:03:50  mohor
129 
// Signal scanb_sen renamed to scanb_en.
130 
//
131 
// Revision 1.28  2002/10/17 20:04:40  lampret
132 
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
133 
//
134 
// Revision 1.27  2002/09/16 03:13:23  lampret
135 
// Removed obsolete comment.
136 
//
137 
// Revision 1.26  2002/09/08 05:52:16  lampret
138 
// Added optional l.div/l.divu insns. By default they are disabled.
139 
//
140 
// Revision 1.25  2002/09/07 19:16:10  lampret
141 
// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].
142 
//
143 
// Revision 1.24  2002/09/07 05:42:02  lampret
144 
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
145 
//
146 
// Revision 1.23  2002/09/04 00:50:34  lampret
147 
// Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v.
148 
//
149 
// Revision 1.22  2002/09/03 22:28:21  lampret
150 
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
151 
//
152 
// Revision 1.21  2002/08/22 02:18:55  lampret
153 
// Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.
154 
//
155 
// Revision 1.20  2002/08/18 21:59:45  lampret
156 
// Disable SB until it is tested
157 
//
158 
// Revision 1.19  2002/08/18 19:53:08  lampret
159 
// Added store buffer.
160 
//
161 
// Revision 1.18  2002/08/15 06:04:11  lampret
162 
// Fixed Xilinx trace buffer address. REported by Taylor Su.
163 
//
164 
// Revision 1.17  2002/08/12 05:31:44  lampret
165 
// Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section.
166 
//
167 
// Revision 1.16  2002/07/14 22:17:17  lampret
168 
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
169 
//
170 
// Revision 1.15  2002/06/08 16:20:21  lampret
171 
// Added defines for enabling generic FF based memory macro for register file.
172 
//
173 
// Revision 1.14  2002/03/29 16:24:06  lampret
174 
// Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives
175 
//
176 
// Revision 1.13  2002/03/29 15:16:55  lampret
177 
// Some of the warnings fixed.
178 
//
179 
// Revision 1.12  2002/03/28 19:25:42  lampret
180 
// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.
181 
//
182 
// Revision 1.11  2002/03/28 19:13:17  lampret
183 
// Updated defines.
184 
//
185 
// Revision 1.10  2002/03/14 00:30:24  lampret
186 
// Added alternative for critical path in DU.
187 
//
188 
// Revision 1.9  2002/03/11 01:26:26  lampret
189 
// Fixed async loop. Changed multiplier type for ASIC.
190 
//
191 
// Revision 1.8  2002/02/11 04:33:17  lampret
192 
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
193 
//
194 
// Revision 1.7  2002/02/01 19:56:54  lampret
195 
// Fixed combinational loops.
196 
//
197 
// Revision 1.6  2002/01/19 14:10:22  lampret
198 
// Fixed OR1200_XILINX_RAM32X1D.
199 
//
200 
// Revision 1.5  2002/01/18 07:56:00  lampret
201 
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
202 
//
203 
// Revision 1.4  2002/01/14 09:44:12  lampret
204 
// Default ASIC configuration does not sample WB inputs.
205 
//
206 
// Revision 1.3  2002/01/08 00:51:08  lampret
207 
// Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be.
208 
//
209 
// Revision 1.2  2002/01/03 21:23:03  lampret
210 
// Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target.
211 
//
212 
// Revision 1.1  2002/01/03 08:16:15  lampret
213 
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
214 
//
215 
// Revision 1.20  2001/12/04 05:02:36  lampret
216 
// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32
217 
//
218 
// Revision 1.19  2001/11/27 19:46:57  lampret
219 
// Now FPGA and ASIC target are separate.
220 
//
221 
// Revision 1.18  2001/11/23 21:42:31  simons
222 
// Program counter divided to PPC and NPC.
223 
//
224 
// Revision 1.17  2001/11/23 08:38:51  lampret
225 
// Changed DSR/DRR behavior and exception detection.
226 
//
227 
// Revision 1.16  2001/11/20 21:30:38  lampret
228 
// Added OR1200_REGISTERED_INPUTS.
229 
//
230 
// Revision 1.15  2001/11/19 14:29:48  simons
231 
// Cashes disabled.
232 
//
233 
// Revision 1.14  2001/11/13 10:02:21  lampret
234 
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
235 
//
236 
// Revision 1.13  2001/11/12 01:45:40  lampret
237 
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
238 
//
239 
// Revision 1.12  2001/11/10 03:43:57  lampret
240 
// Fixed exceptions.
241 
//
242 
// Revision 1.11  2001/11/02 18:57:14  lampret
243 
// Modified virtual silicon instantiations.
244 
//
245 
// Revision 1.10  2001/10/21 17:57:16  lampret
246 
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
247 
//
248 
// Revision 1.9  2001/10/19 23:28:46  lampret
249 
// Fixed some synthesis warnings. Configured with caches and MMUs.
250 
//
251 
// Revision 1.8  2001/10/14 13:12:09  lampret
252 
// MP3 version.
253 
//
254 
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
255 
// no message
256 
//
257 
// Revision 1.3  2001/08/17 08:01:19  lampret
258 
// IC enable/disable.
259 
//
260 
// Revision 1.2  2001/08/13 03:36:20  lampret
261 
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
262 
//
263 
// Revision 1.1  2001/08/09 13:39:33  lampret
264 
// Major clean-up.
265 
//
266 
// Revision 1.2  2001/07/22 03:31:54  lampret
267 
// Fixed RAM's oen bug. Cache bypass under development.
268 
//
269 
// Revision 1.1  2001/07/20 00:46:03  lampret
270 
// Development version of RTL. Libraries are missing.
271 
//
272 
//
273 
 
274 
//
275 
// Dump VCD
276 
//
277 
//`define OR1200_VCD_DUMP
278 
 
279 
//
280 
// Generate debug messages during simulation
281 
//
282 
//`define OR1200_VERBOSE
283 
 
284 
//  `define OR1200_ASIC
285 
////////////////////////////////////////////////////////
286 
//
287 
// Typical configuration for an ASIC
288 
//
289 
`ifdef OR1200_ASIC
290 
 
291 
//
292 
// Target ASIC memories
293 
//
294 
//`define OR1200_ARTISAN_SSP
295 
//`define OR1200_ARTISAN_SDP
296 
//`define OR1200_ARTISAN_STP
297 
`define OR1200_VIRTUALSILICON_SSP
298 
//`define OR1200_VIRTUALSILICON_STP_T1
299 
//`define OR1200_VIRTUALSILICON_STP_T2
300 
 
301 
//
302 
// Do not implement Data cache
303 
//
304 
//`define OR1200_NO_DC
305 
 
306 
//
307 
// Do not implement Insn cache
308 
//
309 
//`define OR1200_NO_IC
310 
 
311 
//
312 
// Do not implement Data MMU
313 
//
314 
//`define OR1200_NO_DMMU
315 
 
316 
//
317 
// Do not implement Insn MMU
318 
//
319 
//`define OR1200_NO_IMMU
320 
 
321 
//
322 
// Select between ASIC optimized and generic multiplier
323 
//
324 
//`define OR1200_ASIC_MULTP2_32X32
325 
`define OR1200_GENERIC_MULTP2_32X32
326 
 
327 
//
328 
// Size/type of insn/data cache if implemented
329 
//
330 
// `define OR1200_IC_1W_512B
331 
// `define OR1200_IC_1W_4KB
332 
`define OR1200_IC_1W_8KB
333 
// `define OR1200_DC_1W_4KB
334 
`define OR1200_DC_1W_8KB
335 
 
336 
`else
337 
 
338 
 
339 
/////////////////////////////////////////////////////////
340 
//
341 
// Typical configuration for an FPGA
342 
//
343 
 
344 
//
345 
// Target FPGA memories
346 
//
347 
//`define OR1200_ALTERA_LPM
348 
//`define OR1200_XILINX_RAMB16
349 
//`define OR1200_XILINX_RAMB4
350 
//`define OR1200_XILINX_RAM32X1D
351 
//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
352 
 
353 
//
354 
// Do not implement Data cache
355 
//
356 
`define OR1200_NO_DC
357 
 
358 
//
359 
// Do not implement Insn cache
360 
//
361 
`define OR1200_NO_IC
362 
 
363 
//
364 
// Do not implement Data MMU
365 
//
366 
`define OR1200_NO_DMMU
367 
 
368 
//
369 
// Do not implement Insn MMU
370 
//
371 
`define OR1200_NO_IMMU
372 
 
373 
//
374 
// Select between ASIC and generic multiplier
375 
//
376 
// (Generic seems to trigger a bug in the Cadence Ncsim simulator)
377 
//
378 
//`define OR1200_ASIC_MULTP2_32X32
379 
`define OR1200_GENERIC_MULTP2_32X32
380 
 
381 
//
382 
// Size/type of insn/data cache if implemented
383 
// (consider available FPGA memory resources)
384 
//
385 
//`define OR1200_IC_1W_512B
386 
`define OR1200_IC_1W_4KB
387 
//`define OR1200_IC_1W_8KB
388 
`define OR1200_DC_1W_4KB
389 
//`define OR1200_DC_1W_8KB
390 
 
391 
`endif
392 
 
393 
 
394 
//////////////////////////////////////////////////////////
395 
//
396 
// Do not change below unless you know what you are doing
397 
//
398 
 
399 
//
400 
// Enable RAM BIST
401 
//
402 
// At the moment this only works for Virtual Silicon
403 
// single port RAMs. For other RAMs it has not effect.
404 
// Special wrapper for VS RAMs needs to be provided
405 
// with scan flops to facilitate bist scan.
406 
//
407 
//`define OR1200_BIST
408 
 
409 
//
410 
// Register OR1200 WISHBONE outputs
411 
// (must be defined/enabled)
412 
//
413 
`define OR1200_REGISTERED_OUTPUTS
414 
 
415 
//
416 
// Register OR1200 WISHBONE inputs
417 
//
418 
// (must be undefined/disabled)
419 
//
420 
//`define OR1200_REGISTERED_INPUTS
421 
 
422 
//
423 
// Disable bursts if they are not supported by the
424 
// memory subsystem (only affect cache line fill)
425 
//
426 
//`define OR1200_NO_BURSTS
427 
//
428 
 
429 
//
430 
// WISHBONE retry counter range
431 
//
432 
// 2^value range for retry counter. Retry counter
433 
// is activated whenever *wb_rty_i is asserted and
434 
// until retry counter expires, corresponding
435 
// WISHBONE interface is deactivated.
436 
//
437 
// To disable retry counters and *wb_rty_i all together,
438 
// undefine this macro.
439 
//
440 
//`define OR1200_WB_RETRY 7
441 
 
442 
//
443 
// WISHBONE Consecutive Address Burst
444 
//
445 
// This was used prior to WISHBONE B3 specification
446 
// to identify bursts. It is no longer needed but
447 
// remains enabled for compatibility with old designs.
448 
//
449 
// To remove *wb_cab_o ports undefine this macro.
450 
//
451 
`define OR1200_WB_CAB
452 
 
453 
//
454 
// WISHBONE B3 compatible interface
455 
//
456 
// This follows the WISHBONE B3 specification.
457 
// It is not enabled by default because most
458 
// designs still don't use WB b3.
459 
//
460 
// To enable *wb_cti_o/*wb_bte_o ports,
461 
// define this macro.
462 
//
463 
//`define OR1200_WB_B3
464 
 
465 
//
466 
// Enable additional synthesis directives if using
467 
// _Synopsys_ synthesis tool
468 
//
469 
//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
470 
 
471 
//
472 
// Enables default statement in some case blocks
473 
// and disables Synopsys synthesis directive full_case
474 
//
475 
// By default it is enabled. When disabled it
476 
// can increase clock frequency.
477 
//
478 
`define OR1200_CASE_DEFAULT
479 
 
480 
//
481 
// Operand width / register file address width
482 
//
483 
// (DO NOT CHANGE)
484 
//
485 
`define OR1200_OPERAND_WIDTH            32
486 
`define OR1200_REGFILE_ADDR_WIDTH       5
487 
 
488 
//
489 
// l.add/l.addi/l.and and optional l.addc/l.addic
490 
// also set (compare) flag when result of their
491 
// operation equals zero
492 
//
493 
// At the time of writing this, default or32
494 
// C/C++ compiler doesn't generate code that
495 
// would benefit from this optimization.
496 
//
497 
// By default this optimization is disabled to
498 
// save area.
499 
//
500 
//`define OR1200_ADDITIONAL_FLAG_MODIFIERS
501 
 
502 
//
503 
// Implement l.addc/l.addic instructions
504 
//
505 
// By default implementation of l.addc/l.addic
506 
// instructions is enabled in case you need them.
507 
// If you don't use them, then disable implementation
508 
// to save area.
509 
//
510 
`define OR1200_IMPL_ADDC
511 
 
512 
//
513 
// Implement carry bit SR[CY]
514 
//
515 
// By default implementation of SR[CY] is enabled
516 
// to be compliant with the simulator. However
517 
// SR[CY] is explicitly only used by l.addc/l.addic
518 
// instructions and if these two insns are not
519 
// implemented there is not much point having SR[CY].
520 
//
521 
`define OR1200_IMPL_CY
522 
 
523 
//
524 
// Implement optional l.div/l.divu instructions
525 
//
526 
// By default divide instructions are not implemented
527 
// to save area and increase clock frequency. or32 C/C++
528 
// compiler can use soft library for division.
529 
//
530 
// To implement divide, multiplier needs to be implemented.
531 
//
532 
//`define OR1200_IMPL_DIV
533 
 
534 
//
535 
// Implement rotate in the ALU
536 
//
537 
// At the time of writing this, or32
538 
// C/C++ compiler doesn't generate rotate
539 
// instructions. However or32 assembler
540 
// can assemble code that uses rotate insn.
541 
// This means that rotate instructions
542 
// must be used manually inserted.
543 
//
544 
// By default implementation of rotate
545 
// is disabled to save area and increase
546 
// clock frequency.
547 
//
548 
//`define OR1200_IMPL_ALU_ROTATE
549 
 
550 
//
551 
// Type of ALU compare to implement
552 
//
553 
// Try either one to find what yields
554 
// higher clock frequencyin your case.
555 
//
556 
//`define OR1200_IMPL_ALU_COMP1
557 
`define OR1200_IMPL_ALU_COMP2
558 
 
559 
//
560 
// Implement multiplier
561 
//
562 
// By default multiplier is implemented
563 
//
564 
`define OR1200_MULT_IMPLEMENTED
565 
 
566 
//
567 
// Implement multiply-and-accumulate
568 
//
569 
// By default MAC is implemented. To
570 
// implement MAC, multiplier needs to be
571 
// implemented.
572 
//
573 
`define OR1200_MAC_IMPLEMENTED
574 
 
575 
//
576 
// Low power, slower multiplier
577 
//
578 
// Select between low-power (larger) multiplier
579 
// and faster multiplier. The actual difference
580 
// is only AND logic that prevents distribution
581 
// of operands into the multiplier when instruction
582 
// in execution is not multiply instruction
583 
//
584 
//`define OR1200_LOWPWR_MULT
585 
 
586 
//
587 
// Clock ratio RISC clock versus WB clock
588 
//
589 
// If you plan to run WB:RISC clock fixed to 1:1, disable
590 
// both defines
591 
//
592 
// For WB:RISC 1:2 or 1:1, enable OR1200_CLKDIV_2_SUPPORTED
593 
// and use clmode to set ratio
594 
//
595 
// For WB:RISC 1:4, 1:2 or 1:1, enable both defines and use
596 
// clmode to set ratio
597 
//
598 
// `define OR1200_CLKDIV_2_SUPPORTED    -- qaz
599 
//`define OR1200_CLKDIV_4_SUPPORTED
600 
 
601 
//
602 
// Type of register file RAM
603 
//
604 
// Memory macro w/ two ports (see or1200_tpram_32x32.v)
605 
//`define OR1200_RFRAM_TWOPORT
606 
//
607 
// Memory macro dual port (see or1200_dpram_32x32.v)
608 
//`define OR1200_RFRAM_DUALPORT
609 
//
610 
// Generic (flip-flop based) register file (see or1200_rfram_generic.v)
611 
`define OR1200_RFRAM_GENERIC
612 
 
613 
//
614 
// Type of mem2reg aligner to implement.
615 
//
616 
// Once OR1200_IMPL_MEM2REG2 yielded faster
617 
// circuit, however with today tools it will
618 
// most probably give you slower circuit.
619 
//
620 
`define OR1200_IMPL_MEM2REG1
621 
//`define OR1200_IMPL_MEM2REG2
622 
 
623 
//
624 
// ALUOPs
625 
//
626 
`define OR1200_ALUOP_WIDTH      4
627 
`define OR1200_ALUOP_NOP        4'd4
628 
/* Order defined by arith insns that have two source operands both in regs
629 
   (see binutils/include/opcode/or32.h) */
630 
`define OR1200_ALUOP_ADD        4'd0
631 
`define OR1200_ALUOP_ADDC       4'd1
632 
`define OR1200_ALUOP_SUB        4'd2
633 
`define OR1200_ALUOP_AND        4'd3
634 
`define OR1200_ALUOP_OR         4'd4
635 
`define OR1200_ALUOP_XOR        4'd5
636 
`define OR1200_ALUOP_MUL        4'd6
637 
`define OR1200_ALUOP_CUST5      4'd7
638 
`define OR1200_ALUOP_SHROT      4'd8
639 
`define OR1200_ALUOP_DIV        4'd9
640 
`define OR1200_ALUOP_DIVU       4'd10
641 
/* Order not specifically defined. */
642 
`define OR1200_ALUOP_IMM        4'd11
643 
`define OR1200_ALUOP_MOVHI      4'd12
644 
`define OR1200_ALUOP_COMP       4'd13
645 
`define OR1200_ALUOP_MTSR       4'd14
646 
`define OR1200_ALUOP_MFSR       4'd15
647 
`define OR1200_ALUOP_CMOV 4'd14
648 
`define OR1200_ALUOP_FF1  4'd15
649 
//
650 
// MACOPs
651 
//
652 
`define OR1200_MACOP_WIDTH      2
653 
`define OR1200_MACOP_NOP        2'b00
654 
`define OR1200_MACOP_MAC        2'b01
655 
`define OR1200_MACOP_MSB        2'b10
656 
 
657 
//
658 
// Shift/rotate ops
659 
//
660 
`define OR1200_SHROTOP_WIDTH    2
661 
`define OR1200_SHROTOP_NOP      2'd0
662 
`define OR1200_SHROTOP_SLL      2'd0
663 
`define OR1200_SHROTOP_SRL      2'd1
664 
`define OR1200_SHROTOP_SRA      2'd2
665 
`define OR1200_SHROTOP_ROR      2'd3
666 
 
667 
// Execution cycles per instruction
668 
`define OR1200_MULTICYCLE_WIDTH 2
669 
`define OR1200_ONE_CYCLE                2'd0
670 
`define OR1200_TWO_CYCLES               2'd1
671 
 
672 
// Operand MUX selects
673 
`define OR1200_SEL_WIDTH                2
674 
`define OR1200_SEL_RF                   2'd0
675 
`define OR1200_SEL_IMM                  2'd1
676 
`define OR1200_SEL_EX_FORW              2'd2
677 
`define OR1200_SEL_WB_FORW              2'd3
678 
 
679 
//
680 
// BRANCHOPs
681 
//
682 
`define OR1200_BRANCHOP_WIDTH           3
683 
`define OR1200_BRANCHOP_NOP             3'd0
684 
`define OR1200_BRANCHOP_J               3'd1
685 
`define OR1200_BRANCHOP_JR              3'd2
686 
`define OR1200_BRANCHOP_BAL             3'd3
687 
`define OR1200_BRANCHOP_BF              3'd4
688 
`define OR1200_BRANCHOP_BNF             3'd5
689 
`define OR1200_BRANCHOP_RFE             3'd6
690 
 
691 
//
692 
// LSUOPs
693 
//
694 
// Bit 0: sign extend
695 
// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword
696 
// Bit 3: 0 load, 1 store
697 
`define OR1200_LSUOP_WIDTH              4
698 
`define OR1200_LSUOP_NOP                4'b0000
699 
`define OR1200_LSUOP_LBZ                4'b0010
700 
`define OR1200_LSUOP_LBS                4'b0011
701 
`define OR1200_LSUOP_LHZ                4'b0100
702 
`define OR1200_LSUOP_LHS                4'b0101
703 
`define OR1200_LSUOP_LWZ                4'b0110
704 
`define OR1200_LSUOP_LWS                4'b0111
705 
`define OR1200_LSUOP_LD         4'b0001
706 
`define OR1200_LSUOP_SD         4'b1000
707 
`define OR1200_LSUOP_SB         4'b1010
708 
`define OR1200_LSUOP_SH         4'b1100
709 
`define OR1200_LSUOP_SW         4'b1110
710 
 
711 
// FETCHOPs
712 
`define OR1200_FETCHOP_WIDTH            1
713 
`define OR1200_FETCHOP_NOP              1'b0
714 
`define OR1200_FETCHOP_LW               1'b1
715 
 
716 
//
717 
// Register File Write-Back OPs
718 
//
719 
// Bit 0: register file write enable
720 
// Bits 2-1: write-back mux selects
721 
`define OR1200_RFWBOP_WIDTH             3
722 
`define OR1200_RFWBOP_NOP               3'b000
723 
`define OR1200_RFWBOP_ALU               3'b001
724 
`define OR1200_RFWBOP_LSU               3'b011
725 
`define OR1200_RFWBOP_SPRS              3'b101
726 
`define OR1200_RFWBOP_LR                3'b111
727 
 
728 
// Compare instructions
729 
`define OR1200_COP_SFEQ       3'b000
730 
`define OR1200_COP_SFNE       3'b001
731 
`define OR1200_COP_SFGT       3'b010
732 
`define OR1200_COP_SFGE       3'b011
733 
`define OR1200_COP_SFLT       3'b100
734 
`define OR1200_COP_SFLE       3'b101
735 
`define OR1200_COP_X          3'b111
736 
`define OR1200_SIGNED_COMPARE 'd3
737 
`define OR1200_COMPOP_WIDTH     4
738 
 
739 
//
740 
// TAGs for instruction bus
741 
//
742 
`define OR1200_ITAG_IDLE        4'h0    // idle bus
743 
`define OR1200_ITAG_NI          4'h1    // normal insn
744 
`define OR1200_ITAG_BE          4'hb    // Bus error exception
745 
`define OR1200_ITAG_PE          4'hc    // Page fault exception
746 
`define OR1200_ITAG_TE          4'hd    // TLB miss exception
747 
 
748 
//
749 
// TAGs for data bus
750 
//
751 
`define OR1200_DTAG_IDLE        4'h0    // idle bus
752 
`define OR1200_DTAG_ND          4'h1    // normal data
753 
`define OR1200_DTAG_AE          4'ha    // Alignment exception
754 
`define OR1200_DTAG_BE          4'hb    // Bus error exception
755 
`define OR1200_DTAG_PE          4'hc    // Page fault exception
756 
`define OR1200_DTAG_TE          4'hd    // TLB miss exception
757 
 
758 
 
759 
//////////////////////////////////////////////
760 
//
761 
// ORBIS32 ISA specifics
762 
//
763 
 
764 
// SHROT_OP position in machine word
765 
`define OR1200_SHROTOP_POS              7:6
766 
 
767 
// ALU instructions multicycle field in machine word
768 
`define OR1200_ALUMCYC_POS              9:8
769 
 
770 
//
771 
// Instruction opcode groups (basic)
772 
//
773 
`define OR1200_OR32_J                 6'b000000
774 
`define OR1200_OR32_JAL               6'b000001
775 
`define OR1200_OR32_BNF               6'b000011
776 
`define OR1200_OR32_BF                6'b000100
777 
`define OR1200_OR32_NOP               6'b000101
778 
`define OR1200_OR32_MOVHI             6'b000110
779 
`define OR1200_OR32_XSYNC             6'b001000
780 
`define OR1200_OR32_RFE               6'b001001
781 
/* */
782 
`define OR1200_OR32_JR                6'b010001
783 
`define OR1200_OR32_JALR              6'b010010
784 
`define OR1200_OR32_MACI              6'b010011
785 
/* */
786 
`define OR1200_OR32_LWZ               6'b100001
787 
`define OR1200_OR32_LBZ               6'b100011
788 
`define OR1200_OR32_LBS               6'b100100
789 
`define OR1200_OR32_LHZ               6'b100101
790 
`define OR1200_OR32_LHS               6'b100110
791 
`define OR1200_OR32_ADDI              6'b100111
792 
`define OR1200_OR32_ADDIC             6'b101000
793 
`define OR1200_OR32_ANDI              6'b101001
794 
`define OR1200_OR32_ORI               6'b101010
795 
`define OR1200_OR32_XORI              6'b101011
796 
`define OR1200_OR32_MULI              6'b101100
797 
`define OR1200_OR32_MFSPR             6'b101101
798 
`define OR1200_OR32_SH_ROTI           6'b101110
799 
`define OR1200_OR32_SFXXI             6'b101111
800 
/* */
801 
`define OR1200_OR32_MTSPR             6'b110000
802 
`define OR1200_OR32_MACMSB            6'b110001
803 
/* */
804 
`define OR1200_OR32_SW                6'b110101
805 
`define OR1200_OR32_SB                6'b110110
806 
`define OR1200_OR32_SH                6'b110111
807 
`define OR1200_OR32_ALU               6'b111000
808 
`define OR1200_OR32_SFXX              6'b111001
809 
//`define OR1200_OR32_CUST5             6'b111100
810 
 
811 
 
812 
/////////////////////////////////////////////////////
813 
//
814 
// Exceptions
815 
//
816 
 
817 
//
818 
// Exception vectors per OR1K architecture:
819 
// 0xPPPPP100 - reset
820 
// 0xPPPPP200 - bus error
821 
// ... etc
822 
// where P represents exception prefix.
823 
//
824 
// Exception vectors can be customized as per
825 
// the following formula:
826 
// 0xPPPPPNVV - exception N
827 
//
828 
// P represents exception prefix
829 
// N represents exception N
830 
// VV represents length of the individual vector space,
831 
//   usually it is 8 bits wide and starts with all bits zero
832 
//
833 
 
834 
//
835 
// PPPPP and VV parts
836 
//
837 
// Sum of these two defines needs to be 28
838 
//
839 
`define OR1200_EXCEPT_EPH0_P 20'h00000
840 
`define OR1200_EXCEPT_EPH1_P 20'hF0000
841 
`define OR1200_EXCEPT_V            8'h00
842 
 
843 
//
844 
// N part width
845 
//
846 
`define OR1200_EXCEPT_WIDTH 4
847 
 
848 
//
849 
// Definition of exception vectors
850 
//
851 
// To avoid implementation of a certain exception,
852 
// simply comment out corresponding line
853 
//
854 
`define OR1200_EXCEPT_UNUSED            `OR1200_EXCEPT_WIDTH'hf
855 
`define OR1200_EXCEPT_TRAP              `OR1200_EXCEPT_WIDTH'he
856 
`define OR1200_EXCEPT_BREAK             `OR1200_EXCEPT_WIDTH'hd
857 
`define OR1200_EXCEPT_SYSCALL           `OR1200_EXCEPT_WIDTH'hc
858 
`define OR1200_EXCEPT_RANGE             `OR1200_EXCEPT_WIDTH'hb
859 
`define OR1200_EXCEPT_ITLBMISS          `OR1200_EXCEPT_WIDTH'ha
860 
`define OR1200_EXCEPT_DTLBMISS          `OR1200_EXCEPT_WIDTH'h9
861 
`define OR1200_EXCEPT_INT               `OR1200_EXCEPT_WIDTH'h8
862 
`define OR1200_EXCEPT_ILLEGAL           `OR1200_EXCEPT_WIDTH'h7
863 
`define OR1200_EXCEPT_ALIGN             `OR1200_EXCEPT_WIDTH'h6
864 
`define OR1200_EXCEPT_TICK              `OR1200_EXCEPT_WIDTH'h5
865 
`define OR1200_EXCEPT_IPF               `OR1200_EXCEPT_WIDTH'h4
866 
`define OR1200_EXCEPT_DPF               `OR1200_EXCEPT_WIDTH'h3
867 
`define OR1200_EXCEPT_BUSERR            `OR1200_EXCEPT_WIDTH'h2
868 
`define OR1200_EXCEPT_RESET             `OR1200_EXCEPT_WIDTH'h1
869 
`define OR1200_EXCEPT_NONE              `OR1200_EXCEPT_WIDTH'h0
870 
 
871 
 
872 
/////////////////////////////////////////////////////
873 
//
874 
// SPR groups
875 
//
876 
 
877 
// Bits that define the group
878 
`define OR1200_SPR_GROUP_BITS   15:11
879 
 
880 
// Width of the group bits
881 
`define OR1200_SPR_GROUP_WIDTH  5
882 
 
883 
// Bits that define offset inside the group
884 
`define OR1200_SPR_OFS_BITS 10:0
885 
 
886 
// List of groups
887 
`define OR1200_SPR_GROUP_SYS    5'd00
888 
`define OR1200_SPR_GROUP_DMMU   5'd01
889 
`define OR1200_SPR_GROUP_IMMU   5'd02
890 
`define OR1200_SPR_GROUP_DC     5'd03
891 
`define OR1200_SPR_GROUP_IC     5'd04
892 
`define OR1200_SPR_GROUP_MAC    5'd05
893 
`define OR1200_SPR_GROUP_DU     5'd06
894 
`define OR1200_SPR_GROUP_PM     5'd08
895 
`define OR1200_SPR_GROUP_PIC    5'd09
896 
`define OR1200_SPR_GROUP_TT     5'd10
897 
 
898 
 
899 
/////////////////////////////////////////////////////
900 
//
901 
// System group
902 
//
903 
 
904 
//
905 
// System registers
906 
//
907 
`define OR1200_SPR_CFGR         7'd0
908 
`define OR1200_SPR_RF           6'd32   // 1024 >> 5
909 
`define OR1200_SPR_NPC          11'd16
910 
`define OR1200_SPR_SR           11'd17
911 
`define OR1200_SPR_PPC          11'd18
912 
`define OR1200_SPR_EPCR         11'd32
913 
`define OR1200_SPR_EEAR         11'd48
914 
`define OR1200_SPR_ESR          11'd64
915 
 
916 
//
917 
// SR bits
918 
//
919 
`define OR1200_SR_WIDTH 16
920 
`define OR1200_SR_SM   0
921 
`define OR1200_SR_TEE  1
922 
`define OR1200_SR_IEE  2
923 
`define OR1200_SR_DCE  3
924 
`define OR1200_SR_ICE  4
925 
`define OR1200_SR_DME  5
926 
`define OR1200_SR_IME  6
927 
`define OR1200_SR_LEE  7
928 
`define OR1200_SR_CE   8
929 
`define OR1200_SR_F    9
930 
`define OR1200_SR_CY   10       // Unused
931 
`define OR1200_SR_OV   11       // Unused
932 
`define OR1200_SR_OVE  12       // Unused
933 
`define OR1200_SR_DSX  13       // Unused
934 
`define OR1200_SR_EPH  14
935 
`define OR1200_SR_FO   15
936 
`define OR1200_SR_CID  31:28    // Unimplemented
937 
 
938 
//
939 
// Bits that define offset inside the group
940 
//
941 
`define OR1200_SPROFS_BITS 10:0
942 
 
943 
//
944 
// Default Exception Prefix
945 
//
946 
// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)
947 
// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)
948 
//
949 
`define OR1200_SR_EPH_DEF       1'b0
950 
 
951 
/////////////////////////////////////////////////////
952 
//
953 
// Power Management (PM)
954 
//
955 
 
956 
// Define it if you want PM implemented
957 
// `define OR1200_PM_IMPLEMENTED    -- qaz
958 
 
959 
// Bit positions inside PMR (don't change)
960 
`define OR1200_PM_PMR_SDF 3:0
961 
`define OR1200_PM_PMR_DME 4
962 
`define OR1200_PM_PMR_SME 5
963 
`define OR1200_PM_PMR_DCGE 6
964 
`define OR1200_PM_PMR_UNUSED 31:7
965 
 
966 
// PMR offset inside PM group of registers
967 
`define OR1200_PM_OFS_PMR 11'b0
968 
 
969 
// PM group
970 
`define OR1200_SPRGRP_PM 5'd8
971 
 
972 
// Define if PMR can be read/written at any address inside PM group
973 
`define OR1200_PM_PARTIAL_DECODING
974 
 
975 
// Define if reading PMR is allowed
976 
`define OR1200_PM_READREGS
977 
 
978 
// Define if unused PMR bits should be zero
979 
`define OR1200_PM_UNUSED_ZERO
980 
 
981 
 
982 
/////////////////////////////////////////////////////
983 
//
984 
// Debug Unit (DU)
985 
//
986 
 
987 
// Define it if you want DU implemented
988 
// `define OR1200_DU_IMPLEMENTED    -- qaz
989 
 
990 
//
991 
// Define if you want HW Breakpoints
992 
// (if HW breakpoints are not implemented
993 
// only default software trapping is
994 
// possible with l.trap insn - this is
995 
// however already enough for use
996 
// with or32 gdb)
997 
//
998 
//`define OR1200_DU_HWBKPTS
999 
 
1000 
// Number of DVR/DCR pairs if HW breakpoints enabled
1001 
`define OR1200_DU_DVRDCR_PAIRS 8
1002 
 
1003 
// Define if you want trace buffer
1004 
//`define OR1200_DU_TB_IMPLEMENTED
1005 
 
1006 
//
1007 
// Address offsets of DU registers inside DU group
1008 
//
1009 
// To not implement a register, doq not define its address
1010 
//
1011 
`ifdef OR1200_DU_HWBKPTS
1012 
`define OR1200_DU_DVR0          11'd0
1013 
`define OR1200_DU_DVR1          11'd1
1014 
`define OR1200_DU_DVR2          11'd2
1015 
`define OR1200_DU_DVR3          11'd3
1016 
`define OR1200_DU_DVR4          11'd4
1017 
`define OR1200_DU_DVR5          11'd5
1018 
`define OR1200_DU_DVR6          11'd6
1019 
`define OR1200_DU_DVR7          11'd7
1020 
`define OR1200_DU_DCR0          11'd8
1021 
`define OR1200_DU_DCR1          11'd9
1022 
`define OR1200_DU_DCR2          11'd10
1023 
`define OR1200_DU_DCR3          11'd11
1024 
`define OR1200_DU_DCR4          11'd12
1025 
`define OR1200_DU_DCR5          11'd13
1026 
`define OR1200_DU_DCR6          11'd14
1027 
`define OR1200_DU_DCR7          11'd15
1028 
`endif
1029 
`define OR1200_DU_DMR1          11'd16
1030 
`ifdef OR1200_DU_HWBKPTS
1031 
`define OR1200_DU_DMR2          11'd17
1032 
`define OR1200_DU_DWCR0         11'd18
1033 
`define OR1200_DU_DWCR1         11'd19
1034 
`endif
1035 
`define OR1200_DU_DSR           11'd20
1036 
`define OR1200_DU_DRR           11'd21
1037 
`ifdef OR1200_DU_TB_IMPLEMENTED
1038 
`define OR1200_DU_TBADR         11'h0ff
1039 
`define OR1200_DU_TBIA          11'h1xx
1040 
`define OR1200_DU_TBIM          11'h2xx
1041 
`define OR1200_DU_TBAR          11'h3xx
1042 
`define OR1200_DU_TBTS          11'h4xx
1043 
`endif
1044 
 
1045 
// Position of offset bits inside SPR address
1046 
`define OR1200_DUOFS_BITS       10:0
1047 
 
1048 
// DCR bits
1049 
`define OR1200_DU_DCR_DP        0
1050 
`define OR1200_DU_DCR_CC        3:1
1051 
`define OR1200_DU_DCR_SC        4
1052 
`define OR1200_DU_DCR_CT        7:5
1053 
 
1054 
// DMR1 bits
1055 
`define OR1200_DU_DMR1_CW0      1:0
1056 
`define OR1200_DU_DMR1_CW1      3:2
1057 
`define OR1200_DU_DMR1_CW2      5:4
1058 
`define OR1200_DU_DMR1_CW3      7:6
1059 
`define OR1200_DU_DMR1_CW4      9:8
1060 
`define OR1200_DU_DMR1_CW5      11:10
1061 
`define OR1200_DU_DMR1_CW6      13:12
1062 
`define OR1200_DU_DMR1_CW7      15:14
1063 
`define OR1200_DU_DMR1_CW8      17:16
1064 
`define OR1200_DU_DMR1_CW9      19:18
1065 
`define OR1200_DU_DMR1_CW10     21:20
1066 
`define OR1200_DU_DMR1_ST       22
1067 
`define OR1200_DU_DMR1_BT       23
1068 
`define OR1200_DU_DMR1_DXFW     24
1069 
`define OR1200_DU_DMR1_ETE      25
1070 
 
1071 
// DMR2 bits
1072 
`define OR1200_DU_DMR2_WCE0     0
1073 
`define OR1200_DU_DMR2_WCE1     1
1074 
`define OR1200_DU_DMR2_AWTC     12:2
1075 
`define OR1200_DU_DMR2_WGB      23:13
1076 
 
1077 
// DWCR bits
1078 
`define OR1200_DU_DWCR_COUNT    15:0
1079 
`define OR1200_DU_DWCR_MATCH    31:16
1080 
 
1081 
// DSR bits
1082 
`define OR1200_DU_DSR_WIDTH     14
1083 
`define OR1200_DU_DSR_RSTE      0
1084 
`define OR1200_DU_DSR_BUSEE     1
1085 
`define OR1200_DU_DSR_DPFE      2
1086 
`define OR1200_DU_DSR_IPFE      3
1087 
`define OR1200_DU_DSR_TTE       4
1088 
`define OR1200_DU_DSR_AE        5
1089 
`define OR1200_DU_DSR_IIE       6
1090 
`define OR1200_DU_DSR_IE        7
1091 
`define OR1200_DU_DSR_DME       8
1092 
`define OR1200_DU_DSR_IME       9
1093 
`define OR1200_DU_DSR_RE        10
1094 
`define OR1200_DU_DSR_SCE       11
1095 
`define OR1200_DU_DSR_BE        12
1096 
`define OR1200_DU_DSR_TE        13
1097 
 
1098 
// DRR bits
1099 
`define OR1200_DU_DRR_RSTE      0
1100 
`define OR1200_DU_DRR_BUSEE     1
1101 
`define OR1200_DU_DRR_DPFE      2
1102 
`define OR1200_DU_DRR_IPFE      3
1103 
`define OR1200_DU_DRR_TTE       4
1104 
`define OR1200_DU_DRR_AE        5
1105 
`define OR1200_DU_DRR_IIE       6
1106 
`define OR1200_DU_DRR_IE        7
1107 
`define OR1200_DU_DRR_DME       8
1108 
`define OR1200_DU_DRR_IME       9
1109 
`define OR1200_DU_DRR_RE        10
1110 
`define OR1200_DU_DRR_SCE       11
1111 
`define OR1200_DU_DRR_BE        12
1112 
`define OR1200_DU_DRR_TE        13
1113 
 
1114 
// Define if reading DU regs is allowed
1115 
`define OR1200_DU_READREGS
1116 
 
1117 
// Define if unused DU registers bits should be zero
1118 
`define OR1200_DU_UNUSED_ZERO
1119 
 
1120 
// Define if IF/LSU status is not needed by devel i/f
1121 
`define OR1200_DU_STATUS_UNIMPLEMENTED
1122 
 
1123 
/////////////////////////////////////////////////////
1124 
//
1125 
// Programmable Interrupt Controller (PIC)
1126 
//
1127 
 
1128 
// Define it if you want PIC implemented
1129 
// `define OR1200_PIC_IMPLEMENTED   -- qaz
1130 
 
1131 
// Define number of interrupt inputs (2-31)
1132 
`define OR1200_PIC_INTS 20
1133 
 
1134 
// Address offsets of PIC registers inside PIC group
1135 
`define OR1200_PIC_OFS_PICMR 2'd0
1136 
`define OR1200_PIC_OFS_PICSR 2'd2
1137 
 
1138 
// Position of offset bits inside SPR address
1139 
`define OR1200_PICOFS_BITS 1:0
1140 
 
1141 
// Define if you want these PIC registers to be implemented
1142 
`define OR1200_PIC_PICMR
1143 
`define OR1200_PIC_PICSR
1144 
 
1145 
// Define if reading PIC registers is allowed
1146 
`define OR1200_PIC_READREGS
1147 
 
1148 
// Define if unused PIC register bits should be zero
1149 
`define OR1200_PIC_UNUSED_ZERO
1150 
 
1151 
 
1152 
/////////////////////////////////////////////////////
1153 
//
1154 
// Tick Timer (TT)
1155 
//
1156 
 
1157 
// Define it if you want TT implemented
1158 
// `define OR1200_TT_IMPLEMENTED    -- qaz
1159 24 qaztronic 
`define OR1200_TT_IMPLEMENTED
1160 21 qaztronic 
 
1161 
// Address offsets of TT registers inside TT group
1162 
`define OR1200_TT_OFS_TTMR 1'd0
1163 
`define OR1200_TT_OFS_TTCR 1'd1
1164 
 
1165 
// Position of offset bits inside SPR group
1166 
`define OR1200_TTOFS_BITS 0
1167 
 
1168 
// Define if you want these TT registers to be implemented
1169 
`define OR1200_TT_TTMR
1170 
`define OR1200_TT_TTCR
1171 
 
1172 
// TTMR bits
1173 
`define OR1200_TT_TTMR_TP 27:0
1174 
`define OR1200_TT_TTMR_IP 28
1175 
`define OR1200_TT_TTMR_IE 29
1176 
`define OR1200_TT_TTMR_M 31:30
1177 
 
1178 
// Define if reading TT registers is allowed
1179 
`define OR1200_TT_READREGS
1180 
 
1181 
 
1182 
//////////////////////////////////////////////
1183 
//
1184 
// MAC
1185 
//
1186 
`define OR1200_MAC_ADDR         0        // MACLO 0xxxxxxxx1, MACHI 0xxxxxxxx0
1187 
`define OR1200_MAC_SPR_WE               // Define if MACLO/MACHI are SPR writable
1188 
 
1189 
//
1190 
// Shift {MACHI,MACLO} into destination register when executing l.macrc
1191 
//
1192 
// According to architecture manual there is no shift, so default value is 0.
1193 
//
1194 
// However the implementation has deviated in this from the arch manual and had hard coded shift by 28 bits which
1195 
// is a useful optimization for MP3 decoding (if using libmad fixed point library). Shifts are no longer
1196 
// default setup, but if you need to remain backward compatible, define your shift bits, which were normally
1197 
// dest_GPR = {MACHI,MACLO}[59:28]
1198 
`define OR1200_MAC_SHIFTBY      0        // 0 = According to arch manual, 28 = obsolete backward compatibility
1199 
 
1200 
 
1201 
//////////////////////////////////////////////
1202 
//
1203 
// Data MMU (DMMU)
1204 
//
1205 
 
1206 
//
1207 
// Address that selects between TLB TR and MR
1208 
//
1209 
`define OR1200_DTLB_TM_ADDR     7
1210 
 
1211 
//
1212 
// DTLBMR fields
1213 
//
1214 
`define OR1200_DTLBMR_V_BITS    0
1215 
`define OR1200_DTLBMR_CID_BITS  4:1
1216 
`define OR1200_DTLBMR_RES_BITS  11:5
1217 
`define OR1200_DTLBMR_VPN_BITS  31:13
1218 
 
1219 
//
1220 
// DTLBTR fields
1221 
//
1222 
`define OR1200_DTLBTR_CC_BITS   0
1223 
`define OR1200_DTLBTR_CI_BITS   1
1224 
`define OR1200_DTLBTR_WBC_BITS  2
1225 
`define OR1200_DTLBTR_WOM_BITS  3
1226 
`define OR1200_DTLBTR_A_BITS    4
1227 
`define OR1200_DTLBTR_D_BITS    5
1228 
`define OR1200_DTLBTR_URE_BITS  6
1229 
`define OR1200_DTLBTR_UWE_BITS  7
1230 
`define OR1200_DTLBTR_SRE_BITS  8
1231 
`define OR1200_DTLBTR_SWE_BITS  9
1232 
`define OR1200_DTLBTR_RES_BITS  11:10
1233 
`define OR1200_DTLBTR_PPN_BITS  31:13
1234 
 
1235 
//
1236 
// DTLB configuration
1237 
//
1238 
`define OR1200_DMMU_PS          13                                      // 13 for 8KB page size
1239 
`define OR1200_DTLB_INDXW       6                                       // 6 for 64 entry DTLB  7 for 128 entries
1240 
`define OR1200_DTLB_INDXL       `OR1200_DMMU_PS                         // 13                   13
1241 
`define OR1200_DTLB_INDXH       `OR1200_DMMU_PS+`OR1200_DTLB_INDXW-1    // 18                   19
1242 
`define OR1200_DTLB_INDX        `OR1200_DTLB_INDXH:`OR1200_DTLB_INDXL   // 18:13                19:13
1243 
`define OR1200_DTLB_TAGW        32-`OR1200_DTLB_INDXW-`OR1200_DMMU_PS   // 13                   12
1244 
`define OR1200_DTLB_TAGL        `OR1200_DTLB_INDXH+1                    // 19                   20
1245 
`define OR1200_DTLB_TAG         31:`OR1200_DTLB_TAGL                    // 31:19                31:20
1246 
`define OR1200_DTLBMRW          `OR1200_DTLB_TAGW+1                     // +1 because of V bit
1247 
`define OR1200_DTLBTRW          32-`OR1200_DMMU_PS+5                    // +5 because of protection bits and CI
1248 
 
1249 
//
1250 
// Cache inhibit while DMMU is not enabled/implemented
1251 
//
1252 
// cache inhibited 0GB-4GB              1'b1
1253 
// cache inhibited 0GB-2GB              !dcpu_adr_i[31]
1254 
// cache inhibited 0GB-1GB 2GB-3GB      !dcpu_adr_i[30]
1255 
// cache inhibited 1GB-2GB 3GB-4GB      dcpu_adr_i[30]
1256 
// cache inhibited 2GB-4GB (default)    dcpu_adr_i[31]
1257 
// cached 0GB-4GB                       1'b0
1258 
//
1259 
`define OR1200_DMMU_CI                  dcpu_adr_i[31]
1260 
 
1261 
 
1262 
//////////////////////////////////////////////
1263 
//
1264 
// Insn MMU (IMMU)
1265 
//
1266 
 
1267 
//
1268 
// Address that selects between TLB TR and MR
1269 
//
1270 
`define OR1200_ITLB_TM_ADDR     7
1271 
 
1272 
//
1273 
// ITLBMR fields
1274 
//
1275 
`define OR1200_ITLBMR_V_BITS    0
1276 
`define OR1200_ITLBMR_CID_BITS  4:1
1277 
`define OR1200_ITLBMR_RES_BITS  11:5
1278 
`define OR1200_ITLBMR_VPN_BITS  31:13
1279 
 
1280 
//
1281 
// ITLBTR fields
1282 
//
1283 
`define OR1200_ITLBTR_CC_BITS   0
1284 
`define OR1200_ITLBTR_CI_BITS   1
1285 
`define OR1200_ITLBTR_WBC_BITS  2
1286 
`define OR1200_ITLBTR_WOM_BITS  3
1287 
`define OR1200_ITLBTR_A_BITS    4
1288 
`define OR1200_ITLBTR_D_BITS    5
1289 
`define OR1200_ITLBTR_SXE_BITS  6
1290 
`define OR1200_ITLBTR_UXE_BITS  7
1291 
`define OR1200_ITLBTR_RES_BITS  11:8
1292 
`define OR1200_ITLBTR_PPN_BITS  31:13
1293 
 
1294 
//
1295 
// ITLB configuration
1296 
//
1297 
`define OR1200_IMMU_PS          13                                      // 13 for 8KB page size
1298 
`define OR1200_ITLB_INDXW       6                                       // 6 for 64 entry ITLB  7 for 128 entries
1299 
`define OR1200_ITLB_INDXL       `OR1200_IMMU_PS                         // 13                   13
1300 
`define OR1200_ITLB_INDXH       `OR1200_IMMU_PS+`OR1200_ITLB_INDXW-1    // 18                   19
1301 
`define OR1200_ITLB_INDX        `OR1200_ITLB_INDXH:`OR1200_ITLB_INDXL   // 18:13                19:13
1302 
`define OR1200_ITLB_TAGW        32-`OR1200_ITLB_INDXW-`OR1200_IMMU_PS   // 13                   12
1303 
`define OR1200_ITLB_TAGL        `OR1200_ITLB_INDXH+1                    // 19                   20
1304 
`define OR1200_ITLB_TAG         31:`OR1200_ITLB_TAGL                    // 31:19                31:20
1305 
`define OR1200_ITLBMRW          `OR1200_ITLB_TAGW+1                     // +1 because of V bit
1306 
`define OR1200_ITLBTRW          32-`OR1200_IMMU_PS+3                    // +3 because of protection bits and CI
1307 
 
1308 
//
1309 
// Cache inhibit while IMMU is not enabled/implemented
1310 
// Note: all combinations that use icpu_adr_i cause async loop
1311 
//
1312 
// cache inhibited 0GB-4GB              1'b1
1313 
// cache inhibited 0GB-2GB              !icpu_adr_i[31]
1314 
// cache inhibited 0GB-1GB 2GB-3GB      !icpu_adr_i[30]
1315 
// cache inhibited 1GB-2GB 3GB-4GB      icpu_adr_i[30]
1316 
// cache inhibited 2GB-4GB (default)    icpu_adr_i[31]
1317 
// cached 0GB-4GB                       1'b0
1318 
//
1319 
`define OR1200_IMMU_CI                  1'b0
1320 
 
1321 
 
1322 
/////////////////////////////////////////////////
1323 
//
1324 
// Insn cache (IC)
1325 
//
1326 
 
1327 
// 3 for 8 bytes, 4 for 16 bytes etc
1328 
`define OR1200_ICLS             4
1329 
 
1330 
//
1331 
// IC configurations
1332 
//
1333 
`ifdef OR1200_IC_1W_512B
1334 
`define OR1200_ICSIZE   9     // 512
1335 
`define OR1200_ICINDX   `OR1200_ICSIZE-2 // 7
1336 
`define OR1200_ICINDXH  `OR1200_ICSIZE-1 // 8
1337 
`define OR1200_ICTAGL   `OR1200_ICINDXH+1 // 9
1338 
`define OR1200_ICTAG    `OR1200_ICSIZE-`OR1200_ICLS // 5
1339 
`define OR1200_ICTAG_W  24
1340 
`endif
1341 
`ifdef OR1200_IC_1W_4KB
1342 
`define OR1200_ICSIZE                   12                      // 4096
1343 
`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 10
1344 
`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 11
1345 
`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 12
1346 
`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS     // 8
1347 
`define OR1200_ICTAG_W                  21
1348 
`endif
1349 
`ifdef OR1200_IC_1W_8KB
1350 
`define OR1200_ICSIZE                   13                      // 8192
1351 
`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 11
1352 
`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 12
1353 
`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 13
1354 
`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS     // 9
1355 
`define OR1200_ICTAG_W                  20
1356 
`endif
1357 
 
1358 
 
1359 
/////////////////////////////////////////////////
1360 
//
1361 
// Data cache (DC)
1362 
//
1363 
 
1364 
// 3 for 8 bytes, 4 for 16 bytes etc
1365 
`define OR1200_DCLS             4
1366 
 
1367 
// Define to perform store refill (potential performance penalty)
1368 
// `define OR1200_DC_STORE_REFILL
1369 
 
1370 
//
1371 
// DC configurations
1372 
//
1373 
`ifdef OR1200_DC_1W_4KB
1374 
`define OR1200_DCSIZE                   12                      // 4096
1375 
`define OR1200_DCINDX                   `OR1200_DCSIZE-2        // 10
1376 
`define OR1200_DCINDXH                  `OR1200_DCSIZE-1        // 11
1377 
`define OR1200_DCTAGL                   `OR1200_DCINDXH+1       // 12
1378 
`define OR1200_DCTAG                    `OR1200_DCSIZE-`OR1200_DCLS     // 8
1379 
`define OR1200_DCTAG_W                  21
1380 
`endif
1381 
`ifdef OR1200_DC_1W_8KB
1382 
`define OR1200_DCSIZE                   13                      // 8192
1383 
`define OR1200_DCINDX                   `OR1200_DCSIZE-2        // 11
1384 
`define OR1200_DCINDXH                  `OR1200_DCSIZE-1        // 12
1385 
`define OR1200_DCTAGL                   `OR1200_DCINDXH+1       // 13
1386 
`define OR1200_DCTAG                    `OR1200_DCSIZE-`OR1200_DCLS     // 9
1387 
`define OR1200_DCTAG_W                  20
1388 
`endif
1389 
 
1390 
/////////////////////////////////////////////////
1391 
//
1392 
// Store buffer (SB)
1393 
//
1394 
 
1395 
//
1396 
// Store buffer
1397 
//
1398 
// It will improve performance by "caching" CPU stores
1399 
// using store buffer. This is most important for function
1400 
// prologues because DC can only work in write though mode
1401 
// and all stores would have to complete external WB writes
1402 
// to memory.
1403 
// Store buffer is between DC and data BIU.
1404 
// All stores will be stored into store buffer and immediately
1405 
// completed by the CPU, even though actual external writes
1406 
// will be performed later. As a consequence store buffer masks
1407 
// all data bus errors related to stores (data bus errors
1408 
// related to loads are delivered normally).
1409 
// All pending CPU loads will wait until store buffer is empty to
1410 
// ensure strict memory model. Right now this is necessary because
1411 
// we don't make destinction between cached and cache inhibited
1412 
// address space, so we simply empty store buffer until loads
1413 
// can begin.
1414 
//
1415 
// It makes design a bit bigger, depending what is the number of
1416 
// entries in SB FIFO. Number of entries can be changed further
1417 
// down.
1418 
//
1419 
//`define OR1200_SB_IMPLEMENTED
1420 
 
1421 
//
1422 
// Number of store buffer entries
1423 
//
1424 
// Verified number of entries are 4 and 8 entries
1425 
// (2 and 3 for OR1200_SB_LOG). OR1200_SB_ENTRIES must
1426 
// always match 2**OR1200_SB_LOG.
1427 
// To disable store buffer, undefine
1428 
// OR1200_SB_IMPLEMENTED.
1429 
//
1430 
`define OR1200_SB_LOG           2       // 2 or 3
1431 
`define OR1200_SB_ENTRIES       4       // 4 or 8
1432 
 
1433 
 
1434 
/////////////////////////////////////////////////
1435 
//
1436 
// Quick Embedded Memory (QMEM)
1437 
//
1438 
 
1439 
//
1440 
// Quick Embedded Memory
1441 
//
1442 
// Instantiation of dedicated insn/data memory (RAM or ROM).
1443 
// Insn fetch has effective throughput 1insn / clock cycle.
1444 
// Data load takes two clock cycles / access, data store
1445 
// takes 1 clock cycle / access (if there is no insn fetch)).
1446 
// Memory instantiation is shared between insn and data,
1447 
// meaning if insn fetch are performed, data load/store
1448 
// performance will be lower.
1449 
//
1450 
// Main reason for QMEM is to put some time critical functions
1451 
// into this memory and to have predictable and fast access
1452 
// to these functions. (soft fpu, context switch, exception
1453 
// handlers, stack, etc)
1454 
//
1455 
// It makes design a bit bigger and slower. QMEM sits behind
1456 
// IMMU/DMMU so all addresses are physical (so the MMUs can be
1457 
// used with QMEM and QMEM is seen by the CPU just like any other
1458 
// memory in the system). IC/DC are sitting behind QMEM so the
1459 
// whole design timing might be worse with QMEM implemented.
1460 
//
1461 
// `define OR1200_QMEM_IMPLEMENTED
1462 
 
1463 
//
1464 
// Base address and mask of QMEM
1465 
//
1466 
// Base address defines first address of QMEM. Mask defines
1467 
// QMEM range in address space. Actual size of QMEM is however
1468 
// determined with instantiated RAM/ROM. However bigger
1469 
// mask will reserve more address space for QMEM, but also
1470 
// make design faster, while more tight mask will take
1471 
// less address space but also make design slower. If
1472 
// instantiated RAM/ROM is smaller than space reserved with
1473 
// the mask, instatiated RAM/ROM will also be shadowed
1474 
// at higher addresses in reserved space.
1475 
//
1476 
`define OR1200_QMEM_IADDR       32'hffe0_0000
1477 
`define OR1200_QMEM_IMASK       32'hfff0_0000   // Max QMEM size 1MB
1478 
`define OR1200_QMEM_DADDR  32'hffe0_0000
1479 
`define OR1200_QMEM_DMASK  32'hfff0_0000 // Max QMEM size 1MB
1480 
 
1481 
//
1482 
// QMEM interface byte-select capability
1483 
//
1484 
// To enable qmem_sel* ports, define this macro.
1485 
//
1486 
//`define OR1200_QMEM_BSEL
1487 
 
1488 
//
1489 
// QMEM interface acknowledge
1490 
//
1491 
// To enable qmem_ack port, define this macro.
1492 
//
1493 
//`define OR1200_QMEM_ACK
1494 
 
1495 
/////////////////////////////////////////////////////
1496 
//
1497 
// VR, UPR and Configuration Registers
1498 
//
1499 
//
1500 
// VR, UPR and configuration registers are optional. If
1501 
// implemented, operating system can automatically figure
1502 
// out how to use the processor because it knows
1503 
// what units are available in the processor and how they
1504 
// are configured.
1505 
//
1506 
// This section must be last in or1200_defines.v file so
1507 
// that all units are already configured and thus
1508 
// configuration registers are properly set.
1509 
//
1510 
 
1511 
// Define if you want configuration registers implemented
1512 
`define OR1200_CFGR_IMPLEMENTED
1513 
 
1514 
// Define if you want full address decode inside SYS group
1515 
`define OR1200_SYS_FULL_DECODE
1516 
 
1517 
// Offsets of VR, UPR and CFGR registers
1518 
`define OR1200_SPRGRP_SYS_VR            4'h0
1519 
`define OR1200_SPRGRP_SYS_UPR           4'h1
1520 
`define OR1200_SPRGRP_SYS_CPUCFGR       4'h2
1521 
`define OR1200_SPRGRP_SYS_DMMUCFGR      4'h3
1522 
`define OR1200_SPRGRP_SYS_IMMUCFGR      4'h4
1523 
`define OR1200_SPRGRP_SYS_DCCFGR        4'h5
1524 
`define OR1200_SPRGRP_SYS_ICCFGR        4'h6
1525 
`define OR1200_SPRGRP_SYS_DCFGR 4'h7
1526 
 
1527 
// VR fields
1528 
`define OR1200_VR_REV_BITS              5:0
1529 
`define OR1200_VR_RES1_BITS             15:6
1530 
`define OR1200_VR_CFG_BITS              23:16
1531 
`define OR1200_VR_VER_BITS              31:24
1532 
 
1533 
// VR values
1534 
`define OR1200_VR_REV                   6'h01
1535 
`define OR1200_VR_RES1                  10'h000
1536 
`define OR1200_VR_CFG                   8'h00
1537 
`define OR1200_VR_VER                   8'h12
1538 
 
1539 
// UPR fields
1540 
`define OR1200_UPR_UP_BITS              0
1541 
`define OR1200_UPR_DCP_BITS             1
1542 
`define OR1200_UPR_ICP_BITS             2
1543 
`define OR1200_UPR_DMP_BITS             3
1544 
`define OR1200_UPR_IMP_BITS             4
1545 
`define OR1200_UPR_MP_BITS              5
1546 
`define OR1200_UPR_DUP_BITS             6
1547 
`define OR1200_UPR_PCUP_BITS            7
1548 
`define OR1200_UPR_PMP_BITS             8
1549 
`define OR1200_UPR_PICP_BITS            9
1550 
`define OR1200_UPR_TTP_BITS             10
1551 
`define OR1200_UPR_RES1_BITS            23:11
1552 
`define OR1200_UPR_CUP_BITS             31:24
1553 
 
1554 
// UPR values
1555 
`define OR1200_UPR_UP                   1'b1
1556 
`ifdef OR1200_NO_DC
1557 
`define OR1200_UPR_DCP                  1'b0
1558 
`else
1559 
`define OR1200_UPR_DCP                  1'b1
1560 
`endif
1561 
`ifdef OR1200_NO_IC
1562 
`define OR1200_UPR_ICP                  1'b0
1563 
`else
1564 
`define OR1200_UPR_ICP                  1'b1
1565 
`endif
1566 
`ifdef OR1200_NO_DMMU
1567 
`define OR1200_UPR_DMP                  1'b0
1568 
`else
1569 
`define OR1200_UPR_DMP                  1'b1
1570 
`endif
1571 
`ifdef OR1200_NO_IMMU
1572 
`define OR1200_UPR_IMP                  1'b0
1573 
`else
1574 
`define OR1200_UPR_IMP                  1'b1
1575 
`endif
1576 
`define OR1200_UPR_MP                   1'b1    // MAC always present
1577 
`ifdef OR1200_DU_IMPLEMENTED
1578 
`define OR1200_UPR_DUP                  1'b1
1579 
`else
1580 
`define OR1200_UPR_DUP                  1'b0
1581 
`endif
1582 
`define OR1200_UPR_PCUP                 1'b0    // Performance counters not present
1583 
`ifdef OR1200_DU_IMPLEMENTED
1584 
`define OR1200_UPR_PMP                  1'b1
1585 
`else
1586 
`define OR1200_UPR_PMP                  1'b0
1587 
`endif
1588 
`ifdef OR1200_DU_IMPLEMENTED
1589 
`define OR1200_UPR_PICP                 1'b1
1590 
`else
1591 
`define OR1200_UPR_PICP                 1'b0
1592 
`endif
1593 
`ifdef OR1200_DU_IMPLEMENTED
1594 
`define OR1200_UPR_TTP                  1'b1
1595 
`else
1596 
`define OR1200_UPR_TTP                  1'b0
1597 
`endif
1598 
`define OR1200_UPR_RES1                 13'h0000
1599 
`define OR1200_UPR_CUP                  8'h00
1600 
 
1601 
// CPUCFGR fields
1602 
`define OR1200_CPUCFGR_NSGF_BITS        3:0
1603 
`define OR1200_CPUCFGR_HGF_BITS 4
1604 
`define OR1200_CPUCFGR_OB32S_BITS       5
1605 
`define OR1200_CPUCFGR_OB64S_BITS       6
1606 
`define OR1200_CPUCFGR_OF32S_BITS       7
1607 
`define OR1200_CPUCFGR_OF64S_BITS       8
1608 
`define OR1200_CPUCFGR_OV64S_BITS       9
1609 
`define OR1200_CPUCFGR_RES1_BITS        31:10
1610 
 
1611 
// CPUCFGR values
1612 
`define OR1200_CPUCFGR_NSGF             4'h0
1613 
`define OR1200_CPUCFGR_HGF              1'b0
1614 
`define OR1200_CPUCFGR_OB32S            1'b1
1615 
`define OR1200_CPUCFGR_OB64S            1'b0
1616 
`define OR1200_CPUCFGR_OF32S            1'b0
1617 
`define OR1200_CPUCFGR_OF64S            1'b0
1618 
`define OR1200_CPUCFGR_OV64S            1'b0
1619 
`define OR1200_CPUCFGR_RES1             22'h000000
1620 
 
1621 
// DMMUCFGR fields
1622 
`define OR1200_DMMUCFGR_NTW_BITS        1:0
1623 
`define OR1200_DMMUCFGR_NTS_BITS        4:2
1624 
`define OR1200_DMMUCFGR_NAE_BITS        7:5
1625 
`define OR1200_DMMUCFGR_CRI_BITS        8
1626 
`define OR1200_DMMUCFGR_PRI_BITS        9
1627 
`define OR1200_DMMUCFGR_TEIRI_BITS      10
1628 
`define OR1200_DMMUCFGR_HTR_BITS        11
1629 
`define OR1200_DMMUCFGR_RES1_BITS       31:12
1630 
 
1631 
// DMMUCFGR values
1632 
`ifdef OR1200_NO_DMMU
1633 
`define OR1200_DMMUCFGR_NTW             2'h0    // Irrelevant
1634 
`define OR1200_DMMUCFGR_NTS             3'h0    // Irrelevant
1635 
`define OR1200_DMMUCFGR_NAE             3'h0    // Irrelevant
1636 
`define OR1200_DMMUCFGR_CRI             1'b0    // Irrelevant
1637 
`define OR1200_DMMUCFGR_PRI             1'b0    // Irrelevant
1638 
`define OR1200_DMMUCFGR_TEIRI           1'b0    // Irrelevant
1639 
`define OR1200_DMMUCFGR_HTR             1'b0    // Irrelevant
1640 
`define OR1200_DMMUCFGR_RES1            20'h00000
1641 
`else
1642 
`define OR1200_DMMUCFGR_NTW             2'h0    // 1 TLB way
1643 
`define OR1200_DMMUCFGR_NTS 3'h`OR1200_DTLB_INDXW       // Num TLB sets
1644 
`define OR1200_DMMUCFGR_NAE             3'h0    // No ATB entries
1645 
`define OR1200_DMMUCFGR_CRI             1'b0    // No control register
1646 
`define OR1200_DMMUCFGR_PRI             1'b0    // No protection reg
1647 
`define OR1200_DMMUCFGR_TEIRI           1'b1    // TLB entry inv reg impl.
1648 
`define OR1200_DMMUCFGR_HTR             1'b0    // No HW TLB reload
1649 
`define OR1200_DMMUCFGR_RES1            20'h00000
1650 
`endif
1651 
 
1652 
// IMMUCFGR fields
1653 
`define OR1200_IMMUCFGR_NTW_BITS        1:0
1654 
`define OR1200_IMMUCFGR_NTS_BITS        4:2
1655 
`define OR1200_IMMUCFGR_NAE_BITS        7:5
1656 
`define OR1200_IMMUCFGR_CRI_BITS        8
1657 
`define OR1200_IMMUCFGR_PRI_BITS        9
1658 
`define OR1200_IMMUCFGR_TEIRI_BITS      10
1659 
`define OR1200_IMMUCFGR_HTR_BITS        11
1660 
`define OR1200_IMMUCFGR_RES1_BITS       31:12
1661 
 
1662 
// IMMUCFGR values
1663 
`ifdef OR1200_NO_IMMU
1664 
`define OR1200_IMMUCFGR_NTW             2'h0    // Irrelevant
1665 
`define OR1200_IMMUCFGR_NTS             3'h0    // Irrelevant
1666 
`define OR1200_IMMUCFGR_NAE             3'h0    // Irrelevant
1667 
`define OR1200_IMMUCFGR_CRI             1'b0    // Irrelevant
1668 
`define OR1200_IMMUCFGR_PRI             1'b0    // Irrelevant
1669 
`define OR1200_IMMUCFGR_TEIRI           1'b0    // Irrelevant
1670 
`define OR1200_IMMUCFGR_HTR             1'b0    // Irrelevant
1671 
`define OR1200_IMMUCFGR_RES1            20'h00000
1672 
`else
1673 
`define OR1200_IMMUCFGR_NTW             2'h0    // 1 TLB way
1674 
`define OR1200_IMMUCFGR_NTS 3'h`OR1200_ITLB_INDXW       // Num TLB sets
1675 
`define OR1200_IMMUCFGR_NAE             3'h0    // No ATB entry
1676 
`define OR1200_IMMUCFGR_CRI             1'b0    // No control reg
1677 
`define OR1200_IMMUCFGR_PRI             1'b0    // No protection reg
1678 
`define OR1200_IMMUCFGR_TEIRI           1'b1    // TLB entry inv reg impl
1679 
`define OR1200_IMMUCFGR_HTR             1'b0    // No HW TLB reload
1680 
`define OR1200_IMMUCFGR_RES1            20'h00000
1681 
`endif
1682 
 
1683 
// DCCFGR fields
1684 
`define OR1200_DCCFGR_NCW_BITS          2:0
1685 
`define OR1200_DCCFGR_NCS_BITS          6:3
1686 
`define OR1200_DCCFGR_CBS_BITS          7
1687 
`define OR1200_DCCFGR_CWS_BITS          8
1688 
`define OR1200_DCCFGR_CCRI_BITS         9
1689 
`define OR1200_DCCFGR_CBIRI_BITS        10
1690 
`define OR1200_DCCFGR_CBPRI_BITS        11
1691 
`define OR1200_DCCFGR_CBLRI_BITS        12
1692 
`define OR1200_DCCFGR_CBFRI_BITS        13
1693 
`define OR1200_DCCFGR_CBWBRI_BITS       14
1694 
`define OR1200_DCCFGR_RES1_BITS 31:15
1695 
 
1696 
// DCCFGR values
1697 
`ifdef OR1200_NO_DC
1698 
`define OR1200_DCCFGR_NCW               3'h0    // Irrelevant
1699 
`define OR1200_DCCFGR_NCS               4'h0    // Irrelevant
1700 
`define OR1200_DCCFGR_CBS               1'b0    // Irrelevant
1701 
`define OR1200_DCCFGR_CWS               1'b0    // Irrelevant
1702 
`define OR1200_DCCFGR_CCRI              1'b1    // Irrelevant
1703 
`define OR1200_DCCFGR_CBIRI             1'b1    // Irrelevant
1704 
`define OR1200_DCCFGR_CBPRI             1'b0    // Irrelevant
1705 
`define OR1200_DCCFGR_CBLRI             1'b0    // Irrelevant
1706 
`define OR1200_DCCFGR_CBFRI             1'b1    // Irrelevant
1707 
`define OR1200_DCCFGR_CBWBRI            1'b0    // Irrelevant
1708 
`define OR1200_DCCFGR_RES1              17'h00000
1709 
`else
1710 
`define OR1200_DCCFGR_NCW               3'h0    // 1 cache way
1711 
`define OR1200_DCCFGR_NCS (`OR1200_DCTAG)       // Num cache sets
1712 
`define OR1200_DCCFGR_CBS (`OR1200_DCLS-4)      // 16 byte cache block
1713 
`define OR1200_DCCFGR_CWS               1'b0    // Write-through strategy
1714 
`define OR1200_DCCFGR_CCRI              1'b1    // Cache control reg impl.
1715 
`define OR1200_DCCFGR_CBIRI             1'b1    // Cache block inv reg impl.
1716 
`define OR1200_DCCFGR_CBPRI             1'b0    // Cache block prefetch reg not impl.
1717 
`define OR1200_DCCFGR_CBLRI             1'b0    // Cache block lock reg not impl.
1718 
`define OR1200_DCCFGR_CBFRI             1'b1    // Cache block flush reg impl.
1719 
`define OR1200_DCCFGR_CBWBRI            1'b0    // Cache block WB reg not impl.
1720 
`define OR1200_DCCFGR_RES1              17'h00000
1721 
`endif
1722 
 
1723 
// ICCFGR fields
1724 
`define OR1200_ICCFGR_NCW_BITS          2:0
1725 
`define OR1200_ICCFGR_NCS_BITS          6:3
1726 
`define OR1200_ICCFGR_CBS_BITS          7
1727 
`define OR1200_ICCFGR_CWS_BITS          8
1728 
`define OR1200_ICCFGR_CCRI_BITS         9
1729 
`define OR1200_ICCFGR_CBIRI_BITS        10
1730 
`define OR1200_ICCFGR_CBPRI_BITS        11
1731 
`define OR1200_ICCFGR_CBLRI_BITS        12
1732 
`define OR1200_ICCFGR_CBFRI_BITS        13
1733 
`define OR1200_ICCFGR_CBWBRI_BITS       14
1734 
`define OR1200_ICCFGR_RES1_BITS 31:15
1735 
 
1736 
// ICCFGR values
1737 
`ifdef OR1200_NO_IC
1738 
`define OR1200_ICCFGR_NCW               3'h0    // Irrelevant
1739 
`define OR1200_ICCFGR_NCS               4'h0    // Irrelevant
1740 
`define OR1200_ICCFGR_CBS               1'b0    // Irrelevant
1741 
`define OR1200_ICCFGR_CWS               1'b0    // Irrelevant
1742 
`define OR1200_ICCFGR_CCRI              1'b0    // Irrelevant
1743 
`define OR1200_ICCFGR_CBIRI             1'b0    // Irrelevant
1744 
`define OR1200_ICCFGR_CBPRI             1'b0    // Irrelevant
1745 
`define OR1200_ICCFGR_CBLRI             1'b0    // Irrelevant
1746 
`define OR1200_ICCFGR_CBFRI             1'b0    // Irrelevant
1747 
`define OR1200_ICCFGR_CBWBRI            1'b0    // Irrelevant
1748 
`define OR1200_ICCFGR_RES1              17'h00000
1749 
`else
1750 
`define OR1200_ICCFGR_NCW               3'h0    // 1 cache way
1751 
`define OR1200_ICCFGR_NCS (`OR1200_ICTAG)       // Num cache sets
1752 
`define OR1200_ICCFGR_CBS (`OR1200_ICLS-4)      // 16 byte cache block
1753 
`define OR1200_ICCFGR_CWS               1'b0    // Irrelevant
1754 
`define OR1200_ICCFGR_CCRI              1'b1    // Cache control reg impl.
1755 
`define OR1200_ICCFGR_CBIRI             1'b1    // Cache block inv reg impl.
1756 
`define OR1200_ICCFGR_CBPRI             1'b0    // Cache block prefetch reg not impl.
1757 
`define OR1200_ICCFGR_CBLRI             1'b0    // Cache block lock reg not impl.
1758 
`define OR1200_ICCFGR_CBFRI             1'b1    // Cache block flush reg impl.
1759 
`define OR1200_ICCFGR_CBWBRI            1'b0    // Irrelevant
1760 
`define OR1200_ICCFGR_RES1              17'h00000
1761 
`endif
1762 
 
1763 
// DCFGR fields
1764 
`define OR1200_DCFGR_NDP_BITS           2:0
1765 
`define OR1200_DCFGR_WPCI_BITS          3
1766 
`define OR1200_DCFGR_RES1_BITS          31:4
1767 
 
1768 
// DCFGR values
1769 
`ifdef OR1200_DU_HWBKPTS
1770 
`define OR1200_DCFGR_NDP        3'h`OR1200_DU_DVRDCR_PAIRS // # of DVR/DCR pairs
1771 
`ifdef OR1200_DU_DWCR0
1772 
`define OR1200_DCFGR_WPCI               1'b1
1773 
`else
1774 
`define OR1200_DCFGR_WPCI               1'b0    // WP counters not impl.
1775 
`endif
1776 
`else
1777 
`define OR1200_DCFGR_NDP                3'h0    // Zero DVR/DCR pairs
1778 
`define OR1200_DCFGR_WPCI               1'b0    // WP counters not impl.
1779 
`endif
1780 
`define OR1200_DCFGR_RES1               28'h0000000
1781 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.