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[/] [or1200_soc/] [trunk/] [src/] [soc_boot.v] - Blame information for rev 15

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Line No. Rev Author Line
1 2 qaztronic
// --------------------------------------------------------------------
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//
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// --------------------------------------------------------------------
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module soc_boot(
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                input   [31:0]  mem_data_i,
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                output  [31:0]  mem_data_o,
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                input   [31:0]  mem_addr_i,
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                input   [3:0]   mem_sel_i,
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                input           mem_we_i,
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                input           mem_cyc_i,
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                input           mem_stb_i,
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                output          mem_ack_o,
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                output          mem_err_o,
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                output          mem_rty_o,
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                input   [1:0]   boot_select,
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                input           mem_clk_i,
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                input           mem_rst_i
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              );
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        parameter BOOT_VECTOR_FILE      = "../../../../or1200_soc/sw/load_this_to_ram/boot_vector_rom.txt";
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        parameter BOOT_ROM_0_FILE       = "../../../../or1200_soc/sw/load_this_to_ram/boot_rom_0.txt";
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        parameter BOOT_ROM_0_DEPTH      = 8;
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        parameter BOOT_ROM_1_FILE       = "../../../../or1200_soc/sw/load_this_to_ram/boot_rom_1.txt";
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        parameter BOOT_ROM_1_DEPTH      = 15;
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        parameter BOOT_ROM_2_FILE       = 0;
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        parameter BOOT_ROM_2_DEPTH      = 0;
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  //---------------------------------------------------
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  // slave muxes
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  reg  [1:0]   slave_select;
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  always @(*)
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    casez( {mem_addr_i[27:26], boot_select} )
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      4'b00_00: slave_select = 2'b00;
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      4'b00_01: slave_select = 2'b01;
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      4'b00_10: slave_select = 2'b10;
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      4'b00_11: slave_select = 2'b11;
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      4'b01_??: slave_select = 2'b01;
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      4'b10_??: slave_select = 2'b10;
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      4'b11_??: slave_select = 2'b11;
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    endcase
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  // data_o mux
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  wire  [31:0]  slave_0_data_o, slave_1_data_o, slave_2_data_o, slave_3_data_o;
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  reg   [31:0]  slave_mux_data_o;
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  assign mem_data_o = slave_mux_data_o;
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  always @(*)
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    case( slave_select )
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      2'b00: slave_mux_data_o = slave_0_data_o;
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      2'b01: slave_mux_data_o = slave_1_data_o;
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      2'b10: slave_mux_data_o = slave_2_data_o;
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      2'b11: slave_mux_data_o = slave_3_data_o;
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    endcase
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  assign mem_ack_o        = mem_cyc_i & mem_stb_i;
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  assign mem_err_o                              = 1'b0;
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  assign mem_rty_o                              = 1'b0;
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  //---------------------------------------------------
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  // boot_vector_rom
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  wire slave_0_we_i = mem_we_i & (slave_select == 2'b00);
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  soc_ram #(    .DATA_WIDTH(32), .ADDR_WIDTH(2),
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                                                .MEM_INIT(BOOT_VECTOR_FILE) )
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  i_boot_vector_rom             (
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                                    .data(mem_data_i),
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                                    .addr( mem_addr_i[3:2] ),
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                                    .we(slave_0_we_i),
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                                    .clk(~mem_clk_i),
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                                    .q(slave_0_data_o)
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                                  );
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  //---------------------------------------------------
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  // boot_rom_0
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  wire slave_1_we_i = mem_we_i & (slave_select == 2'b01);
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        generate
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                if( BOOT_ROM_0_FILE )
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                  soc_ram #(    .DATA_WIDTH(32), .ADDR_WIDTH(BOOT_ROM_0_DEPTH) ,
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                                                                .MEM_INIT(BOOT_ROM_0_FILE) )
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                  i_boot_rom_0                          (
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                                                    .data(mem_data_i),
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                                                    .addr( mem_addr_i[(BOOT_ROM_0_DEPTH + 1):2] ),
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                                                    .we(slave_1_we_i),
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                                                    .clk(~mem_clk_i),
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                                                    .q(slave_1_data_o)
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                                                  );
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                else
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                        assign slave_1_data_o = 32'h1bad_c0de;
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        endgenerate
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  //---------------------------------------------------
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  // boot_rom_1
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  wire slave_2_we_i = mem_we_i & (slave_select == 2'b10);
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        generate
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                if( BOOT_ROM_1_FILE )
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                  soc_ram #(    .DATA_WIDTH(32), .ADDR_WIDTH(BOOT_ROM_1_DEPTH),
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                                                                .MEM_INIT(BOOT_ROM_1_FILE) )
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                  i_boot_rom_1                          (
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                                                    .data(mem_data_i),
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                                                    .addr( mem_addr_i[(BOOT_ROM_1_DEPTH + 1):2] ),
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                                                    .we(slave_2_we_i),
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                                                    .clk(~mem_clk_i),
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                                                    .q(slave_2_data_o)
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                                                  );
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                else
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                        assign slave_2_data_o = 32'h1bad_c0de;
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        endgenerate
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  //---------------------------------------------------
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  // boot_rom_2
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  wire slave_3_we_i = mem_we_i & (slave_select == 2'b11);
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        generate
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                if( BOOT_ROM_2_FILE )
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                  soc_ram #(    .DATA_WIDTH(32), .ADDR_WIDTH(BOOT_ROM_2_DEPTH),
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                                                                .MEM_INIT(BOOT_ROM_2_FILE) )
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                  i_boot_rom_2                          (
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                                                    .data(mem_data_i),
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                                                    .addr( mem_addr_i[(BOOT_ROM_2_DEPTH + 1):2] ),
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                                                    .we(slave_3_we_i),
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                                                    .clk(~mem_clk_i),
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                                                    .q(slave_3_data_o)
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                                                  );
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                else
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                        assign slave_3_data_o = 32'h1bad_c0de;
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        endgenerate
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endmodule
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