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[/] [or1200_soc/] [trunk/] [src/] [soc_boot.v] - Blame information for rev 2

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// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
 
module soc_boot(
                input   [31:0]  mem_data_i,
                output  [31:0]  mem_data_o,
                input   [31:0]  mem_addr_i,
                input   [3:0]   mem_sel_i,
                input           mem_we_i,
                input           mem_cyc_i,
                input           mem_stb_i,
                output          mem_ack_o,
                output          mem_err_o,
                output          mem_rty_o,
 
                input   [1:0]   boot_select,
 
                input           mem_clk_i,
                input           mem_rst_i
              );
 
        parameter BOOT_VECTOR_FILE      = "../../../../or1200_soc/sw/load_this_to_ram/boot_vector_rom.txt";
        parameter BOOT_ROM_0_FILE       = "../../../../or1200_soc/sw/load_this_to_ram/boot_rom_0.txt";
        parameter BOOT_ROM_0_DEPTH      = 8;
        parameter BOOT_ROM_1_FILE       = "../../../../or1200_soc/sw/load_this_to_ram/boot_rom_1.txt";
        parameter BOOT_ROM_1_DEPTH      = 15;
        parameter BOOT_ROM_2_FILE       = 0;
        parameter BOOT_ROM_2_DEPTH      = 0;
 
  //---------------------------------------------------
  // slave muxes
  reg  [1:0]   slave_select;
 
  always @(*)
    casez( {mem_addr_i[27:26], boot_select} )
      4'b00_00: slave_select = 2'b00;
      4'b00_01: slave_select = 2'b01;
      4'b00_10: slave_select = 2'b10;
      4'b00_11: slave_select = 2'b11;
      4'b01_??: slave_select = 2'b01;
      4'b10_??: slave_select = 2'b10;
      4'b11_??: slave_select = 2'b11;
    endcase
 
  // data_o mux
  wire  [31:0]  slave_0_data_o, slave_1_data_o, slave_2_data_o, slave_3_data_o;
  reg   [31:0]  slave_mux_data_o;
 
  assign mem_data_o = slave_mux_data_o;
 
  always @(*)
    case( slave_select )
      2'b00: slave_mux_data_o = slave_0_data_o;
      2'b01: slave_mux_data_o = slave_1_data_o;
      2'b10: slave_mux_data_o = slave_2_data_o;
      2'b11: slave_mux_data_o = slave_3_data_o;
    endcase
 
  assign mem_ack_o        = mem_cyc_i & mem_stb_i;
  assign mem_err_o                              = 1'b0;
  assign mem_rty_o                              = 1'b0;
 
 
  //---------------------------------------------------
  // boot_vector_rom
  wire slave_0_we_i = mem_we_i & (slave_select == 2'b00);
 
  soc_ram #(    .DATA_WIDTH(32), .ADDR_WIDTH(2),
                                                .MEM_INIT(BOOT_VECTOR_FILE) )
  i_boot_vector_rom             (
                                    .data(mem_data_i),
                                    .addr( mem_addr_i[3:2] ),
                                    .we(slave_0_we_i),
                                    .clk(~mem_clk_i),
                                    .q(slave_0_data_o)
                                  );
 
  //---------------------------------------------------
  // boot_rom_0
  wire slave_1_we_i = mem_we_i & (slave_select == 2'b01);
 
        generate
                if( BOOT_ROM_0_FILE )
                  soc_ram #(    .DATA_WIDTH(32), .ADDR_WIDTH(BOOT_ROM_0_DEPTH) ,
                                                                .MEM_INIT(BOOT_ROM_0_FILE) )
                  i_boot_rom_0                          (
                                                    .data(mem_data_i),
                                                    .addr( mem_addr_i[(BOOT_ROM_0_DEPTH + 1):2] ),
                                                    .we(slave_1_we_i),
                                                    .clk(~mem_clk_i),
                                                    .q(slave_1_data_o)
                                                  );
                else
                        assign slave_1_data_o = 32'h1bad_c0de;
        endgenerate
 
  //---------------------------------------------------
  // boot_rom_1
  wire slave_2_we_i = mem_we_i & (slave_select == 2'b10);
 
        generate
                if( BOOT_ROM_1_FILE )
                  soc_ram #(    .DATA_WIDTH(32), .ADDR_WIDTH(BOOT_ROM_1_DEPTH),
                                                                .MEM_INIT(BOOT_ROM_1_FILE) )
                  i_boot_rom_1                          (
                                                    .data(mem_data_i),
                                                    .addr( mem_addr_i[(BOOT_ROM_1_DEPTH + 1):2] ),
                                                    .we(slave_2_we_i),
                                                    .clk(~mem_clk_i),
                                                    .q(slave_2_data_o)
                                                  );
                else
                        assign slave_2_data_o = 32'h1bad_c0de;
        endgenerate
 
  //---------------------------------------------------
  // boot_rom_2
  wire slave_3_we_i = mem_we_i & (slave_select == 2'b11);
 
        generate
                if( BOOT_ROM_2_FILE )
                  soc_ram #(    .DATA_WIDTH(32), .ADDR_WIDTH(BOOT_ROM_2_DEPTH),
                                                                .MEM_INIT(BOOT_ROM_2_FILE) )
                  i_boot_rom_2                          (
                                                    .data(mem_data_i),
                                                    .addr( mem_addr_i[(BOOT_ROM_2_DEPTH + 1):2] ),
                                                    .we(slave_3_we_i),
                                                    .clk(~mem_clk_i),
                                                    .q(slave_3_data_o)
                                                  );
                else
                        assign slave_3_data_o = 32'h1bad_c0de;
        endgenerate
 
endmodule
 

Line No.	Rev	Author	Line
1	2	qaztronic	`// --------------------------------------------------------------------`
2			`//`
3			`// --------------------------------------------------------------------`
4
5
6			`module soc_boot(`
7			`input [31:0] mem_data_i,`
8			`output [31:0] mem_data_o,`
9			`input [31:0] mem_addr_i,`
10			`input [3:0] mem_sel_i,`
11			`input mem_we_i,`
12			`input mem_cyc_i,`
13			`input mem_stb_i,`
14			`output mem_ack_o,`
15			`output mem_err_o,`
16			`output mem_rty_o,`
17
18			`input [1:0] boot_select,`
19
20			`input mem_clk_i,`
21			`input mem_rst_i`
22			`);`
23
24			`parameter BOOT_VECTOR_FILE = "../../../../or1200_soc/sw/load_this_to_ram/boot_vector_rom.txt";`
25			`parameter BOOT_ROM_0_FILE = "../../../../or1200_soc/sw/load_this_to_ram/boot_rom_0.txt";`
26			`parameter BOOT_ROM_0_DEPTH = 8;`
27			`parameter BOOT_ROM_1_FILE = "../../../../or1200_soc/sw/load_this_to_ram/boot_rom_1.txt";`
28			`parameter BOOT_ROM_1_DEPTH = 15;`
29			`parameter BOOT_ROM_2_FILE = 0;`
30			`parameter BOOT_ROM_2_DEPTH = 0;`
31
32			`//---------------------------------------------------`
33			`// slave muxes`
34			`reg [1:0] slave_select;`
35
36			`always @(*)`
37			`casez( {mem_addr_i[27:26], boot_select} )`
38			`4'b00_00: slave_select = 2'b00;`
39			`4'b00_01: slave_select = 2'b01;`
40			`4'b00_10: slave_select = 2'b10;`
41			`4'b00_11: slave_select = 2'b11;`
42			`4'b01_??: slave_select = 2'b01;`
43			`4'b10_??: slave_select = 2'b10;`
44			`4'b11_??: slave_select = 2'b11;`
45			`endcase`
46
47			`// data_o mux`
48			`wire [31:0] slave_0_data_o, slave_1_data_o, slave_2_data_o, slave_3_data_o;`
49			`reg [31:0] slave_mux_data_o;`
50
51			`assign mem_data_o = slave_mux_data_o;`
52
53			`always @(*)`
54			`case( slave_select )`
55			`2'b00: slave_mux_data_o = slave_0_data_o;`
56			`2'b01: slave_mux_data_o = slave_1_data_o;`
57			`2'b10: slave_mux_data_o = slave_2_data_o;`
58			`2'b11: slave_mux_data_o = slave_3_data_o;`
59			`endcase`
60
61			`assign mem_ack_o = mem_cyc_i & mem_stb_i;`
62			`assign mem_err_o = 1'b0;`
63			`assign mem_rty_o = 1'b0;`
64
65
66			`//---------------------------------------------------`
67			`// boot_vector_rom`
68			`wire slave_0_we_i = mem_we_i & (slave_select == 2'b00);`
69
70			`soc_ram #( .DATA_WIDTH(32), .ADDR_WIDTH(2),`
71			`.MEM_INIT(BOOT_VECTOR_FILE) )`
72			`i_boot_vector_rom (`
73			`.data(mem_data_i),`
74			`.addr( mem_addr_i[3:2] ),`
75			`.we(slave_0_we_i),`
76			`.clk(~mem_clk_i),`
77			`.q(slave_0_data_o)`
78			`);`
79
80			`//---------------------------------------------------`
81			`// boot_rom_0`
82			`wire slave_1_we_i = mem_we_i & (slave_select == 2'b01);`
83
84			`generate`
85			`if( BOOT_ROM_0_FILE )`
86			`soc_ram #( .DATA_WIDTH(32), .ADDR_WIDTH(BOOT_ROM_0_DEPTH) ,`
87			`.MEM_INIT(BOOT_ROM_0_FILE) )`
88			`i_boot_rom_0 (`
89			`.data(mem_data_i),`
90			`.addr( mem_addr_i[(BOOT_ROM_0_DEPTH + 1):2] ),`
91			`.we(slave_1_we_i),`
92			`.clk(~mem_clk_i),`
93			`.q(slave_1_data_o)`
94			`);`
95			`else`
96			`assign slave_1_data_o = 32'h1bad_c0de;`
97			`endgenerate`
98
99			`//---------------------------------------------------`
100			`// boot_rom_1`
101			`wire slave_2_we_i = mem_we_i & (slave_select == 2'b10);`
102
103			`generate`
104			`if( BOOT_ROM_1_FILE )`
105			`soc_ram #( .DATA_WIDTH(32), .ADDR_WIDTH(BOOT_ROM_1_DEPTH),`
106			`.MEM_INIT(BOOT_ROM_1_FILE) )`
107			`i_boot_rom_1 (`
108			`.data(mem_data_i),`
109			`.addr( mem_addr_i[(BOOT_ROM_1_DEPTH + 1):2] ),`
110			`.we(slave_2_we_i),`
111			`.clk(~mem_clk_i),`
112			`.q(slave_2_data_o)`
113			`);`
114			`else`
115			`assign slave_2_data_o = 32'h1bad_c0de;`
116			`endgenerate`
117
118			`//---------------------------------------------------`
119			`// boot_rom_2`
120			`wire slave_3_we_i = mem_we_i & (slave_select == 2'b11);`
121
122			`generate`
123			`if( BOOT_ROM_2_FILE )`
124			`soc_ram #( .DATA_WIDTH(32), .ADDR_WIDTH(BOOT_ROM_2_DEPTH),`
125			`.MEM_INIT(BOOT_ROM_2_FILE) )`
126			`i_boot_rom_2 (`
127			`.data(mem_data_i),`
128			`.addr( mem_addr_i[(BOOT_ROM_2_DEPTH + 1):2] ),`
129			`.we(slave_3_we_i),`
130			`.clk(~mem_clk_i),`
131			`.q(slave_3_data_o)`
132			`);`
133			`else`
134			`assign slave_3_data_o = 32'h1bad_c0de;`
135			`endgenerate`
136
137			`endmodule`
138

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[/] [or1200_soc/] [trunk/] [src/] [soc_boot.v] - Blame information for rev 2