OpenCores
URL https://opencores.org/ocsvn/or1200_soc/or1200_soc/trunk

Subversion Repositories or1200_soc

[/] [or1200_soc/] [trunk/] [src/] [soc_boot.v] - Blame information for rev 21

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 21 qaztronic
// --------------------------------------------------------------------
2
//
3
// --------------------------------------------------------------------
4
 
5
 
6
module soc_boot
7
  (
8
    input   [31:0]  mem_data_i,
9
    output  [31:0]  mem_data_o,
10
    input   [31:0]  mem_addr_i,
11
    input   [3:0]   mem_sel_i,
12
    input           mem_we_i,
13
    input           mem_cyc_i,
14
    input           mem_stb_i,
15
    output          mem_ack_o,
16
    output          mem_err_o,
17
    output          mem_rty_o,
18
 
19
    input       [1:0]   boot_select,
20
 
21
    input           mem_clk_i,
22
    input           mem_rst_i
23
  );
24
 
25
        parameter USE_BOOT_ROM_0            = 1;
26
//      parameter BOOT_ROM_0_FILE       = "../../../../../sw/load_this_to_ram/boot_rom_0.txt";
27
        parameter BOOT_ROM_0_DEPTH        = 8;
28
 
29
        parameter USE_BOOT_ROM_1            = 0;
30
//      parameter BOOT_ROM_1_FILE       = "../../../../../sw/load_this_to_ram/boot_rom_1.txt";
31
//      parameter BOOT_ROM_1_DEPTH      = 15;
32
        parameter BOOT_ROM_1_DEPTH        = 0;
33
 
34
        parameter USE_BOOT_ROM_2            = 0;
35
        parameter BOOT_ROM_2_FILE         = 0;
36
        parameter BOOT_ROM_2_DEPTH        = 0;
37
 
38
  //---------------------------------------------------
39
  // slave muxes
40
  reg  [1:0]   slave_select;
41
 
42
  always @(*)
43
    casez( {mem_addr_i[27:26], boot_select} )
44
      4'b00_00: slave_select = 2'b00;
45
      4'b00_01: slave_select = 2'b01;
46
      4'b00_10: slave_select = 2'b10;
47
      4'b00_11: slave_select = 2'b11;
48
      4'b01_??: slave_select = 2'b01;
49
      4'b10_??: slave_select = 2'b10;
50
      4'b11_??: slave_select = 2'b11;
51
    endcase
52
 
53
  // data_o mux
54
  wire  [31:0]  slave_0_data_o, slave_1_data_o, slave_2_data_o, slave_3_data_o;
55
  reg   [31:0]  slave_mux_data_o;
56
 
57
  assign mem_data_o = slave_mux_data_o;
58
 
59
  always @(*)
60
    case( slave_select )
61
      2'b00: slave_mux_data_o = slave_0_data_o;
62
      2'b01: slave_mux_data_o = slave_1_data_o;
63
      2'b10: slave_mux_data_o = slave_2_data_o;
64
      2'b11: slave_mux_data_o = slave_3_data_o;
65
    endcase
66
 
67
  assign mem_ack_o        = mem_cyc_i & mem_stb_i;
68
  assign mem_err_o                              = 1'b0;
69
  assign mem_rty_o                              = 1'b0;
70
 
71
 
72
  //---------------------------------------------------
73
  // boot_vector_rom
74
  wire slave_0_we_i = mem_we_i & (slave_select == 2'b00);
75
 
76
  boot_vector_rom #(    .DATA_WIDTH(32), .ADDR_WIDTH(2) )
77
    i_boot_vector_rom           (
78
                                    .data(mem_data_i),
79
                                    .addr( mem_addr_i[3:2] ),
80
                                    .we(slave_0_we_i),
81
                                    .clk(~mem_clk_i),
82
                                    .q(slave_0_data_o)
83
                                  );
84
 
85
  //---------------------------------------------------
86
  // boot_rom_0
87
  wire slave_1_we_i = mem_we_i & (slave_select == 2'b01);
88
 
89
        generate
90
                if( USE_BOOT_ROM_0 )
91
                  boot_rom_0 #(         .DATA_WIDTH(32), .ADDR_WIDTH(BOOT_ROM_0_DEPTH) )
92
                    i_boot_rom_0                                (
93
                                                    .data(mem_data_i),
94
                                                    .addr( mem_addr_i[(BOOT_ROM_0_DEPTH + 1):2] ),
95
                                                    .we(slave_1_we_i),
96
                                                    .clk(~mem_clk_i),
97
                                                    .q(slave_1_data_o)
98
                                                  );
99
                else
100
                        assign slave_1_data_o = 32'h1bad_c0de;
101
        endgenerate
102
 
103
  //---------------------------------------------------
104
  // boot_rom_1
105
  wire slave_2_we_i = mem_we_i & (slave_select == 2'b10);
106
 
107
        generate
108
                if( USE_BOOT_ROM_1 )
109
                  boot_rom_1 #(         .DATA_WIDTH(32), .ADDR_WIDTH(BOOT_ROM_1_DEPTH) )
110
                  i_boot_rom_1                          (
111
                                                    .data(mem_data_i),
112
                                                    .addr( mem_addr_i[(BOOT_ROM_1_DEPTH + 1):2] ),
113
                                                    .we(slave_2_we_i),
114
                                                    .clk(~mem_clk_i),
115
                                                    .q(slave_2_data_o)
116
                                                  );
117
                else
118
                        assign slave_2_data_o = 32'h1bad_c0de;
119
        endgenerate
120
 
121
  //---------------------------------------------------
122
  // boot_rom_2
123
  wire slave_3_we_i = mem_we_i & (slave_select == 2'b11);
124
 
125
        generate
126
                if( USE_BOOT_ROM_2 )
127
                  boot_rom_2 #(         .DATA_WIDTH(32), .ADDR_WIDTH(BOOT_ROM_2_DEPTH) )
128
                  i_boot_rom_2                          (
129
                                                    .data(mem_data_i),
130
                                                    .addr( mem_addr_i[(BOOT_ROM_2_DEPTH + 1):2] ),
131
                                                    .we(slave_3_we_i),
132
                                                    .clk(~mem_clk_i),
133
                                                    .q(slave_3_data_o)
134
                                                  );
135
                else
136
                        assign slave_3_data_o = 32'h1bad_c0de;
137
        endgenerate
138
 
139
endmodule
140
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.