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[/] [or1200_soc/] [trunk/] [src/] [soc_mem_bank_3.v] - Blame information for rev 12

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Line No. Rev Author Line
1 2 qaztronic
// --------------------------------------------------------------------
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//
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// --------------------------------------------------------------------
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module soc_mem_bank_3(
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                              input   [31:0]  mem_data_i,
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                              output  [31:0]  mem_data_o,
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                              input   [31:0]  mem_addr_i,
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                              input   [3:0]   mem_sel_i,
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                              input           mem_we_i,
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                              input           mem_cyc_i,
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                              input           mem_stb_i,
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                              output          mem_ack_o,
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                              output          mem_err_o,
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                              output          mem_rty_o,
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                              input           mem_clk_i,
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                              input           mem_rst_i
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                            );
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        parameter MEM_DEPTH     = 14;
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  //---------------------------------------------------
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  // ram_byte_0
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        soc_ram #(      .DATA_WIDTH(8), .ADDR_WIDTH(MEM_DEPTH), .MEM_INIT(0) )
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        i_ram_byte_0                            (
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                                    .data(mem_data_i[7:0]),
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                                    .addr( mem_addr_i[(MEM_DEPTH + 1):2] ),
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                                    .we(mem_we_i & mem_sel_i[0]),
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                                    .clk(~mem_clk_i),
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                                    .q(mem_data_o[7:0])
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                                  );
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  //---------------------------------------------------
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  // ram_byte_1
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        soc_ram #(      .DATA_WIDTH(8), .ADDR_WIDTH(MEM_DEPTH), .MEM_INIT(0) )
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        i_ram_byte_1                            (
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                                    .data(mem_data_i[15:8]),
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                                    .addr( mem_addr_i[(MEM_DEPTH + 1):2] ),
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                                    .we(mem_we_i & mem_sel_i[1]),
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                                    .clk(~mem_clk_i),
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                                    .q(mem_data_o[15:8])
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                                  );
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  //---------------------------------------------------
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  // ram_byte_2
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        soc_ram #(      .DATA_WIDTH(8), .ADDR_WIDTH(MEM_DEPTH), .MEM_INIT(0) )
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        i_ram_byte_2                            (
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                                    .data(mem_data_i[23:16]),
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                                    .addr( mem_addr_i[(MEM_DEPTH + 1):2] ),
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                                    .we(mem_we_i & mem_sel_i[2]),
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                                    .clk(~mem_clk_i),
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                                    .q(mem_data_o[23:16])
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                                  );
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  //---------------------------------------------------
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  // ram_byte_3
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        soc_ram #(      .DATA_WIDTH(8), .ADDR_WIDTH(MEM_DEPTH), .MEM_INIT(0) )
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        i_ram_byte_3                            (
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                                    .data(mem_data_i[31:24]),
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                                    .addr( mem_addr_i[(MEM_DEPTH + 1):2] ),
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                                    .we(mem_we_i & mem_sel_i[3]),
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                                    .clk(~mem_clk_i),
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                                    .q(mem_data_o[31:24])
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                                  );
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  //---------------------------------------------------
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  // outputs
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  assign mem_ack_o = mem_cyc_i & mem_stb_i;
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  assign mem_err_o = 1'b0;
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  assign mem_rty_o = 1'b0;
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endmodule
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