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[/] [or1200_soc/] [trunk/] [src/] [soc_mem_bank_3.v] - Blame information for rev 21

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// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
 
 
 
module soc_mem_bank_3(
                              input   [31:0]  mem_data_i,
                              output  [31:0]  mem_data_o,
                              input   [31:0]  mem_addr_i,
                              input   [3:0]   mem_sel_i,
                              input           mem_we_i,
                              input           mem_cyc_i,
                              input           mem_stb_i,
                              output          mem_ack_o,
                              output          mem_err_o,
                              output          mem_rty_o,
 
                        inout   [15:0]  sram_dq,
                        output  [17:0]  sram_addr,
                        output          sram_ub_n,
                        output          sram_lb_n,
                        output          sram_we_n,
                        output          sram_ce_n,
                        output          sram_oe_n,
 
                              input           mem_clk_i,
                              input           mem_rst_i
                            );
 
        parameter USE_ON_CHIP_MEM       = 0;
        parameter ON_CHIP_MEM_DEPTH = 14;
 
        parameter USE_ASYNC_SRAM          = 1;
 
        generate
                if( USE_ON_CHIP_MEM )
                  begin
        //---------------------------------------------------
        // ram_byte_0
        soc_ram #(      .DATA_WIDTH(8), .ADDR_WIDTH(ON_CHIP_MEM_DEPTH), .MEM_INIT(0) )
        i_ram_byte_0                            (
                                    .data(mem_data_i[7:0]),
                                    .addr( mem_addr_i[(ON_CHIP_MEM_DEPTH + 1):2] ),
                                    .we(mem_we_i & mem_sel_i[0]),
                                    .clk(~mem_clk_i),
                                    .q(mem_data_o[7:0])
                                  );
 
        //---------------------------------------------------
        // ram_byte_1
        soc_ram #(      .DATA_WIDTH(8), .ADDR_WIDTH(ON_CHIP_MEM_DEPTH), .MEM_INIT(0) )
        i_ram_byte_1                            (
                                    .data(mem_data_i[15:8]),
                                    .addr( mem_addr_i[(ON_CHIP_MEM_DEPTH + 1):2] ),
                                    .we(mem_we_i & mem_sel_i[1]),
                                    .clk(~mem_clk_i),
                                    .q(mem_data_o[15:8])
                                  );
 
        //---------------------------------------------------
        // ram_byte_2
        soc_ram #(      .DATA_WIDTH(8), .ADDR_WIDTH(ON_CHIP_MEM_DEPTH), .MEM_INIT(0) )
        i_ram_byte_2                            (
                                    .data(mem_data_i[23:16]),
                                    .addr( mem_addr_i[(ON_CHIP_MEM_DEPTH + 1):2] ),
                                    .we(mem_we_i & mem_sel_i[2]),
                                    .clk(~mem_clk_i),
                                    .q(mem_data_o[23:16])
                                  );
 
        //---------------------------------------------------
        // ram_byte_3
        soc_ram #(      .DATA_WIDTH(8), .ADDR_WIDTH(ON_CHIP_MEM_DEPTH), .MEM_INIT(0) )
        i_ram_byte_3                            (
                                    .data(mem_data_i[31:24]),
                                    .addr( mem_addr_i[(ON_CHIP_MEM_DEPTH + 1):2] ),
                                    .we(mem_we_i & mem_sel_i[3]),
                                    .clk(~mem_clk_i),
                                    .q(mem_data_o[31:24])
                                  );
 
        //---------------------------------------------------
        // outputs for on chip memory
        assign mem_ack_o = mem_cyc_i & mem_stb_i;
        assign mem_err_o = 1'b0;
        assign mem_rty_o = 1'b0;
 
      end
                else if( USE_ASYNC_SRAM )
                  begin
        //---------------------------------------------------
        // async_mem_if
        async_mem_if #( .AW(18), .DW(16) )
        i_sram (
                  .async_dq(sram_dq),
                  .async_addr(sram_addr),
                  .async_ub_n(sram_ub_n),
                  .async_lb_n(sram_lb_n),
                  .async_we_n(sram_we_n),
                  .async_ce_n(sram_ce_n),
                  .async_oe_n(sram_oe_n),
                  .wb_clk_i(mem_clk_i),
                  .wb_rst_i(mem_rst_i),
                  .wb_adr_i( {13'h0000, mem_addr_i[18:0]} ),
                  .wb_dat_i(mem_data_i),
                  .wb_we_i(mem_we_i),
                  .wb_stb_i(mem_stb_i),
                  .wb_cyc_i(mem_cyc_i),
                  .wb_sel_i(mem_sel_i),
                  .wb_dat_o(mem_data_o),
                  .wb_ack_o(mem_ack_o),
                  .ce_setup(4'h0),
                  .op_hold(4'h1),
                  .ce_hold(4'h0),
                  .big_endian_if_i(1'b1),
                  .lo_byte_if_i(1'b0)
                );
 
        //---------------------------------------------------
        // outputs for async_mem_if
        assign mem_err_o = 1'b0;
        assign mem_rty_o = 1'b0;
      end
    else
      begin
        //---------------------------------------------------
        // outputs for stub
        assign mem_data_o = 32'h1bad_c0de;
        assign mem_ack_o = mem_cyc_i & mem_stb_i;
        assign mem_err_o = 1'b0;
        assign mem_rty_o = 1'b0;
      end
 
        endgenerate
 
endmodule
 

Line No.	Rev	Author	Line
1	21	qaztronic	`// --------------------------------------------------------------------`
2			`//`
3			`// --------------------------------------------------------------------`
4
5
6
7
8			`module soc_mem_bank_3(`
9			`input [31:0] mem_data_i,`
10			`output [31:0] mem_data_o,`
11			`input [31:0] mem_addr_i,`
12			`input [3:0] mem_sel_i,`
13			`input mem_we_i,`
14			`input mem_cyc_i,`
15			`input mem_stb_i,`
16			`output mem_ack_o,`
17			`output mem_err_o,`
18			`output mem_rty_o,`
19
20			`inout [15:0] sram_dq,`
21			`output [17:0] sram_addr,`
22			`output sram_ub_n,`
23			`output sram_lb_n,`
24			`output sram_we_n,`
25			`output sram_ce_n,`
26			`output sram_oe_n,`
27
28			`input mem_clk_i,`
29			`input mem_rst_i`
30			`);`
31
32			`parameter USE_ON_CHIP_MEM = 0;`
33			`parameter ON_CHIP_MEM_DEPTH = 14;`
34
35			`parameter USE_ASYNC_SRAM = 1;`
36
37			`generate`
38			`if( USE_ON_CHIP_MEM )`
39			`begin`
40			`//---------------------------------------------------`
41			`// ram_byte_0`
42			`soc_ram #( .DATA_WIDTH(8), .ADDR_WIDTH(ON_CHIP_MEM_DEPTH), .MEM_INIT(0) )`
43			`i_ram_byte_0 (`
44			`.data(mem_data_i[7:0]),`
45			`.addr( mem_addr_i[(ON_CHIP_MEM_DEPTH + 1):2] ),`
46			`.we(mem_we_i & mem_sel_i[0]),`
47			`.clk(~mem_clk_i),`
48			`.q(mem_data_o[7:0])`
49			`);`
50
51			`//---------------------------------------------------`
52			`// ram_byte_1`
53			`soc_ram #( .DATA_WIDTH(8), .ADDR_WIDTH(ON_CHIP_MEM_DEPTH), .MEM_INIT(0) )`
54			`i_ram_byte_1 (`
55			`.data(mem_data_i[15:8]),`
56			`.addr( mem_addr_i[(ON_CHIP_MEM_DEPTH + 1):2] ),`
57			`.we(mem_we_i & mem_sel_i[1]),`
58			`.clk(~mem_clk_i),`
59			`.q(mem_data_o[15:8])`
60			`);`
61
62			`//---------------------------------------------------`
63			`// ram_byte_2`
64			`soc_ram #( .DATA_WIDTH(8), .ADDR_WIDTH(ON_CHIP_MEM_DEPTH), .MEM_INIT(0) )`
65			`i_ram_byte_2 (`
66			`.data(mem_data_i[23:16]),`
67			`.addr( mem_addr_i[(ON_CHIP_MEM_DEPTH + 1):2] ),`
68			`.we(mem_we_i & mem_sel_i[2]),`
69			`.clk(~mem_clk_i),`
70			`.q(mem_data_o[23:16])`
71			`);`
72
73			`//---------------------------------------------------`
74			`// ram_byte_3`
75			`soc_ram #( .DATA_WIDTH(8), .ADDR_WIDTH(ON_CHIP_MEM_DEPTH), .MEM_INIT(0) )`
76			`i_ram_byte_3 (`
77			`.data(mem_data_i[31:24]),`
78			`.addr( mem_addr_i[(ON_CHIP_MEM_DEPTH + 1):2] ),`
79			`.we(mem_we_i & mem_sel_i[3]),`
80			`.clk(~mem_clk_i),`
81			`.q(mem_data_o[31:24])`
82			`);`
83
84			`//---------------------------------------------------`
85			`// outputs for on chip memory`
86			`assign mem_ack_o = mem_cyc_i & mem_stb_i;`
87			`assign mem_err_o = 1'b0;`
88			`assign mem_rty_o = 1'b0;`
89
90			`end`
91			`else if( USE_ASYNC_SRAM )`
92			`begin`
93			`//---------------------------------------------------`
94			`// async_mem_if`
95			`async_mem_if #( .AW(18), .DW(16) )`
96			`i_sram (`
97			`.async_dq(sram_dq),`
98			`.async_addr(sram_addr),`
99			`.async_ub_n(sram_ub_n),`
100			`.async_lb_n(sram_lb_n),`
101			`.async_we_n(sram_we_n),`
102			`.async_ce_n(sram_ce_n),`
103			`.async_oe_n(sram_oe_n),`
104			`.wb_clk_i(mem_clk_i),`
105			`.wb_rst_i(mem_rst_i),`
106			`.wb_adr_i( {13'h0000, mem_addr_i[18:0]} ),`
107			`.wb_dat_i(mem_data_i),`
108			`.wb_we_i(mem_we_i),`
109			`.wb_stb_i(mem_stb_i),`
110			`.wb_cyc_i(mem_cyc_i),`
111			`.wb_sel_i(mem_sel_i),`
112			`.wb_dat_o(mem_data_o),`
113			`.wb_ack_o(mem_ack_o),`
114			`.ce_setup(4'h0),`
115			`.op_hold(4'h1),`
116			`.ce_hold(4'h0),`
117			`.big_endian_if_i(1'b1),`
118			`.lo_byte_if_i(1'b0)`
119			`);`
120
121			`//---------------------------------------------------`
122			`// outputs for async_mem_if`
123			`assign mem_err_o = 1'b0;`
124			`assign mem_rty_o = 1'b0;`
125			`end`
126			`else`
127			`begin`
128			`//---------------------------------------------------`
129			`// outputs for stub`
130			`assign mem_data_o = 32'h1bad_c0de;`
131			`assign mem_ack_o = mem_cyc_i & mem_stb_i;`
132			`assign mem_err_o = 1'b0;`
133			`assign mem_rty_o = 1'b0;`
134			`end`
135
136			`endgenerate`
137
138			`endmodule`
139

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[/] [or1200_soc/] [trunk/] [src/] [soc_mem_bank_3.v] - Blame information for rev 21