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[/] [or1200_soc/] [trunk/] [src/] [soc_mem_bank_3.v] - Blame information for rev 7

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// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
 
 
 
module soc_mem_bank_3(
                              input   [31:0]  mem_data_i,
                              output  [31:0]  mem_data_o,
                              input   [31:0]  mem_addr_i,
                              input   [3:0]   mem_sel_i,
                              input           mem_we_i,
                              input           mem_cyc_i,
                              input           mem_stb_i,
                              output          mem_ack_o,
                              output          mem_err_o,
                              output          mem_rty_o,
 
                              input           mem_clk_i,
                              input           mem_rst_i
                            );
 
        parameter MEM_DEPTH     = 14;
 
  //---------------------------------------------------
  // ram_byte_0
        soc_ram #(      .DATA_WIDTH(8), .ADDR_WIDTH(MEM_DEPTH), .MEM_INIT(0) )
        i_ram_byte_0                            (
                                    .data(mem_data_i[7:0]),
                                    .addr( mem_addr_i[(MEM_DEPTH + 1):2] ),
                                    .we(mem_we_i & mem_sel_i[0]),
                                    .clk(~mem_clk_i),
                                    .q(mem_data_o[7:0])
                                  );
 
  //---------------------------------------------------
  // ram_byte_1
        soc_ram #(      .DATA_WIDTH(8), .ADDR_WIDTH(MEM_DEPTH), .MEM_INIT(0) )
        i_ram_byte_1                            (
                                    .data(mem_data_i[15:8]),
                                    .addr( mem_addr_i[(MEM_DEPTH + 1):2] ),
                                    .we(mem_we_i & mem_sel_i[1]),
                                    .clk(~mem_clk_i),
                                    .q(mem_data_o[15:8])
                                  );
 
  //---------------------------------------------------
  // ram_byte_2
        soc_ram #(      .DATA_WIDTH(8), .ADDR_WIDTH(MEM_DEPTH), .MEM_INIT(0) )
        i_ram_byte_2                            (
                                    .data(mem_data_i[23:16]),
                                    .addr( mem_addr_i[(MEM_DEPTH + 1):2] ),
                                    .we(mem_we_i & mem_sel_i[2]),
                                    .clk(~mem_clk_i),
                                    .q(mem_data_o[23:16])
                                  );
 
  //---------------------------------------------------
  // ram_byte_3
        soc_ram #(      .DATA_WIDTH(8), .ADDR_WIDTH(MEM_DEPTH), .MEM_INIT(0) )
        i_ram_byte_3                            (
                                    .data(mem_data_i[31:24]),
                                    .addr( mem_addr_i[(MEM_DEPTH + 1):2] ),
                                    .we(mem_we_i & mem_sel_i[3]),
                                    .clk(~mem_clk_i),
                                    .q(mem_data_o[31:24])
                                  );
 
 
 
  //---------------------------------------------------
  // outputs
  assign mem_ack_o = mem_cyc_i & mem_stb_i;
  assign mem_err_o = 1'b0;
  assign mem_rty_o = 1'b0;
 
endmodule
 

Line No.	Rev	Author	Line
1	2	qaztronic	`// --------------------------------------------------------------------`
2			`//`
3			`// --------------------------------------------------------------------`
4
5
6
7
8			`module soc_mem_bank_3(`
9			`input [31:0] mem_data_i,`
10			`output [31:0] mem_data_o,`
11			`input [31:0] mem_addr_i,`
12			`input [3:0] mem_sel_i,`
13			`input mem_we_i,`
14			`input mem_cyc_i,`
15			`input mem_stb_i,`
16			`output mem_ack_o,`
17			`output mem_err_o,`
18			`output mem_rty_o,`
19
20			`input mem_clk_i,`
21			`input mem_rst_i`
22			`);`
23
24			`parameter MEM_DEPTH = 14;`
25
26			`//---------------------------------------------------`
27			`// ram_byte_0`
28			`soc_ram #( .DATA_WIDTH(8), .ADDR_WIDTH(MEM_DEPTH), .MEM_INIT(0) )`
29			`i_ram_byte_0 (`
30			`.data(mem_data_i[7:0]),`
31			`.addr( mem_addr_i[(MEM_DEPTH + 1):2] ),`
32			`.we(mem_we_i & mem_sel_i[0]),`
33			`.clk(~mem_clk_i),`
34			`.q(mem_data_o[7:0])`
35			`);`
36
37			`//---------------------------------------------------`
38			`// ram_byte_1`
39			`soc_ram #( .DATA_WIDTH(8), .ADDR_WIDTH(MEM_DEPTH), .MEM_INIT(0) )`
40			`i_ram_byte_1 (`
41			`.data(mem_data_i[15:8]),`
42			`.addr( mem_addr_i[(MEM_DEPTH + 1):2] ),`
43			`.we(mem_we_i & mem_sel_i[1]),`
44			`.clk(~mem_clk_i),`
45			`.q(mem_data_o[15:8])`
46			`);`
47
48			`//---------------------------------------------------`
49			`// ram_byte_2`
50			`soc_ram #( .DATA_WIDTH(8), .ADDR_WIDTH(MEM_DEPTH), .MEM_INIT(0) )`
51			`i_ram_byte_2 (`
52			`.data(mem_data_i[23:16]),`
53			`.addr( mem_addr_i[(MEM_DEPTH + 1):2] ),`
54			`.we(mem_we_i & mem_sel_i[2]),`
55			`.clk(~mem_clk_i),`
56			`.q(mem_data_o[23:16])`
57			`);`
58
59			`//---------------------------------------------------`
60			`// ram_byte_3`
61			`soc_ram #( .DATA_WIDTH(8), .ADDR_WIDTH(MEM_DEPTH), .MEM_INIT(0) )`
62			`i_ram_byte_3 (`
63			`.data(mem_data_i[31:24]),`
64			`.addr( mem_addr_i[(MEM_DEPTH + 1):2] ),`
65			`.we(mem_we_i & mem_sel_i[3]),`
66			`.clk(~mem_clk_i),`
67			`.q(mem_data_o[31:24])`
68			`);`
69
70
71
72			`//---------------------------------------------------`
73			`// outputs`
74			`assign mem_ack_o = mem_cyc_i & mem_stb_i;`
75			`assign mem_err_o = 1'b0;`
76			`assign mem_rty_o = 1'b0;`
77
78			`endmodule`
79

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[/] [or1200_soc/] [trunk/] [src/] [soc_mem_bank_3.v] - Blame information for rev 7