OpenCores
URL https://opencores.org/ocsvn/or1200_soc/or1200_soc/trunk

Subversion Repositories or1200_soc

[/] [or1200_soc/] [trunk/] [src/] [soc_system.v] - Blame information for rev 16

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 qaztronic
// --------------------------------------------------------------------
2
//
3
// --------------------------------------------------------------------
4
 
5
 
6
module
7
  soc_system(
8
              input   [31:0]  sys_data_i,
9
              output  [31:0]  sys_data_o,
10
              input   [31:0]  sys_addr_i,
11
              input   [3:0]   sys_sel_i,
12
              input           sys_we_i,
13
              input           sys_cyc_i,
14
              input           sys_stb_i,
15
              output          sys_ack_o,
16
              output          sys_err_o,
17
              output          sys_rty_o,
18
 
19
              input   [3:0]   boot_strap,
20
              output  [1:0]   boot_select,
21
              output  [1:0]   boot_remap,
22
 
23
              input           sys_clk_i,
24
              input           sys_rst_i
25
            );
26
 
27
 
28
  //---------------------------------------------------
29
  // boot_strap flops
30
 
31
  reg [3:0] boot_strap_r;
32
 
33
  always @(negedge sys_rst_i)
34
    boot_strap_r <= boot_strap;
35
 
36
 
37
  //---------------------------------------------------
38
  // soc_registers
39
  soc_registers
40
    i_soc_registers(
41
                      .reg_data_i(sys_data_i),
42
                      .reg_data_o(sys_data_o),
43
                      .reg_addr_i(sys_addr_i),
44
                      .reg_sel_i(sys_sel_i),
45
                      .reg_we_i(sys_we_i),
46
                      .reg_cyc_i(sys_cyc_i),
47
                      .reg_stb_i(sys_stb_i),
48
                      .reg_ack_o(sys_ack_o),
49
                      .reg_err_o(sys_err_o),
50
                      .reg_rty_o(sys_rty_o),
51
 
52
                      .reg_clk_i(sys_clk_i),
53
                      .reg_rst_i(sys_rst_i)
54
                    );
55
 
56
  //---------------------------------------------------
57
  // outputs
58
  assign boot_remap   = boot_strap_r[1:0];
59
  assign boot_select  = boot_strap_r[3:2];
60
 
61
endmodule
62
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.