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URL https://opencores.org/ocsvn/or1200_soc/or1200_soc/trunk

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[/] [or1200_soc/] [trunk/] [src/] [soc_top.v] - Blame information for rev 15

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Line No. Rev Author Line
1 2 qaztronic
// --------------------------------------------------------------------
2
//
3
// --------------------------------------------------------------------
4
 
5
 
6
`include "timescale.v"
7
`include "or1200_defines.v"
8
`include "soc_defines.v"
9
 
10
 
11
module soc_top
12
(
13
  ////////////////////////////  UART  ////////////////////////////
14
  output          uart_txd_0,       //  UART Transmitter
15
  input           uart_rxd_0,       //  UART Receiver
16
  ///////////////////////   SDRAM Interface ////////////////////////
17
//   inout [15:0]    DRAM_DQ,        //  SDRAM Data bus 16 Bits
18
//   output  [11:0]  DRAM_ADDR,      //  SDRAM Address bus 12 Bits
19
//   output          DRAM_LDQM,      //  SDRAM Low-byte Data Mask
20
//   output          DRAM_UDQM,      //  SDRAM High-byte Data Mask
21
//   output          DRAM_WE_N,      //  SDRAM Write Enable
22
//   output          DRAM_CAS_N,     //  SDRAM Column Address Strobe
23
//   output          DRAM_RAS_N,     //  SDRAM Row Address Strobe
24
//   output          DRAM_CS_N,      //  SDRAM Chip Select
25
//   output          DRAM_BA_0,      //  SDRAM Bank Address 0
26
//   output          DRAM_BA_1,      //  SDRAM Bank Address 0
27
//   output          DRAM_CLK,       //  SDRAM Clock
28
//   output          DRAM_CKE,       //  SDRAM Clock Enable
29
  ////////////////////////  Flash Interface ////////////////////////
30
  inout [7:0]     fl_dq,          //  flash data bus 8 bits
31
  output  [21:0]  fl_addr,        //  flash address bus 22 bits
32
  output          fl_we_n,        //  flash write enable
33
  output          fl_rst_n,       //  flash reset
34
  output          fl_oe_n,        //  flash output enable
35
  output          fl_ce_n,        //  flash chip enable
36
  ////////////////////////  sram interface  ////////////////////////
37
  inout [15:0]    sram_dq,        //  sram data bus 16 bits
38
  output  [17:0]  sram_addr,      //  sram address bus 18 bits
39
  output          sram_ub_n,      //  sram high-byte data mask
40
  output          sram_lb_n,      //  sram low-byte data mask
41
  output          sram_we_n,      //  sram write enable
42
  output          sram_ce_n,      //  sram chip enable
43
  output          sram_oe_n,      //  sram output enable
44
 
45
  input   [31:0]  gpio_a_aux_i,
46
  input   [31:0]  gpio_a_ext_pad_i,
47
  output  [31:0]  gpio_a_ext_pad_o,
48
  output  [31:0]  gpio_a_ext_padoe_o,
49
 
50
  input   [31:0]  gpio_b_aux_i,
51
  input   [31:0]  gpio_b_ext_pad_i,
52
  output  [31:0]  gpio_b_ext_pad_o,
53
  output  [31:0]  gpio_b_ext_padoe_o,
54
 
55
  input   [31:0]  gpio_c_aux_i,
56
  input   [31:0]  gpio_c_ext_pad_i,
57
  output  [31:0]  gpio_c_ext_pad_o,
58
  output  [31:0]  gpio_c_ext_padoe_o,
59
 
60
  input   [31:0]  gpio_d_aux_i,
61
  input   [31:0]  gpio_d_ext_pad_i,
62
  output  [31:0]  gpio_d_ext_pad_o,
63
  output  [31:0]  gpio_d_ext_padoe_o,
64
 
65
  input   [31:0]  gpio_e_aux_i,
66
  input   [31:0]  gpio_e_ext_pad_i,
67
  output  [31:0]  gpio_e_ext_pad_o,
68
  output  [31:0]  gpio_e_ext_padoe_o,
69
 
70
  input   [31:0]  gpio_f_aux_i,
71
  input   [31:0]  gpio_f_ext_pad_i,
72
  output  [31:0]  gpio_f_ext_pad_o,
73
  output  [31:0]  gpio_f_ext_padoe_o,
74
 
75
  input   [31:0]  gpio_g_aux_i,
76
  input   [31:0]  gpio_g_ext_pad_i,
77
  output  [31:0]  gpio_g_ext_pad_o,
78
  output  [31:0]  gpio_g_ext_padoe_o,
79
 
80
  input [3:0]     boot_strap,
81
 
82
`ifdef USE_DEBUG_0
83
  output [255:0]  debug_0,
84
`endif
85
 
86
  input           sys_clk,
87
  input           sys_rst
88
);
89
 
90
 
91
  //  All inout port turn to tri-state
92
  assign  DRAM_DQ   = 16'hzzzz;
93
  assign  FL_DQ   = 8'hzz;
94
 
95
 
96
  //---------------------------------------------------
97
  // or1200_top
98
  //---------------------------------------------------
99
  parameter dw = `OR1200_OPERAND_WIDTH;
100
  parameter aw = `OR1200_OPERAND_WIDTH;
101
 
102
 
103
  // System
104
  wire      clk_i = sys_clk;
105
  wire      rst_i = sys_rst;
106
 
107
  //---------------------------------------------------
108
  // Instruction WISHBONE interface
109
  wire            iwb_clk_i = sys_clk;
110
  wire            iwb_rst_i = sys_rst;
111
  wire            iwb_ack_i;
112
  wire            iwb_err_i;
113
  wire            iwb_rty_i;
114
  wire  [dw-1:0]  iwb_dat_i;
115
  wire            iwb_cyc_o;
116
  wire  [aw-1:0]  iwb_adr_o;
117
  wire            iwb_stb_o;
118
  wire            iwb_we_o;
119
  wire  [3:0]     iwb_sel_o;
120
  wire  [dw-1:0]  iwb_dat_o;
121
  wire            iwb_cab_o;
122
 
123
  //---------------------------------------------------
124
  // Data WISHBONE interface
125
  wire            dwb_clk_i = sys_clk;
126
  wire            dwb_rst_i = sys_rst;
127
  wire            dwb_ack_i;
128
  wire            dwb_err_i;
129
  wire            dwb_rty_i;
130
  wire  [dw-1:0]  dwb_dat_i;
131
  wire            dwb_cyc_o;
132
  wire  [aw-1:0]  dwb_adr_o;
133
  wire            dwb_stb_o;
134
  wire            dwb_we_o;
135
  wire  [3:0]     dwb_sel_o;
136
  wire  [dw-1:0]  dwb_dat_o;
137
  wire            dwb_cab_o;
138
 
139
  or1200_top i_or1200_top(
140
                          //---------------------------------------------------
141
                          // Instruction WISHBONE interface
142
                          .iwb_clk_i(iwb_clk_i),  // clock input
143
                          .iwb_rst_i(iwb_rst_i),  // reset input
144
                          .iwb_ack_i(iwb_ack_i),  // normal termination
145
                          .iwb_err_i(iwb_err_i),  // termination w/ error
146
                          .iwb_rty_i(iwb_rty_i),  // termination w/ retry
147
                          .iwb_dat_i(iwb_dat_i),  // input data bus
148
                          .iwb_cyc_o(iwb_cyc_o),  // cycle valid output
149
                          .iwb_adr_o(iwb_adr_o),  // address bus outputs
150
                          .iwb_stb_o(iwb_stb_o),  // strobe output
151
                          .iwb_we_o(iwb_we_o),  // indicates write transfer
152
                          .iwb_sel_o(iwb_sel_o),  // byte select outputs
153
                          .iwb_dat_o(iwb_dat_o),  // output data bus
154
  `ifdef OR1200_WB_CAB
155
                          .iwb_cab_o(iwb_cab_o),  // indicates consecutive address burst
156
  `endif
157
  `ifdef OR1200_WB_B3
158
                          .iwb_cti_o(iwb_cti_o),  // cycle type identifier
159
                          .iwb_bte_o(iwb_bte_o),  // burst type extension
160
  `endif
161
 
162
                          //---------------------------------------------------
163
                          // Data WISHBONE interface
164
                          .dwb_clk_i(dwb_clk_i),  // clock input
165
                          .dwb_rst_i(dwb_rst_i),  // reset input
166
                          .dwb_ack_i(dwb_ack_i),  // normal termination
167
                          .dwb_err_i(dwb_err_i),  // termination w/ error
168
                          .dwb_rty_i(dwb_rty_i),  // termination w/ retry
169
                          .dwb_dat_i(dwb_dat_i),  // input data bus
170
                          .dwb_cyc_o(dwb_cyc_o),  // cycle valid output
171
                          .dwb_adr_o(dwb_adr_o),  // address bus outputs
172
                          .dwb_stb_o(dwb_stb_o),  // strobe output
173
                          .dwb_we_o(dwb_we_o),  // indicates write transfer
174
                          .dwb_sel_o(dwb_sel_o),  // byte select outputs
175
                          .dwb_dat_o(dwb_dat_o),  // output data bus
176
  `ifdef OR1200_WB_CAB
177
                          .dwb_cab_o(dwb_cab_o),  // indicates consecutive address burst
178
  `endif
179
  `ifdef OR1200_WB_B3
180
                          .dwb_cti_o(dwb_cti_o),  // cycle type identifier
181
                          .dwb_bte_o(dwb_bte_o),  // burst type extension
182
  `endif
183
 
184
                          //---------------------------------------------------
185
                          // External Debug Interface
186
                          .dbg_stall_i(1'b0), // External Stall Input
187
//                           .dbg_ewt_i(dbg_ewt_i), // External Watchpoint Trigger Input
188
//                           .dbg_lss_o(dbg_lss_o), // External Load/Store Unit Status
189
//                           .dbg_is_o(dbg_is_o), // External Insn Fetch Status
190
//                           .dbg_wp_o(dbg_wp_o), // Watchpoints Outputs
191
//                           .dbg_bp_o(dbg_bp_o), // Breakpoint Output
192
//                           .dbg_stb_i(dbg_stb_i),      // External Address/Data Strobe
193
//                           .dbg_we_i(dbg_we_i),       // External Write Enable
194
//                           .dbg_adr_i(dbg_adr_i), // External Address Input
195
//                           .dbg_dat_i(dbg_dat_i), // External Data Input
196
//                           .dbg_dat_o(dbg_dat_o), // External Data Output
197
//                           .dbg_ack_o(dbg_ack_o), // External Data Acknowledge (not WB compatible)
198
 
199
 
200
                          //---------------------------------------------------
201
                          // RAM BIST
202
  `ifdef OR1200_BIST
203
                          .mbist_si_i(mbist_si_i),
204
                          .mbist_ctrl_i(mbist_ctrl_i),
205
                          .mbist_so_o(mbist_so_o),
206
  `endif
207
 
208
                        //---------------------------------------------------
209
                        // Power Management
210
//                         .pm_cpustall_i(pm_cpustall_i),
211
//                         .pm_clksd_o(pm_clksd_o),
212
//                         .pm_dc_gate_o(pm_dc_gate_o),
213
//                         .pm_ic_gate_o(pm_ic_gate_o),
214
//                         .pm_dmmu_gate_o(pm_dmmu_gate_o),
215
//                         .pm_immu_gate_o(pm_immu_gate_o),
216
//                         .pm_tt_gate_o(pm_tt_gate_o),
217
//                         .pm_cpu_gate_o(pm_cpu_gate_o),
218
//                         .pm_wakeup_o(pm_wakeup_o),
219
//                         .pm_lvolt_o(pm_lvolt_o),
220
//
221
                        //---------------------------------------------------
222
                        // System
223
//                         .clmode_i(clmode_i), // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
224
//                         .pic_ints_i(pic_ints_i),
225
                          .clk_i(clk_i),
226
                          .rst_i(rst_i)
227
                        );
228
 
229
 
230
  //---------------------------------------------------
231
  // wb_conmax_top
232
 
233
  // Slave 0 Interface
234
  parameter   sw = dw / 8;  // Number of Select Lines
235
 
236
  wire  [dw-1:0]  s0_data_i;
237
  wire  [dw-1:0]  s0_data_o;
238
  wire  [aw-1:0]  s0_addr_o;
239
  wire  [sw-1:0]  s0_sel_o;
240
  wire            s0_we_o;
241
  wire            s0_cyc_o;
242
  wire            s0_stb_o;
243
  wire            s0_ack_i;
244
  wire            s0_err_i;
245
  wire            s0_rty_i;
246
 
247
  wire  [dw-1:0]  s1_data_i;
248
  wire  [dw-1:0]  s1_data_o;
249
  wire  [aw-1:0]  s1_addr_o;
250
  wire  [sw-1:0]  s1_sel_o;
251
  wire            s1_we_o;
252
  wire            s1_cyc_o;
253
  wire            s1_stb_o;
254
  wire            s1_ack_i;
255
  wire            s1_err_i;
256
  wire            s1_rty_i;
257
 
258
  wire  [dw-1:0]  s2_data_i;
259
  wire  [dw-1:0]  s2_data_o;
260
  wire  [aw-1:0]  s2_addr_o;
261
  wire  [sw-1:0]  s2_sel_o;
262
  wire            s2_we_o;
263
  wire            s2_cyc_o;
264
  wire            s2_stb_o;
265
  wire            s2_ack_i;
266
  wire            s2_err_i;
267
  wire            s2_rty_i;
268
 
269
  wire  [dw-1:0]  s3_data_i;
270
  wire  [dw-1:0]  s3_data_o;
271
  wire  [aw-1:0]  s3_addr_o;
272
  wire  [sw-1:0]  s3_sel_o;
273
  wire            s3_we_o;
274
  wire            s3_cyc_o;
275
  wire            s3_stb_o;
276
  wire            s3_ack_i;
277
  wire            s3_err_i;
278
  wire            s3_rty_i;
279
 
280
  wire  [dw-1:0]  s4_data_i;
281
  wire  [dw-1:0]  s4_data_o;
282
  wire  [aw-1:0]  s4_addr_o;
283
  wire  [sw-1:0]  s4_sel_o;
284
  wire            s4_we_o;
285
  wire            s4_cyc_o;
286
  wire            s4_stb_o;
287
  wire            s4_ack_i;
288
  wire            s4_err_i;
289
  wire            s4_rty_i;
290
 
291
  wire  [dw-1:0]  s5_data_i;
292
  wire  [dw-1:0]  s5_data_o;
293
  wire  [aw-1:0]  s5_addr_o;
294
  wire  [sw-1:0]  s5_sel_o;
295
  wire            s5_we_o;
296
  wire            s5_cyc_o;
297
  wire            s5_stb_o;
298
  wire            s5_ack_i;
299
  wire            s5_err_i;
300
  wire            s5_rty_i;
301
 
302
  wire  [dw-1:0]  s6_data_i;
303
  wire  [dw-1:0]  s6_data_o;
304
  wire  [aw-1:0]  s6_addr_o;
305
  wire  [sw-1:0]  s6_sel_o;
306
  wire            s6_we_o;
307
  wire            s6_cyc_o;
308
  wire            s6_stb_o;
309
  wire            s6_ack_i;
310
  wire            s6_err_i;
311
  wire            s6_rty_i;
312
 
313
  wire  [1:0]     boot_remap;
314
  wire  [aw-1:0]  iwb_remap_adr;
315
  wire  [aw-1:0]  dwb_remap_adr;
316
 
317
  wb_conmax_top
318
    i_wb_conmax_top(
319
                      // Master 0 Interface
320
                      .m0_data_i(iwb_dat_o),
321
                      .m0_data_o(iwb_dat_i),
322
                      .m0_addr_i(iwb_adr_o),
323
                      .m0_sel_i(iwb_sel_o),
324
                      .m0_we_i(iwb_we_o),
325
                      .m0_cyc_i(iwb_cyc_o),
326
                      .m0_stb_i(iwb_stb_o),
327
                      .m0_ack_o(iwb_ack_i),
328
                      .m0_err_o(iwb_err_i),
329
                      .m0_rty_o(iwb_rty_i),
330
                      // Master 1 Interface
331
                      .m1_data_i(dwb_dat_o),
332
                      .m1_data_o(dwb_dat_i),
333
                      .m1_addr_i(dwb_adr_o),
334
                      .m1_sel_i(dwb_sel_o),
335
                      .m1_we_i(dwb_we_o),
336
                      .m1_cyc_i(dwb_cyc_o),
337
                      .m1_stb_i(dwb_stb_o),
338
                      .m1_ack_o(dwb_ack_i),
339
                      .m1_err_o(dwb_err_i),
340
                      .m1_rty_o(dwb_rty_i),
341
                      // Master 2 Interface
342
                      .m2_data_i(32'h0000_0000),
343
                      .m2_addr_i(32'h0000_0000),
344
                      .m2_sel_i(4'h0),
345
                      .m2_we_i(1'b0),
346
                      .m2_cyc_i(1'b0),
347
                      .m2_stb_i(1'b0),
348
                      // Master 3 Interface
349
                      .m3_data_i(32'h0000_0000),
350
                      .m3_addr_i(32'h0000_0000),
351
                      .m3_sel_i(4'h0),
352
                      .m3_we_i(1'b0),
353
                      .m3_cyc_i(1'b0),
354
                      .m3_stb_i(1'b0),
355
                      // Master 4 Interface
356
                      .m4_data_i(32'h0000_0000),
357
                      .m4_addr_i(32'h0000_0000),
358
                      .m4_sel_i(4'h0),
359
                      .m4_we_i(1'b0),
360
                      .m4_cyc_i(1'b0),
361
                      .m4_stb_i(1'b0),
362
                      // Master 5 Interface
363
                      .m5_data_i(32'h0000_0000),
364
                      .m5_addr_i(32'h0000_0000),
365
                      .m5_sel_i(4'h0),
366
                      .m5_we_i(1'b0),
367
                      .m5_cyc_i(1'b0),
368
                      .m5_stb_i(1'b0),
369
                      // Master 6 Interface
370
                      .m6_data_i(32'h0000_0000),
371
                      .m6_addr_i(32'h0000_0000),
372
                      .m6_sel_i(4'h0),
373
                      .m6_we_i(1'b0),
374
                      .m6_cyc_i(1'b0),
375
                      .m6_stb_i(1'b0),
376
                      // Master 7 Interface
377
                      .m7_data_i(32'h0000_0000),
378
                      .m7_addr_i(32'h0000_0000),
379
                      .m7_sel_i(4'h0),
380
                      .m7_we_i(1'b0),
381
                      .m7_cyc_i(1'b0),
382
                      .m7_stb_i(1'b0),
383
 
384
                      // Slave 0 Interface
385
                      .s0_data_i(s0_data_i),
386
                      .s0_data_o(s0_data_o),
387
                      .s0_addr_o(s0_addr_o),
388
                      .s0_sel_o(s0_sel_o),
389
                      .s0_we_o(s0_we_o),
390
                      .s0_cyc_o(s0_cyc_o),
391
                      .s0_stb_o(s0_stb_o),
392
                      .s0_ack_i(s0_ack_i),
393
                      .s0_err_i(s0_err_i),
394
                      .s0_rty_i(s0_rty_i),
395
                      // Slave 1 Interface
396
                      .s1_data_i(s1_data_i),
397
                      .s1_data_o(s1_data_o),
398
                      .s1_addr_o(s1_addr_o),
399
                      .s1_sel_o(s1_sel_o),
400
                      .s1_we_o(s1_we_o),
401
                      .s1_cyc_o(s1_cyc_o),
402
                      .s1_stb_o(s1_stb_o),
403
                      .s1_ack_i(s1_ack_i),
404
                      .s1_err_i(s1_err_i),
405
                      .s1_rty_i(s1_rty_i),
406
                      // Slave 2 Interface
407
                      .s2_data_i(s2_data_i),
408
                      .s2_data_o(s2_data_o),
409
                      .s2_addr_o(s2_addr_o),
410
                      .s2_sel_o(s2_sel_o),
411
                      .s2_we_o(s2_we_o),
412
                      .s2_cyc_o(s2_cyc_o),
413
                      .s2_stb_o(s2_stb_o),
414
                      .s2_ack_i(s2_ack_i),
415
                      .s2_err_i(s2_err_i),
416
                      .s2_rty_i(s2_rty_i),
417
                      // Slave 3 Interface
418
                      .s3_data_i(s3_data_i),
419
                      .s3_data_o(s3_data_o),
420
                      .s3_addr_o(s3_addr_o),
421
                      .s3_sel_o(s3_sel_o),
422
                      .s3_we_o(s3_we_o),
423
                      .s3_cyc_o(s3_cyc_o),
424
                      .s3_stb_o(s3_stb_o),
425
                      .s3_ack_i(s3_ack_i),
426
                      .s3_err_i(s3_err_i),
427
                      .s3_rty_i(s3_rty_i),
428
                      // Slave 4 Interface
429
                      .s4_data_i(s4_data_i),
430
                      .s4_data_o(s4_data_o),
431
                      .s4_addr_o(s4_addr_o),
432
                      .s4_sel_o(s4_sel_o),
433
                      .s4_we_o(s4_we_o),
434
                      .s4_cyc_o(s4_cyc_o),
435
                      .s4_stb_o(s4_stb_o),
436
                      .s4_ack_i(s4_ack_i),
437
                      .s4_err_i(s4_err_i),
438
                      .s4_rty_i(s4_rty_i),
439
                      // Slave 5 Interface
440
                      .s5_data_i(s5_data_i),
441
                      .s5_data_o(s5_data_o),
442
                      .s5_addr_o(s5_addr_o),
443
                      .s5_sel_o(s5_sel_o),
444
                      .s5_we_o(s5_we_o),
445
                      .s5_cyc_o(s5_cyc_o),
446
                      .s5_stb_o(s5_stb_o),
447
                      .s5_ack_i(s5_ack_i),
448
                      .s5_err_i(s5_err_i),
449
                      .s5_rty_i(s5_rty_i),
450
                      // Slave 6 Interface
451
                      .s6_data_i(s6_data_i),
452
                      .s6_data_o(s6_data_o),
453
                      .s6_addr_o(s6_addr_o),
454
                      .s6_sel_o(s6_sel_o),
455
                      .s6_we_o(s6_we_o),
456
                      .s6_cyc_o(s6_cyc_o),
457
                      .s6_stb_o(s6_stb_o),
458
                      .s6_ack_i(s6_ack_i),
459
                      .s6_err_i(s6_err_i),
460
                      .s6_rty_i(s6_rty_i),
461
                      // Slave 7 Interface
462
                      .s7_data_i(32'h0000_0000),
463
                      .s7_ack_i(1'b0),
464
                      .s7_err_i(1'b0),
465
                      .s7_rty_i(1'b0),
466
                      // Slave 8 Interface
467
                      .s8_data_i(32'h0000_0000),
468
                      .s8_ack_i(1'b0),
469
                      .s8_err_i(1'b0),
470
                      .s8_rty_i(1'b0),
471
                      // Slave 9 Interface
472
                      .s9_data_i(32'h0000_0000),
473
                      .s9_ack_i(1'b0),
474
                      .s9_err_i(1'b0),
475
                      .s9_rty_i(1'b0),
476
                      // Slave 10 Interface
477
                      .s10_data_i(32'h0000_0000),
478
                      .s10_ack_i(1'b0),
479
                      .s10_err_i(1'b0),
480
                      .s10_rty_i(1'b0),
481
                      // Slave 11 Interface
482
                      .s11_data_i(32'h0000_0000),
483
                      .s11_ack_i(1'b0),
484
                      .s11_err_i(1'b0),
485
                      .s11_rty_i(1'b0),
486
                      // Slave 12 Interface
487
                      .s12_data_i(32'h0000_0000),
488
                      .s12_ack_i(1'b0),
489
                      .s12_err_i(1'b0),
490
                      .s12_rty_i(1'b0),
491
                      // Slave 13 Interface
492
                      .s13_data_i(32'h0000_0000),
493
                      .s13_ack_i(1'b0),
494
                      .s13_err_i(1'b0),
495
                      .s13_rty_i(1'b0),
496
                      // Slave 14 Interface
497
                      .s14_data_i(32'h0000_0000),
498
                      .s14_ack_i(1'b0),
499
                      .s14_err_i(1'b0),
500
                      .s14_rty_i(1'b0),
501
                      // Slave 15 Interface
502
                      .s15_data_i(32'h0000_0000),
503
                      .s15_ack_i(1'b0),
504
                      .s15_err_i(1'b0),
505
                      .s15_rty_i(1'b0),
506
 
507
                      .clk_i(clk_i),
508
                      .rst_i(rst_i)
509
                    );
510
 
511
  //---------------------------------------------------
512
  // soc_boot
513
  wire  [1:0] boot_select;
514
 
515
  soc_boot i_soc_boot(
516
                      .mem_data_i(s0_data_o),
517
                      .mem_data_o(s0_data_i),
518
                      .mem_addr_i(s0_addr_o),
519
                      .mem_sel_i(s0_sel_o),
520
                      .mem_we_i(s0_we_o),
521
                      .mem_cyc_i(s0_cyc_o),
522
                      .mem_stb_i(s0_stb_o),
523
                      .mem_ack_o(s0_ack_i),
524
                      .mem_err_o(s0_err_i),
525
                      .mem_rty_o(s0_rty_i),
526
 
527
                      .boot_select(boot_select),
528
 
529
                      .mem_clk_i(clk_i),
530
                      .mem_rst_i(rst_i)
531
                    );
532
 
533
 
534
  //---------------------------------------------------
535
  // soc_mem_bank_1
536
  soc_mem_bank_1
537
    i_soc_mem_bank_1(
538
                      .mem_data_i(s1_data_o),
539
                      .mem_data_o(s1_data_i),
540
                      .mem_addr_i(s1_addr_o),
541
                      .mem_sel_i(s1_sel_o),
542
                      .mem_we_i(s1_we_o),
543
                      .mem_cyc_i(s1_cyc_o),
544
                      .mem_stb_i(s1_stb_o),
545
                      .mem_ack_o(s1_ack_i),
546
                      .mem_err_o(s1_err_i),
547
                      .mem_rty_o(s1_rty_i),
548
 
549
                      .mem_clk_i(clk_i),
550
                      .mem_rst_i(rst_i)
551
                    );
552
 
553
  //---------------------------------------------------
554
  // soc_mem_bank_2
555
  soc_mem_bank_2
556
    i_soc_mem_bank_2(
557
                      .mem_data_i(s2_data_o),
558
                      .mem_data_o(s2_data_i),
559
                      .mem_addr_i(s2_addr_o),
560
                      .mem_sel_i(s2_sel_o),
561
                      .mem_we_i(s2_we_o),
562
                      .mem_cyc_i(s2_cyc_o),
563
                      .mem_stb_i(s2_stb_o),
564
                      .mem_ack_o(s2_ack_i),
565
                      .mem_err_o(s2_err_i),
566
                      .mem_rty_o(s2_rty_i),
567
 
568
                      .mem_clk_i(clk_i),
569
                      .mem_rst_i(rst_i)
570
                    );
571
 
572
  //---------------------------------------------------
573
  // soc_mem_bank_3
574
  soc_mem_bank_3
575
    i_soc_mem_bank_3(
576
                      .mem_data_i(s3_data_o),
577
                      .mem_data_o(s3_data_i),
578
                      .mem_addr_i(s3_addr_o),
579
                      .mem_sel_i(s3_sel_o),
580
                      .mem_we_i(s3_we_o),
581
                      .mem_cyc_i(s3_cyc_o),
582
                      .mem_stb_i(s3_stb_o),
583
                      .mem_ack_o(s3_ack_i),
584
                      .mem_err_o(s3_err_i),
585
                      .mem_rty_o(s3_rty_i),
586
 
587
                      .mem_clk_i(clk_i),
588
                      .mem_rst_i(rst_i)
589
                    );
590
 
591
  //---------------------------------------------------
592
  // soc_system
593
  soc_system
594
    i_soc_system(
595
                  .sys_data_i(s4_data_o),
596
                  .sys_data_o(s4_data_i),
597
                  .sys_addr_i(s4_addr_o),
598
                  .sys_sel_i(s4_sel_o),
599
                  .sys_we_i(s4_we_o),
600
                  .sys_cyc_i(s4_cyc_o),
601
                  .sys_stb_i(s4_stb_o),
602
                  .sys_ack_o(s4_ack_i),
603
                  .sys_err_o(s4_err_i),
604
                  .sys_rty_o(s4_rty_i),
605
 
606
                  .boot_strap(boot_strap),
607
                  .boot_select(boot_select),
608
                  .boot_remap(boot_remap),
609
 
610
                  .sys_clk_i(clk_i),
611
                  .sys_rst_i(rst_i)
612
                );
613
 
614
  //---------------------------------------------------
615
  // peripherals
616
  soc_peripherals
617
    i_soc_peripherals(
618
                        .peri_data_i(s5_data_o),
619
                        .peri_data_o(s5_data_i),
620
                        .peri_addr_i(s5_addr_o),
621
                        .peri_sel_i(s5_sel_o),
622
                        .peri_we_i(s5_we_o),
623
                        .peri_cyc_i(s5_cyc_o),
624
                        .peri_stb_i(s5_stb_o),
625
                        .peri_ack_o(s5_ack_i),
626
                        .peri_err_o(s5_err_i),
627
                        .peri_rty_o(s5_rty_i),
628
 
629
                        .uart_txd_0(uart_txd_0),
630
                        .uart_rxd_0(uart_rxd_0),
631
 
632
                        .peri_clk_i(clk_i),
633
                        .peri_rst_i(rst_i)
634
                      );
635
 
636
  //---------------------------------------------------
637
  // gpio
638
  soc_gpio
639
    i_soc_gpio(
640
                  .gpio_data_i(s6_data_o),
641
                  .gpio_data_o(s6_data_i),
642
                  .gpio_addr_i(s6_addr_o),
643
                  .gpio_sel_i(s6_sel_o),
644
                  .gpio_we_i(s6_we_o),
645
                  .gpio_cyc_i(s6_cyc_o),
646
                  .gpio_stb_i(s6_stb_o),
647
                  .gpio_ack_o(s6_ack_i),
648
                  .gpio_err_o(s6_err_i),
649
                  .gpio_rty_o(s6_rty_i),
650
 
651
                  .gpio_a_aux_i(gpio_a_aux_i),
652
                  .gpio_a_ext_pad_i(gpio_a_ext_pad_i),
653
                  .gpio_a_ext_pad_o(gpio_a_ext_pad_o),
654
                  .gpio_a_ext_padoe_o(gpio_a_ext_padoe_o),
655
                  .gpio_a_inta_o(),
656
 
657
                  .gpio_b_aux_i(gpio_b_aux_i),
658
                  .gpio_b_ext_pad_i(gpio_b_ext_pad_i),
659
                  .gpio_b_ext_pad_o(gpio_b_ext_pad_o),
660
                  .gpio_b_ext_padoe_o(gpio_b_ext_padoe_o),
661
                  .gpio_b_inta_o(),
662
 
663
                  .gpio_c_aux_i(gpio_c_aux_i),
664
                  .gpio_c_ext_pad_i(gpio_c_ext_pad_i),
665
                  .gpio_c_ext_pad_o(gpio_c_ext_pad_o),
666
                  .gpio_c_ext_padoe_o(gpio_c_ext_padoe_o),
667
                  .gpio_c_inta_o(),
668
 
669
                  .gpio_d_aux_i(gpio_d_aux_i),
670
                  .gpio_d_ext_pad_i(gpio_d_ext_pad_i),
671
                  .gpio_d_ext_pad_o(gpio_d_ext_pad_o),
672
                  .gpio_d_ext_padoe_o(gpio_d_ext_padoe_o),
673
                  .gpio_d_inta_o(),
674
 
675
                  .gpio_e_aux_i(gpio_e_aux_i),
676
                  .gpio_e_ext_pad_i(gpio_e_ext_pad_i),
677
                  .gpio_e_ext_pad_o(gpio_e_ext_pad_o),
678
                  .gpio_e_ext_padoe_o(gpio_e_ext_padoe_o),
679
                  .gpio_e_inta_o(),
680
 
681
                  .gpio_f_aux_i(gpio_f_aux_i),
682
                  .gpio_f_ext_pad_i(gpio_f_ext_pad_i),
683
                  .gpio_f_ext_pad_o(gpio_f_ext_pad_o),
684
                  .gpio_f_ext_padoe_o(gpio_f_ext_padoe_o),
685
                  .gpio_f_inta_o(),
686
 
687
                  .gpio_g_aux_i(gpio_g_aux_i),
688
                  .gpio_g_ext_pad_i(gpio_g_ext_pad_i),
689
                  .gpio_g_ext_pad_o(gpio_g_ext_pad_o),
690
                  .gpio_g_ext_padoe_o(gpio_g_ext_padoe_o),
691
                  .gpio_g_inta_o(),
692
 
693
                  .gpio_clk_i(clk_i),
694
                  .gpio_rst_i(rst_i)
695
                );
696
 
697
  //---------------------------------------------------
698
  // debug_0
699
`ifdef USE_DEBUG_0
700
  assign debug_0 = {
701
                      iwb_clk_i,
702
                      iwb_rst_i,
703
                      iwb_ack_i,
704
                      iwb_err_i,
705
                      iwb_rty_i,
706
                      iwb_cyc_o,
707
                      iwb_stb_o,
708
                      iwb_we_o,
709
                      iwb_sel_o,
710
                      iwb_cab_o,
711
                      dwb_clk_i,
712
                      dwb_rst_i,
713
                      dwb_ack_i,
714
                      dwb_err_i,
715
                      dwb_rty_i,
716
                      dwb_cyc_o,
717
                      dwb_stb_o,
718
                      dwb_we_o,
719
                      dwb_sel_o,
720
                      dwb_cab_o,
721
                      iwb_adr_o,
722
                      iwb_dat_i,
723
                      iwb_dat_o,
724
                      dwb_adr_o,
725
                      dwb_dat_i,
726
                      dwb_dat_o
727
                    };
728
`endif
729
 
730
endmodule
731
 
732
 

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