OpenCores
URL https://opencores.org/ocsvn/or1200_soc/or1200_soc/trunk

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[/] [or1200_soc/] [trunk/] [sw/] [ecos-3.0_diff.txt] - Blame information for rev 25

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1 25 qaztronic
diff -NaurbBw /opt/ecos-3.0/packages/devs/flash/openrisc/orp/v3_0/ChangeLog ./ecos-3.0/packages/devs/flash/openrisc/orp/v3_0/ChangeLog
2
--- /opt/ecos-3.0/packages/devs/flash/openrisc/orp/v3_0/ChangeLog       1969-12-31 16:00:00.000000000 -0800
3
+++ ./ecos-3.0/packages/devs/flash/openrisc/orp/v3_0/ChangeLog  2009-09-16 14:04:52.000000000 -0700
4
@@ -0,0 +1,40 @@
5
+2003-03-06  Scott Furman 
6
+       * src/openrisc_orp_flash.c, cdl/flash_openrisc_orp.cdl
7
+         New package:  Flash programming for AMD AM29LVxxxxx devices
8
+         used with OpenRISC Reference Platform (ORP).
9
+
10
+//===========================================================================
11
+//####ECOSGPLCOPYRIGHTBEGIN####
12
+// -------------------------------------------
13
+// This file is part of eCos, the Embedded Configurable Operating System.
14
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15
+// Copyright (C) 2002 Gary Thomas
16
+//
17
+// eCos is free software; you can redistribute it and/or modify it under
18
+// the terms of the GNU General Public License as published by the Free
19
+// Software Foundation; either version 2 or (at your option) any later version.
20
+//
21
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
22
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
23
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
24
+// for more details.
25
+//
26
+// You should have received a copy of the GNU General Public License along
27
+// with eCos; if not, write to the Free Software Foundation, Inc.,
28
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
29
+//
30
+// As a special exception, if other files instantiate templates or use macros
31
+// or inline functions from this file, or you compile this file and link it
32
+// with other works to produce a work based on this file, this file does not
33
+// by itself cause the resulting work to be covered by the GNU General Public
34
+// License. However the source code for this file must still be made available
35
+// in accordance with section (3) of the GNU General Public License.
36
+//
37
+// This exception does not invalidate any other reasons why a work based on
38
+// this file might be covered by the GNU General Public License.
39
+//
40
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
41
+// at http://sources.redhat.com/ecos/ecos-license/
42
+// -------------------------------------------
43
+//####ECOSGPLCOPYRIGHTEND####
44
+//===========================================================================
45
diff -NaurbBw /opt/ecos-3.0/packages/devs/flash/openrisc/orp/v3_0/cdl/flash_openrisc_orp.cdl ./ecos-3.0/packages/devs/flash/openrisc/orp/v3_0/cdl/flash_openrisc_orp.cdl
46
--- /opt/ecos-3.0/packages/devs/flash/openrisc/orp/v3_0/cdl/flash_openrisc_orp.cdl      1969-12-31 16:00:00.000000000 -0800
47
+++ ./ecos-3.0/packages/devs/flash/openrisc/orp/v3_0/cdl/flash_openrisc_orp.cdl 2009-09-16 14:04:52.000000000 -0700
48
@@ -0,0 +1,70 @@
49
+# ====================================================================
50
+#
51
+#      flash_openrisc_orp.cdl
52
+#
53
+#      FLASH memory - Hardware support for OpenRISC Reference Platform
54
+#
55
+# ====================================================================
56
+#####ECOSGPLCOPYRIGHTBEGIN####
57
+## -------------------------------------------
58
+## This file is part of eCos, the Embedded Configurable Operating System.
59
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
60
+##
61
+## eCos is free software; you can redistribute it and/or modify it under
62
+## the terms of the GNU General Public License as published by the Free
63
+## Software Foundation; either version 2 or (at your option) any later version.
64
+##
65
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
66
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
67
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
68
+## for more details.
69
+##
70
+## You should have received a copy of the GNU General Public License along
71
+## with eCos; if not, write to the Free Software Foundation, Inc.,
72
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
73
+##
74
+## As a special exception, if other files instantiate templates or use macros
75
+## or inline functions from this file, or you compile this file and link it
76
+## with other works to produce a work based on this file, this file does not
77
+## by itself cause the resulting work to be covered by the GNU General Public
78
+## License. However the source code for this file must still be made available
79
+## in accordance with section (3) of the GNU General Public License.
80
+##
81
+## This exception does not invalidate any other reasons why a work based on
82
+## this file might be covered by the GNU General Public License.
83
+##
84
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
85
+## at http://sources.redhat.com/ecos/ecos-license/
86
+## -------------------------------------------
87
+#####ECOSGPLCOPYRIGHTEND####
88
+# ====================================================================
89
+######DESCRIPTIONBEGIN####
90
+#
91
+# Author(s):      jskov
92
+# Contributors:   jskov
93
+# Date:           2000-12-05
94
+#
95
+#####DESCRIPTIONEND####
96
+#
97
+# ====================================================================
98
+
99
+cdl_package CYGPKG_DEVS_FLASH_OPENRISC_ORP {
100
+    display       "Flash memory support for OpenRISC ORP"
101
+
102
+    parent        CYGPKG_IO_FLASH
103
+    active_if     CYGPKG_IO_FLASH
104
+    requires      CYGPKG_HAL_OPENRISC_ORP
105
+
106
+    implements    CYGHWR_IO_FLASH_DEVICE
107
+
108
+    compile       openrisc_orp_flash.c
109
+
110
+    # Arguably this should do in the generic package
111
+    # but then there is a logic loop so you can never enable it.
112
+    cdl_interface CYGINT_DEVS_FLASH_AMD_AM29XXXXX_REQUIRED {
113
+        display   "AMD AM29LV160 driver required"
114
+    }
115
+
116
+    implements    CYGINT_DEVS_FLASH_AMD_AM29XXXXX_REQUIRED
117
+    requires      CYGHWR_DEVS_FLASH_AMD_AM29LV160
118
+}
119
diff -NaurbBw /opt/ecos-3.0/packages/devs/flash/openrisc/orp/v3_0/src/openrisc_orp_flash.c ./ecos-3.0/packages/devs/flash/openrisc/orp/v3_0/src/openrisc_orp_flash.c
120
--- /opt/ecos-3.0/packages/devs/flash/openrisc/orp/v3_0/src/openrisc_orp_flash.c        1969-12-31 16:00:00.000000000 -0800
121
+++ ./ecos-3.0/packages/devs/flash/openrisc/orp/v3_0/src/openrisc_orp_flash.c   2009-09-16 14:04:52.000000000 -0700
122
@@ -0,0 +1,70 @@
123
+//==========================================================================
124
+//
125
+//      openrisc_orp_flash.c
126
+//
127
+//      Flash programming for AMD AM29LVxxxxx devices connected to OpenRISC
128
+//      Reference Platform (ORP).
129
+//
130
+//==========================================================================
131
+//####ECOSGPLCOPYRIGHTBEGIN####
132
+// -------------------------------------------
133
+// This file is part of eCos, the Embedded Configurable Operating System.
134
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
135
+//
136
+// eCos is free software; you can redistribute it and/or modify it under
137
+// the terms of the GNU General Public License as published by the Free
138
+// Software Foundation; either version 2 or (at your option) any later version.
139
+//
140
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
141
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
142
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
143
+// for more details.
144
+//
145
+// You should have received a copy of the GNU General Public License along
146
+// with eCos; if not, write to the Free Software Foundation, Inc.,
147
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
148
+//
149
+// As a special exception, if other files instantiate templates or use macros
150
+// or inline functions from this file, or you compile this file and link it
151
+// with other works to produce a work based on this file, this file does not
152
+// by itself cause the resulting work to be covered by the GNU General Public
153
+// License. However the source code for this file must still be made available
154
+// in accordance with section (3) of the GNU General Public License.
155
+//
156
+// This exception does not invalidate any other reasons why a work based on
157
+// this file might be covered by the GNU General Public License.
158
+//
159
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
160
+// at http://sources.redhat.com/ecos/ecos-license/
161
+// -------------------------------------------
162
+//####ECOSGPLCOPYRIGHTEND####
163
+//==========================================================================
164
+//#####DESCRIPTIONBEGIN####
165
+//
166
+// Author(s):    jskov
167
+// Contributors: jskov
168
+// Date:         2001-05-22
169
+// Purpose:
170
+// Description:
171
+//
172
+//####DESCRIPTIONEND####
173
+//
174
+//==========================================================================
175
+
176
+//--------------------------------------------------------------------------
177
+// Device properties
178
+
179
+#define CYGNUM_FLASH_INTERLEAVE        (1)
180
+#define CYGNUM_FLASH_SERIES    (1)
181
+#define CYGNUM_FLASH_WIDTH      (16)
182
+#define CYGNUM_FLASH_BASE      (0xF0000000)
183
+
184
+//--------------------------------------------------------------------------
185
+// Platform specific extras
186
+
187
+//--------------------------------------------------------------------------
188
+// Now include the driver code.
189
+#include "cyg/io/flash_am29xxxxx.inl"
190
+
191
+// ------------------------------------------------------------------------
192
+// EOF mips_ocelot_flash.c
193
diff -NaurbBw /opt/ecos-3.0/packages/ecos.db ./ecos-3.0/packages/ecos.db
194
--- /opt/ecos-3.0/packages/ecos.db      2009-03-27 01:58:47.000000000 -0700
195
+++ ./ecos-3.0/packages/ecos.db 2010-02-05 16:35:58.480650900 -0800
196
@@ -270,6 +270,17 @@
197
           on the PMC-Sierra Ocelot platform."
198
 }
199
 
200
+package CYGPKG_DEVS_FLASH_OPENRISC_ORP {
201
+       alias           { "Support for flash memory for OpenRISC Reference Platform (ORP)"
202
+                          flash_openrisc_orp }
203
+       directory       devs/flash/openrisc/orp
204
+       script          flash_openrisc_orp.cdl
205
+       hardware
206
+        description "
207
+           This package contains hardware support for AM29xxxxx flash memory
208
+          on the OpenRISC Reference Platform."
209
+}
210
+
211
 package CYGPKG_DEVS_FLASH_MIPS_VRC437X {
212
        alias           { "Support for flash memory on VRC437X boards" flash_vrc437x }
213
        directory       devs/flash/mips/vrc437x
214
@@ -6152,6 +6163,63 @@
215
             eCos on a Allied Telesyn TS1000 (PPC855T) board."
216
 }
217
 
218
+# --------------------------------------------------------------------------
219
+# OpenRISC targets
220
+
221
+package CYGPKG_HAL_OPENRISC {
222
+       alias           { "OpenRISC HAL" hal_openrisc openrisc_hal }
223
+       directory       hal/openrisc/arch
224
+       script          hal_openrisc.cdl
225
+       hardware
226
+       description "
227
+          The OpenRISC architecture HAL package provides generic
228
+           support for this processor architecture. It is also necessary to
229
+           select a specific target platform HAL package."  }
230
+
231
+package CYGPKG_HAL_OPENRISC_ORP {
232
+       alias           { "OpenRISC Reference Platform" hal_orp orp_hal }
233
+       directory       hal/openrisc/orp
234
+       script          hal_openrisc_orp.cdl
235
+       hardware
236
+       description "
237
+           The OpenRISC Reference Platform (ORP) package should be used
238
+           with ORP-compliant simulators or hardware. "
239
+}
240
+
241
+target ORP {
242
+       alias { "OpenRISC Refererence Platform" orp }
243
+       packages { CYGPKG_HAL_OPENRISC
244
+             CYGPKG_HAL_OPENRISC_ORP
245
+                  CYGPKG_DEVS_FLASH_OPENRISC_ORP
246
+                        CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
247
+       }
248
+        description "
249
+        The ORP (OpenRISC Reference Platform) target provides the packages
250
+        needed to run eCos in simulator or HW environments that conform to the
251
+        OpenRISC Reference Platform."
252
+}
253
+
254
+package CYGPKG_HAL_OPENRISC_OR1200_SOC {
255
+       alias           { "OpenRISC or1200_soc Platform" hal_or1200_soc or1200_soc_hal }
256
+       directory       hal/openrisc/or1200_soc
257
+       script          hal_openrisc_or1200_soc.cdl
258
+       hardware
259
+       description "
260
+           The OpenRISC or1200_soc Platform. "
261
+}
262
+
263
+target OR1200_SOC {
264
+       alias { "OpenRISC or1200_soc Platform" or1200_soc }
265
+       packages { CYGPKG_HAL_OPENRISC
266
+             CYGPKG_HAL_OPENRISC_OR1200_SOC
267
+                  CYGPKG_DEVS_FLASH_OPENRISC_ORP
268
+                        CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
269
+       }
270
+        description "
271
+        The or1200_soc target provides the packages
272
+        needed to run eCos."
273
+}
274
+
275
 package CYGPKG_DEVS_FLASH_UE250 {
276
        alias           { "FLASH memory support for uE250" flash_uE250 }
277
        directory       devs/flash/arm/uE250
278
diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/ChangeLog ./ecos-3.0/packages/hal/openrisc/arch/v3_0/ChangeLog
279
--- /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/ChangeLog     1969-12-31 16:00:00.000000000 -0800
280
+++ ./ecos-3.0/packages/hal/openrisc/arch/v3_0/ChangeLog        2009-09-16 14:06:26.000000000 -0700
281
@@ -0,0 +1,45 @@
282
+2003-04-17  Scott Furman 
283
+        + Init tick timer on boot
284
+        + Ensure stack is aligned in HAL_INIT_CONTEXT()
285
+       + Add .text.ram section for time-critical code
286
+
287
+
288
+2003-03-06  Scott Furman 
289
+
290
+        Initial port of eCos to OpenRISC architecture
291
+
292
+//===========================================================================
293
+//####ECOSGPLCOPYRIGHTBEGIN####
294
+// -------------------------------------------
295
+// This file is part of eCos, the Embedded Configurable Operating System.
296
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
297
+// Copyright (C) 2002 Gary Thomas
298
+//
299
+// eCos is free software; you can redistribute it and/or modify it under
300
+// the terms of the GNU General Public License as published by the Free
301
+// Software Foundation; either version 2 or (at your option) any later version.
302
+//
303
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
304
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
305
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
306
+// for more details.
307
+//
308
+// You should have received a copy of the GNU General Public License along
309
+// with eCos; if not, write to the Free Software Foundation, Inc.,
310
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
311
+//
312
+// As a special exception, if other files instantiate templates or use macros
313
+// or inline functions from this file, or you compile this file and link it
314
+// with other works to produce a work based on this file, this file does not
315
+// by itself cause the resulting work to be covered by the GNU General Public
316
+// License. However the source code for this file must still be made available
317
+// in accordance with section (3) of the GNU General Public License.
318
+//
319
+// This exception does not invalidate any other reasons why a work based on
320
+// this file might be covered by the GNU General Public License.
321
+//
322
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
323
+// at http://sources.redhat.com/ecos/ecos-license/
324
+// -------------------------------------------
325
+//####ECOSGPLCOPYRIGHTEND####
326
+//===========================================================================
327
diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/cdl/hal_openrisc.cdl ./ecos-3.0/packages/hal/openrisc/arch/v3_0/cdl/hal_openrisc.cdl
328
--- /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/cdl/hal_openrisc.cdl  1969-12-31 16:00:00.000000000 -0800
329
+++ ./ecos-3.0/packages/hal/openrisc/arch/v3_0/cdl/hal_openrisc.cdl     2010-02-09 09:08:43.561765600 -0800
330
@@ -0,0 +1,111 @@
331
+# ====================================================================
332
+#
333
+#      hal_openrisc.cdl
334
+#
335
+#      OpenRISC architectural HAL package configuration data
336
+#
337
+# ====================================================================
338
+#####ECOSGPLCOPYRIGHTBEGIN####
339
+## -------------------------------------------
340
+## This file is part of eCos, the Embedded Configurable Operating System.
341
+## Copyright (C) 2003 Red Hat, Inc.
342
+##
343
+## eCos is free software; you can redistribute it and/or modify it under
344
+## the terms of the GNU General Public License as published by the Free
345
+## Software Foundation; either version 2 or (at your option) any later version.
346
+##
347
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
348
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
349
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
350
+## for more details.
351
+##
352
+## You should have received a copy of the GNU General Public License along
353
+## with eCos; if not, write to the Free Software Foundation, Inc.,
354
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
355
+##
356
+## As a special exception, if other files instantiate templates or use macros
357
+## or inline functions from this file, or you compile this file and link it
358
+## with other works to produce a work based on this file, this file does not
359
+## by itself cause the resulting work to be covered by the GNU General Public
360
+## License. However the source code for this file must still be made available
361
+## in accordance with section (3) of the GNU General Public License.
362
+##
363
+## This exception does not invalidate any other reasons why a work based on
364
+## this file might be covered by the GNU General Public License.
365
+##
366
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
367
+## at http://sources.redhat.com/ecos/ecos-license/
368
+## -------------------------------------------
369
+#####ECOSGPLCOPYRIGHTEND####
370
+# ====================================================================
371
+######DESCRIPTIONBEGIN####
372
+#
373
+# Author(s):      sfurman
374
+# Original data:  bartv, nickg
375
+# Contributors:   jskov
376
+# Date:           2003-02-28
377
+#
378
+#####DESCRIPTIONEND####
379
+#
380
+# ====================================================================
381
+
382
+cdl_package CYGPKG_HAL_OPENRISC {
383
+    display "OpenRISC architecture"
384
+    parent        CYGPKG_HAL
385
+    hardware
386
+    include_dir   cyg/hal
387
+    define_header hal_openrisc.h
388
+    description   "
389
+        The OpenRISC architecture HAL package provides generic support
390
+        for this processor architecture. It is also necessary to
391
+        select a specific target platform HAL package."
392
+
393
+# For now, there are no defined variants of the OpenRISC
394
+#    cdl_interface CYGINT_HAL_OPENRISC_VARIANT {
395
+#        display  "Number of variant implementations in this configuration"
396
+#        requires 1 == CYGINT_HAL_OPENRISC_VARIANT
397
+#    }
398
+
399
+    compile       context.S vectors.S hal_misc.c openrisc_stub.c
400
+
401
+    make {
402
+        /lib/vectors.o : /src/vectors.S
403
+        $(CC) -Wp,-MD,vectors.tmp $(INCLUDE_PATH) $(CFLAGS) -c -o $@ $<
404
+        @echo $@ ": \\" > $(notdir $@).deps
405
+        @tail vectors.tmp >> $(notdir $@).deps
406
+        @echo >> $(notdir $@).deps
407
+        @rm vectors.tmp
408
+    }
409
+
410
+    define_proc {
411
+        puts $::cdl_header "#define HAL_ARCH_PROGRAM_NEW_STACK hal_arch_program_new_stack"
412
+    }
413
+
414
+    cdl_option CYGBLD_LINKER_SCRIPT {
415
+        display "Linker script"
416
+        flavor data
417
+        no_define
418
+        calculated  { "src/openrisc.ld" }
419
+    }
420
+
421
+    make {
422
+        /lib/target.ld: /src/openrisc.ld
423
+        $(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(CFLAGS) -o $@ $<
424
+        @echo $@ ": \\" > $(notdir $@).deps
425
+        @tail target.tmp >> $(notdir $@).deps
426
+        @echo >> $(notdir $@).deps
427
+        @rm target.tmp
428
+    }
429
+
430
+    cdl_option CYGHWR_HAL_OPENRISC_CPU_FREQ {
431
+        display "CPU frequency"
432
+        flavor  data
433
+        legal_values 0 to 1000000
434
+        default_value 104
435
+        description "
436
+           This option contains the frequency of the CPU in MegaHertz.
437
+           Choose the frequency to match the processor you have. This
438
+           may affect thing like serial device, interval clock and
439
+           memory access speed settings."
440
+    }
441
+}
442
diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/doc/README.html ./ecos-3.0/packages/hal/openrisc/arch/v3_0/doc/README.html
443
--- /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/doc/README.html       1969-12-31 16:00:00.000000000 -0800
444
+++ ./ecos-3.0/packages/hal/openrisc/arch/v3_0/doc/README.html  2009-09-16 14:06:26.000000000 -0700
445
@@ -0,0 +1,39 @@
446
+
447
+
448
+
449
+  README - eCos OpenRISC Port
450
+
451
+
452
+
453
+ For those unfamiliar with OpenRISC, it is an open-source RISC/DSP processor
454
+architecture.  OpenCores.org makes available an 
455
+ href="http://www.opencores.org/projects/or1k">implementation of this
456
+architecture that can be synthesized, for example, as part of an FPGA or ASIC.
457
+ The port of eCos to OpenRISC was sponsored by the 
458
+ href="http://www.rosum.com">Rosum Corporation.
459
+ 
460
+ A few notes and caveats about the eCos OpenRISC port:
461
+
462
+   
  • The only platform supported at this time is ORP (OpenRISC Reference
  • 463
    +Platform).
    464
    +   
  • The only ORP devices supported so far are serial ports used for
  • 465
    +  diagnostic and debugging purposes and AM29LVxxxx Flash ROM.
    466
    +   
  • To build and debug, you must build the GNU development tools from
  • 467
    +    
    468
    + href="#%20http://www.opencores.org/projects/or1k/GNU%20Toolchain%20Port">source
    469
    +available at the OpenCores web site -- not the versions      available
    470
    +from the GNU  web site or elsewhere.  There is a 
    471
    + href="./build_or32_elf_tools.sh">shell script in this directory that
    472
    +will assist in downloading     and building the GNU toolchain.
    473
    +   
  • For debugging, you can use either gdb's JTAG target or the serial
  • 474
    +    target.  The latter has some advantages, e.g. the gdb serial target is
    475
    +thread-aware, but it is much slower, especially while     simulating.
    476
    +  
    477
    +
    478
    +
    479
    + Scott Furman
    480
    + sfurman at rosum dot com
    481
    + 
    482
    +
    483
    +
    484
    +
    485
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/doc/build_or32_elf_tools.sh ./ecos-3.0/packages/hal/openrisc/arch/v3_0/doc/build_or32_elf_tools.sh
    486
    --- /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/doc/build_or32_elf_tools.sh   1969-12-31 16:00:00.000000000 -0800
    487
    +++ ./ecos-3.0/packages/hal/openrisc/arch/v3_0/doc/build_or32_elf_tools.sh      2009-09-16 14:06:26.000000000 -0700
    488
    @@ -0,0 +1,156 @@
    489
    +#!/bin/bash -x
    490
    +
    491
    +# Checkout and build gnu toolchain for OpenRISC (or32 target)
    492
    +
    493
    +# Usage:
    494
    +# build_or32_elf_tools.sh [-c]
    495
    +#   -c  Controls whether CVS checkout is done prior to build
    496
    +#       You probably only want to use this command-line option the first time you build.
    497
    +
    498
    +# Directory in which to checkout sources and build
    499
    +BUILD_DIR=$HOME/or32-elf-src
    500
    +
    501
    +# Target architecture/OS
    502
    +TARGET=or32-elf
    503
    +
    504
    +# Directory in which to put compiled files, exported headers, etc.
    505
    +INSTALL_PREFIX=$HOME/tools/i386-redhat-linux
    506
    +
    507
    +########################################################################
    508
    +
    509
    +if [ $1foo = -cfoo ]; then DO_CVS_CHECKOUT=1; else DO_CVS_CHECKOUT=0; fi
    510
    +
    511
    +#
    512
    +# Some common variables
    513
    +#
    514
    +OK_STR="Build OK"
    515
    +FAIL_STR="Build Failed"
    516
    +
    517
    +mkdir -p $BUILD_DIR
    518
    +cd $BUILD_DIR
    519
    +
    520
    +#
    521
    +# Start with binutils
    522
    +#
    523
    +if [ $DO_CVS_CHECKOUT != 0 ]; then
    524
    +date > checkout_binutils.log 2>&1
    525
    +cvs -d :pserver:cvs@cvs.opencores.org:/home/oc/cvs -z9 co -d binutils or1k/binutils >> \
    526
    + checkout_binutils.log 2>&1
    527
    +fi
    528
    +
    529
    +mkdir -p b-b
    530
    +cd b-b
    531
    +date > ../build_binutils.log 2>&1
    532
    +
    533
    +../binutils/configure --target=$TARGET --prefix=$INSTALL_PREFIX >> ../build_binutils.log 2>&1
    534
    +
    535
    +make all install >> ../build_binutils.log 2>&1
    536
    +BUILD_BINUTILS_STATUS=$?
    537
    +export PATH=$INSTALL_PREFIX/bin:$PATH
    538
    +cd ..
    539
    +
    540
    +#
    541
    +# Check if binutils was built and installed correctly
    542
    +#
    543
    +if [ $BUILD_BINUTILS_STATUS = 0 ]; then
    544
    +        echo "$OK_STR (`date`)" >> build_binutils.log
    545
    +else
    546
    +        echo "$FAIL_STR (`date`)" >>  build_binutils.log
    547
    +fi
    548
    +
    549
    +#
    550
    +# Build gdb
    551
    +#
    552
    +if [ $DO_CVS_CHECKOUT != 0 ]; then
    553
    +date > checkout_gdb.log 2>&1
    554
    +cvs -d :pserver:cvs@cvs.opencores.org:/home/oc/cvs -z9 co -d gdb or1k/gdb-5.0 >> checkout_gdb.log 2>&1
    555
    +fi
    556
    +
    557
    +mkdir -p b-gdb
    558
    +cd b-gdb
    559
    +date > ../build_gdb.log 2>&1
    560
    +# Current version of readline has a configuration bug, so you must not specify
    561
    +# the prefix
    562
    +#../gdb/configure --target=$TARGET --prefix=$INSTALL_PREFIX >> ../build_gdb.log 2>&1
    563
    +../gdb/configure --target=$TARGET >> ../build_gdb.log 2>&1
    564
    +make all >> ../build_gdb.log 2>&1
    565
    +BUILD_GDB_STATUS=$?
    566
    +cp gdb/gdb $INSTALL_PREFIX/bin/$TARGET-gdb
    567
    +cd ..
    568
    +
    569
    +
    570
    +#
    571
    +# Check if gdb was built and installed correctly
    572
    +#
    573
    +if [ $BUILD_GDB_STATUS = 0 ]; then
    574
    +        echo "$OK_STR (`date`)" >> build_gdb.log
    575
    +else
    576
    +        echo "$FAIL_STR (`date`)" >>  build_gdb.log
    577
    +fi
    578
    +
    579
    +#
    580
    +# Build or1k simulator
    581
    +#
    582
    +if [ $DO_CVS_CHECKOUT != 0 ]; then
    583
    +date > checkout_or1ksim.log 2>&1
    584
    +cvs -d :pserver:cvs@cvs.opencores.org:/home/oc/cvs -z9 co -d or1ksim or1k/or1ksim >> checkout_or1ksim.log 2>&1
    585
    +fi
    586
    +
    587
    +cd or1ksim
    588
    +date > ../build_or1ksim.log 2>&1
    589
    +../or1ksim/configure --target=$TARGET --prefix=$INSTALL_PREFIX >> ../build_or1ksim.log 2>&1
    590
    +make all install >> ../build_or1ksim.log 2>&1
    591
    +BUILD_OR1KSIM_STATUS=$?
    592
    +cp sim $INSTALL_PREFIX/bin/or32-elf-sim
    593
    +cd ..
    594
    +
    595
    +#
    596
    +# Check if or1ksim was built and installed correctly
    597
    +#
    598
    +if [ $BUILD_OR1KSIM_STATUS = 0 ]; then
    599
    +        echo "$OK_STR (`date`)" >> build_or1ksim.log
    600
    +else
    601
    +        echo "$FAIL_STR (`date`)" >>  build_or1ksim.log
    602
    +fi
    603
    +
    604
    +# For now, bail here
    605
    +#exit
    606
    +
    607
    +#
    608
    +# Build gcc
    609
    +#
    610
    +if [ $DO_CVS_CHECKOUT != 0 ]; then
    611
    +date > checkout_gcc.log 2>&1
    612
    +cvs -d :pserver:cvs@cvs.opencores.org:/home/oc/cvs -z9 co -d gcc or1k/gcc-3.1 >> checkout_gcc.log 2>&1
    613
    +fi
    614
    +
    615
    +# The config script looks for libraries in a weird place.  Instead of figuring out what's wrong,
    616
    +# I just placate it.
    617
    +
    618
    +pushd $INSTALL_PREFIX
    619
    +cp -pr lib $TARGET
    620
    +popd
    621
    +
    622
    +mkdir -p b-gcc
    623
    +cd b-gcc
    624
    +date > ../build_gcc.log 2>&1
    625
    +../gcc/configure --target=$TARGET \
    626
    +        --with-gnu-as --with-gnu-ld --verbose \
    627
    +        --enable-threads --prefix=$INSTALL_PREFIX \
    628
    +        --enable-languages="c,c++" >> ../build_gcc.log 2>&1
    629
    +make all install >> ../build_gcc.log 2>&1
    630
    +BUILD_GCC_STATUS=$?
    631
    +
    632
    +#
    633
    +# Check if gcc was built and installed correctly
    634
    +#
    635
    +if [ $BUILD_GCC_STATUS = 0 ]; then
    636
    +        echo "$OK_STR (`date`)" >> build_gcc.log
    637
    +else
    638
    +        echo "$FAIL_STR (`date`)" >>  build_gcc.log
    639
    +fi
    640
    +
    641
    +# Install even though g++ build fails due to inability to build libg++ without C library.
    642
    +# (How do we prevent building of libg++ ?)
    643
    +make install
    644
    +
    645
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/include/arch.inc ./ecos-3.0/packages/hal/openrisc/arch/v3_0/include/arch.inc
    646
    --- /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/include/arch.inc      1969-12-31 16:00:00.000000000 -0800
    647
    +++ ./ecos-3.0/packages/hal/openrisc/arch/v3_0/include/arch.inc 2010-02-15 15:18:28.366085800 -0800
    648
    @@ -0,0 +1,107 @@
    649
    +##=============================================================================
    650
    +##
    651
    +##      arch.inc
    652
    +##
    653
    +##      OpenRISC assembler header file
    654
    +##
    655
    +##=============================================================================
    656
    +#####ECOSGPLCOPYRIGHTBEGIN####
    657
    +## -------------------------------------------
    658
    +## This file is part of eCos, the Embedded Configurable Operating System.
    659
    +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
    660
    +##
    661
    +## eCos is free software; you can redistribute it and/or modify it under
    662
    +## the terms of the GNU General Public License as published by the Free
    663
    +## Software Foundation; either version 2 or (at your option) any later version.
    664
    +##
    665
    +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
    666
    +## WARRANTY; without even the implied warranty of MERCHANTABILITY or
    667
    +## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    668
    +## for more details.
    669
    +##
    670
    +## You should have received a copy of the GNU General Public License along
    671
    +## with eCos; if not, write to the Free Software Foundation, Inc.,
    672
    +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
    673
    +##
    674
    +## As a special exception, if other files instantiate templates or use macros
    675
    +## or inline functions from this file, or you compile this file and link it
    676
    +## with other works to produce a work based on this file, this file does not
    677
    +## by itself cause the resulting work to be covered by the GNU General Public
    678
    +## License. However the source code for this file must still be made available
    679
    +## in accordance with section (3) of the GNU General Public License.
    680
    +##
    681
    +## This exception does not invalidate any other reasons why a work based on
    682
    +## this file might be covered by the GNU General Public License.
    683
    +##
    684
    +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
    685
    +## at http://sources.redhat.com/ecos/ecos-license/
    686
    +## -------------------------------------------
    687
    +#####ECOSGPLCOPYRIGHTEND####
    688
    +##=============================================================================
    689
    +#######DESCRIPTIONBEGIN####
    690
    +##
    691
    +## Author(s):   sfurman
    692
    +## Contributors:
    693
    +## Date:        2003-01-15
    694
    +## Purpose:     Architecture definitions.
    695
    +## Description: This file contains various definitions and macros that are
    696
    +##              useful for writing assembly code for the OpenRISC CPU family.
    697
    +## Usage:
    698
    +##              #include 
    699
    +##              ...
    700
    +##
    701
    +##
    702
    +######DESCRIPTIONEND####
    703
    +##
    704
    +##=============================================================================
    705
    +
    706
    +#ifndef CYGONCE_HAL_ARCH_INC
    707
    +#define CYGONCE_HAL_ARCH_INC
    708
    +
    709
    +# Declare given label name as the start of a function accessible from C code
    710
    +#define FUNC_START(name)        \
    711
    +        .type _##name,@function;   \
    712
    +        .globl _##name;            \
    713
    +_##name:
    714
    +
    715
    +#define FUNC_END(name)
    716
    +
    717
    +# Make aliases for ABI distinguished registers
    718
    +#define sp r1
    719
    +#define fp r2
    720
    +#define lr r9
    721
    +#define rv r11
    722
    +
    723
    +# Size of GPR regs - 4 bytes for or32
    724
    +#define OR1K_GPRSIZE    4
    725
    +
    726
    +# Size of all other registers
    727
    +#define OR1K_REGSIZE    4
    728
    +
    729
    +# Utility macro: Load a 32-bit constant into a register
    730
    +        .macro  load32i reg const
    731
    +        l.movhi \reg,hi(\const)
    732
    +        l.ori   \reg,\reg,lo(\const)
    733
    +        .endm
    734
    +
    735
    +##-----------------------------------------------------------------------------
    736
    +
    737
    +## OpenRISC thread and interrupt saved state structure. These offsets
    738
    +## must match the layout of the HAL_SavedRegisters struct in
    739
    +## hal_arch.h. Do not change this without changing the layout there,
    740
    +## or viceversa.
    741
    +
    742
    +#define OR1KREGS_GPRS   0
    743
    +#define OR1KREG_MACHI   (OR1KREGS_GPRS + OR1K_GPRSIZE * 32)
    744
    +#define OR1KREG_MACLO   (OR1KREG_MACHI + OR1K_REGSIZE)
    745
    +#define OR1KREG_VECTOR  (OR1KREG_MACLO + OR1K_REGSIZE)
    746
    +#define OR1KREG_SR      (OR1KREG_VECTOR+ OR1K_REGSIZE)
    747
    +#define OR1KREG_PC      (OR1KREG_SR    + OR1K_REGSIZE)
    748
    +#define OR1KREG_EEAR    (OR1KREG_PC    + OR1K_REGSIZE)
    749
    +
    750
    +#define SIZEOF_OR1KREGS (OR1KREG_EEAR  + OR1K_REGSIZE)
    751
    +
    752
    +#include 
    753
    +#include 
    754
    +
    755
    +#endif // #ifndef CYGONCE_HAL_ARCH_INC
    756
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/include/basetype.h ./ecos-3.0/packages/hal/openrisc/arch/v3_0/include/basetype.h
    757
    --- /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/include/basetype.h    1969-12-31 16:00:00.000000000 -0800
    758
    +++ ./ecos-3.0/packages/hal/openrisc/arch/v3_0/include/basetype.h       2009-09-16 14:06:24.000000000 -0700
    759
    @@ -0,0 +1,76 @@
    760
    +#ifndef CYGONCE_HAL_BASETYPE_H
    761
    +#define CYGONCE_HAL_BASETYPE_H
    762
    +
    763
    +//=============================================================================
    764
    +//
    765
    +//      basetype.h
    766
    +//
    767
    +//      Standard types for this architecture.
    768
    +//
    769
    +//=============================================================================
    770
    +//####ECOSGPLCOPYRIGHTBEGIN####
    771
    +// -------------------------------------------
    772
    +// This file is part of eCos, the Embedded Configurable Operating System.
    773
    +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
    774
    +//
    775
    +// eCos is free software; you can redistribute it and/or modify it under
    776
    +// the terms of the GNU General Public License as published by the Free
    777
    +// Software Foundation; either version 2 or (at your option) any later version.
    778
    +//
    779
    +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
    780
    +// WARRANTY; without even the implied warranty of MERCHANTABILITY or
    781
    +// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    782
    +// for more details.
    783
    +//
    784
    +// You should have received a copy of the GNU General Public License along
    785
    +// with eCos; if not, write to the Free Software Foundation, Inc.,
    786
    +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
    787
    +//
    788
    +// As a special exception, if other files instantiate templates or use macros
    789
    +// or inline functions from this file, or you compile this file and link it
    790
    +// with other works to produce a work based on this file, this file does not
    791
    +// by itself cause the resulting work to be covered by the GNU General Public
    792
    +// License. However the source code for this file must still be made available
    793
    +// in accordance with section (3) of the GNU General Public License.
    794
    +//
    795
    +// This exception does not invalidate any other reasons why a work based on
    796
    +// this file might be covered by the GNU General Public License.
    797
    +//
    798
    +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
    799
    +// at http://sources.redhat.com/ecos/ecos-license/
    800
    +// -------------------------------------------
    801
    +//####ECOSGPLCOPYRIGHTEND####
    802
    +//=============================================================================
    803
    +//#####DESCRIPTIONBEGIN####
    804
    +//
    805
    +// Author(s):    sfurman
    806
    +// Contributors: nickg
    807
    +// Date:         2003-02-28
    808
    +// Purpose:      Define architecture base types.
    809
    +// Usage:        Included by , do not use directly
    810
    +//
    811
    +//####DESCRIPTIONEND####
    812
    +//
    813
    +
    814
    +#include 
    815
    +
    816
    +//-----------------------------------------------------------------------------
    817
    +// Characterize the architecture
    818
    +
    819
    +# define CYG_BYTEORDER           CYG_MSBFIRST    // Big endian
    820
    +# define CYG_DOUBLE_BYTEORDER    CYG_MSBFIRST    // Big endian
    821
    +
    822
    +//-----------------------------------------------------------------------------
    823
    +// Prepend underscore to symbol name for it to be visible from C
    824
    +#define CYG_LABEL_DEFN(_name_) _##_name_
    825
    +
    826
    +//-----------------------------------------------------------------------------
    827
    +// Define the standard variable sizes
    828
    +
    829
    +// (The OpenRISC architecture uses the default definitions of the base types,
    830
    +// so we do not need to define any here.)
    831
    +
    832
    +//-----------------------------------------------------------------------------
    833
    +#endif // CYGONCE_HAL_BASETYPE_H
    834
    +
    835
    +// End of basetype.h
    836
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/include/hal_arch.h ./ecos-3.0/packages/hal/openrisc/arch/v3_0/include/hal_arch.h
    837
    --- /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/include/hal_arch.h    1969-12-31 16:00:00.000000000 -0800
    838
    +++ ./ecos-3.0/packages/hal/openrisc/arch/v3_0/include/hal_arch.h       2009-09-16 14:06:26.000000000 -0700
    839
    @@ -0,0 +1,369 @@
    840
    +//==========================================================================
    841
    +//
    842
    +//      hal_arch.h
    843
    +//
    844
    +//      Architecture specific abstractions
    845
    +//
    846
    +//==========================================================================
    847
    +//####ECOSGPLCOPYRIGHTBEGIN####
    848
    +// -------------------------------------------
    849
    +// This file is part of eCos, the Embedded Configurable Operating System.
    850
    +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
    851
    +//
    852
    +// eCos is free software; you can redistribute it and/or modify it under
    853
    +// the terms of the GNU General Public License as published by the Free
    854
    +// Software Foundation; either version 2 or (at your option) any later version.
    855
    +//
    856
    +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
    857
    +// WARRANTY; without even the implied warranty of MERCHANTABILITY or
    858
    +// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    859
    +// for more details.
    860
    +//
    861
    +// You should have received a copy of the GNU General Public License along
    862
    +// with eCos; if not, write to the Free Software Foundation, Inc.,
    863
    +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
    864
    +//
    865
    +// As a special exception, if other files instantiate templates or use macros
    866
    +// or inline functions from this file, or you compile this file and link it
    867
    +// with other works to produce a work based on this file, this file does not
    868
    +// by itself cause the resulting work to be covered by the GNU General Public
    869
    +// License. However the source code for this file must still be made available
    870
    +// in accordance with section (3) of the GNU General Public License.
    871
    +//
    872
    +// This exception does not invalidate any other reasons why a work based on
    873
    +// this file might be covered by the GNU General Public License.
    874
    +//
    875
    +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
    876
    +// at http://sources.redhat.com/ecos/ecos-license/
    877
    +// -------------------------------------------
    878
    +//####ECOSGPLCOPYRIGHTEND####
    879
    +//==========================================================================
    880
    +//#####DESCRIPTIONBEGIN####
    881
    +//
    882
    +// Author(s):    sfurman
    883
    +// Contributors:
    884
    +// Date:         2003-01-17
    885
    +// Purpose:      Define architecture abstractions
    886
    +// Usage:        #include 
    887
    +//
    888
    +//####DESCRIPTIONEND####
    889
    +//
    890
    +//==========================================================================
    891
    +
    892
    +#ifndef CYGONCE_HAL_HAL_ARCH_H
    893
    +#define CYGONCE_HAL_HAL_ARCH_H
    894
    +
    895
    +// Include macros to access special-purpose registers (SPRs)
    896
    +#include 
    897
    +
    898
    +#define CYG_HAL_OPENRISC_REG_SIZE 4
    899
    +
    900
    +#ifndef __ASSEMBLER__
    901
    +#include 
    902
    +#include 
    903
    +
    904
    +//--------------------------------------------------------------------------
    905
    +// Processor saved states:
    906
    +// The layout of this structure is also defined in "arch.inc", for assembly
    907
    +// code. Do not change this without changing that (or vice versa).
    908
    +
    909
    +#define CYG_HAL_OPENRISC_REG CYG_WORD32
    910
    +
    911
    +typedef struct
    912
    +{
    913
    +    // These are common to all saved states
    914
    +    CYG_HAL_OPENRISC_REG    r[32];          // GPR regs
    915
    +    CYG_HAL_OPENRISC_REG    machi;          // High and low words of
    916
    +    CYG_HAL_OPENRISC_REG    maclo;          //   multiply/accumulate reg
    917
    +
    918
    +    // These are only saved for exceptions and interrupts
    919
    +    CYG_WORD32              vector;         /* Vector number            */
    920
    +    CYG_WORD32              sr;             /* Status Reg               */
    921
    +    CYG_HAL_OPENRISC_REG    pc;             /* Program Counter          */
    922
    +
    923
    +    // Saved only for exceptions, and not restored when continued:
    924
    +    // Effective address of instruction/data access that caused exception
    925
    +    CYG_HAL_OPENRISC_REG    eear;           /* Exception effective address reg */
    926
    +} HAL_SavedRegisters;
    927
    +
    928
    +//--------------------------------------------------------------------------
    929
    +//  Utilities
    930
    +
    931
    +// Move from architecture special register (SPR)
    932
    +#define MFSPR(_spr_)                                      \
    933
    +({  CYG_HAL_OPENRISC_REG _result_;                        \
    934
    +    asm volatile ("l.mfspr %0, r0, %1;"                   \
    935
    +        : "=r"(_result_)                                  \
    936
    +        : "K"(_spr_)                                      \
    937
    +    );                                                    \
    938
    +    _result_;})
    939
    +
    940
    +// Move data to architecture special registers (SPR)
    941
    +#define MTSPR(_spr_, _val_)                               \
    942
    +CYG_MACRO_START                                           \
    943
    +    CYG_HAL_OPENRISC_REG val = _val_;                     \
    944
    +    asm volatile ("l.mtspr r0, %0, %1;"                   \
    945
    +        :                                                 \
    946
    +        : "r"(val), "K"(_spr_)                            \
    947
    +    );                                                    \
    948
    +CYG_MACRO_END
    949
    +
    950
    +//--------------------------------------------------------------------------
    951
    +// Exception handling function.
    952
    +// This function is defined by the kernel according to this prototype. It is
    953
    +// invoked from the HAL to deal with any CPU exceptions that the HAL does
    954
    +// not want to deal with itself. It usually invokes the kernel's exception
    955
    +// delivery mechanism.
    956
    +
    957
    +externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data );
    958
    +
    959
    +//--------------------------------------------------------------------------
    960
    +// Bit manipulation macros
    961
    +
    962
    +externC cyg_uint32 hal_lsbit_index(cyg_uint32 mask);
    963
    +externC cyg_uint32 hal_msbit_index(cyg_uint32 mask);
    964
    +
    965
    +#define HAL_LSBIT_INDEX(index, mask) index = hal_lsbit_index(mask);
    966
    +
    967
    +// NOTE - Below can be optimized with l.ff1 instruction if that optional
    968
    +//        instruction is implemented in HW.  OR12k does not implement
    969
    +//        it at this time, however.
    970
    +#define HAL_MSBIT_INDEX(index, mask) index = hal_msbit_index(mask);
    971
    +
    972
    +//--------------------------------------------------------------------------
    973
    +// Context Initialization
    974
    +
    975
    +
    976
    +// Initialize the context of a thread.
    977
    +// Arguments:
    978
    +// _sparg_ name of variable containing current sp, will be written with new sp
    979
    +// _thread_ thread object address, passed as argument to entry point
    980
    +// _entry_ entry point address.
    981
    +// _id_ bit pattern used in initializing registers, for debugging.
    982
    +#define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ )                     \
    983
    +{                                                                                       \
    984
    +    int _i_;                                                                            \
    985
    +    register CYG_WORD _sp_ = ((CYG_WORD)_sparg_);                                       \
    986
    +    register HAL_SavedRegisters *_regs_;                                                \
    987
    +    _regs_ = (HAL_SavedRegisters *)(((_sp_) - sizeof(HAL_SavedRegisters)) & ~(CYGARC_ALIGNMENT));\
    988
    +    _sp_ &= ~(CYGARC_ALIGNMENT);                                                        \
    989
    +    for( _i_ = 1; _i_ < 32; _i_++ ) (_regs_)->r[_i_] = (_id_)|_i_;                      \
    990
    +    (_regs_)->r[1] = (CYG_HAL_OPENRISC_REG)(_sp_);       /* SP = top of stack      */   \
    991
    +    (_regs_)->r[2] = (CYG_HAL_OPENRISC_REG)(_sp_);       /* FP = top of stack      */   \
    992
    +    (_regs_)->r[3] = (CYG_HAL_OPENRISC_REG)(_thread_);   /* R3 = arg1 = thread ptr */   \
    993
    +    (_regs_)->maclo = 0;                                 /* MACLO = 0              */   \
    994
    +    (_regs_)->machi = 0;                                 /* MACHI = 0              */   \
    995
    +    (_regs_)->sr = (SPR_SR_TEE|SPR_SR_IEE);              /* Interrupts enabled     */   \
    996
    +    (_regs_)->pc = (CYG_HAL_OPENRISC_REG)(_entry_);      /* PC = entry point       */   \
    997
    +    (_regs_)->r[9] = (CYG_HAL_OPENRISC_REG)(_entry_);    /* PC = entry point       */   \
    998
    +    _sparg_ = (CYG_ADDRESS)_regs_;                                                      \
    999
    +}
    1000
    +
    1001
    +//--------------------------------------------------------------------------
    1002
    +// Context switch macros.
    1003
    +
    1004
    +// The arguments to these macros are *pointers* to locations where the
    1005
    +// stack pointer of the thread is to be stored/retrieved, i.e. *not*
    1006
    +// the value of the stack pointer itself.
    1007
    +
    1008
    +externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from );
    1009
    +externC void hal_thread_load_context( CYG_ADDRESS to )
    1010
    +    __attribute__ ((noreturn));
    1011
    +
    1012
    +#define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_)                    \
    1013
    +        hal_thread_switch_context( (CYG_ADDRESS)_tspptr_,               \
    1014
    +                                   (CYG_ADDRESS)_fspptr_);
    1015
    +
    1016
    +#define HAL_THREAD_LOAD_CONTEXT(_tspptr_)                               \
    1017
    +        hal_thread_load_context( (CYG_ADDRESS)_tspptr_ );
    1018
    +
    1019
    +// Translate a stack pointer as saved by the thread context macros above into
    1020
    +// a pointer to a HAL_SavedRegisters structure.
    1021
    +#define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ )  \
    1022
    +        (_regs_) = (HAL_SavedRegisters *)(_sp_)
    1023
    +
    1024
    +//--------------------------------------------------------------------------
    1025
    +// Execution reorder barrier.
    1026
    +// When optimizing the compiler can reorder code. In multithreaded systems
    1027
    +// where the order of actions is vital, this can sometimes cause problems.
    1028
    +// This macro may be inserted into places where reordering should not happen.
    1029
    +// The "memory" keyword is potentially unnecessary, but it is harmless to
    1030
    +// keep it.
    1031
    +
    1032
    +#define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" )
    1033
    +
    1034
    +//--------------------------------------------------------------------------
    1035
    +// Breakpoint support
    1036
    +// HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to
    1037
    +//    occur if executed.
    1038
    +// HAL_BREAKINST is the value of the breakpoint instruction and...
    1039
    +// HAL_BREAKINST_SIZE is its size in bytes and...
    1040
    +// HAL_BREAKINST_TYPE is its type.
    1041
    +
    1042
    +#define HAL_BREAKPOINT(_label_)                 \
    1043
    +asm volatile (" .globl  _" #_label_ ";"         \
    1044
    +              "_" #_label_ ":"                  \
    1045
    +              " l.trap 1;"                      \
    1046
    +    );
    1047
    +
    1048
    +#define HAL_BREAKINST           (0x21000001)    // l.trap 1 instruction
    1049
    +
    1050
    +#define HAL_BREAKINST_SIZE      4
    1051
    +
    1052
    +#define HAL_BREAKINST_TYPE      cyg_uint32
    1053
    +
    1054
    +//--------------------------------------------------------------------------
    1055
    +// Thread register state manipulation for GDB support.
    1056
    +
    1057
    +// Default to a 32 bit register size for GDB register dumps.
    1058
    +#ifndef CYG_HAL_GDB_REG
    1059
    +#define CYG_HAL_GDB_REG CYG_WORD32
    1060
    +#endif
    1061
    +
    1062
    +// Register layout expected by GDB
    1063
    +typedef struct
    1064
    +{
    1065
    +    CYG_HAL_OPENRISC_REG    r[32];          // GPR regs
    1066
    +    CYG_HAL_OPENRISC_REG    pc;             // Program Counter
    1067
    +    CYG_HAL_OPENRISC_REG    sr;             // Supervisor/Status Reg
    1068
    +} GDB_Registers;
    1069
    +
    1070
    +// Copy a set of registers from a HAL_SavedRegisters structure into a
    1071
    +// GDB_Registers structure.
    1072
    +#define HAL_GET_GDB_REGISTERS( _aregval_, _regs_ )              \
    1073
    +    CYG_MACRO_START                                             \
    1074
    +    GDB_Registers *_gdb_ = (GDB_Registers *)(_aregval_);        \
    1075
    +    int _i_;                                                    \
    1076
    +                                                                \
    1077
    +    for( _i_ = 0; _i_ <  32; _i_++ ) {                          \
    1078
    +        _gdb_->r[_i_] = (_regs_)->r[_i_];                       \
    1079
    +    }                                                           \
    1080
    +                                                                \
    1081
    +    _gdb_->pc = (_regs_)->pc;                                   \
    1082
    +    _gdb_->sr = (_regs_)->sr;                                   \
    1083
    +    CYG_MACRO_END
    1084
    +
    1085
    +// Copy a set of registers from a GDB_Registers structure into a
    1086
    +// HAL_SavedRegisters structure.
    1087
    +#define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ )             \
    1088
    +    CYG_MACRO_START                                             \
    1089
    +    GDB_Registers *_gdb_ = (GDB_Registers *)(_aregval_);        \
    1090
    +    int _i_;                                                    \
    1091
    +                                                                \
    1092
    +    for( _i_ = 0; _i_ <  32; _i_++ )                            \
    1093
    +        (_regs_)->r[_i_] = _gdb_->r[_i_];                       \
    1094
    +                                                                \
    1095
    +    (_regs_)->pc = _gdb_->pc;                                   \
    1096
    +    (_regs_)->sr = _gdb_->sr;                                   \
    1097
    +    CYG_MACRO_END
    1098
    +
    1099
    +//--------------------------------------------------------------------------
    1100
    +// HAL setjmp
    1101
    +// Note: These definitions are repeated in context.S. If changes are
    1102
    +// required remember to update both sets.
    1103
    +
    1104
    +#define CYGARC_JMP_BUF_R1        0
    1105
    +#define CYGARC_JMP_BUF_R2        1
    1106
    +#define CYGARC_JMP_BUF_R9        2
    1107
    +#define CYGARC_JMP_BUF_R10       3
    1108
    +#define CYGARC_JMP_BUF_R12       4
    1109
    +#define CYGARC_JMP_BUF_R14       5
    1110
    +#define CYGARC_JMP_BUF_R16       6
    1111
    +#define CYGARC_JMP_BUF_R18       7
    1112
    +#define CYGARC_JMP_BUF_R20       8
    1113
    +#define CYGARC_JMP_BUF_R22       9
    1114
    +#define CYGARC_JMP_BUF_R24      10
    1115
    +#define CYGARC_JMP_BUF_R26      11
    1116
    +#define CYGARC_JMP_BUF_R28      12
    1117
    +#define CYGARC_JMP_BUF_R30      13
    1118
    +
    1119
    +#define CYGARC_JMP_BUF_SIZE     14
    1120
    +
    1121
    +typedef CYG_HAL_OPENRISC_REG hal_jmp_buf[CYGARC_JMP_BUF_SIZE];
    1122
    +
    1123
    +externC int hal_setjmp(hal_jmp_buf env);
    1124
    +externC void hal_longjmp(hal_jmp_buf env, int val);
    1125
    +
    1126
    +//-------------------------------------------------------------------------
    1127
    +// Idle thread code.
    1128
    +// This macro is called in the idle thread loop, and gives the HAL the
    1129
    +// chance to run code when no threads are runnable. Typical idle
    1130
    +// thread behaviour might be to halt the processor.
    1131
    +
    1132
    +externC void hal_idle_thread_action(cyg_uint32 loop_count);
    1133
    +
    1134
    +#define HAL_IDLE_THREAD_ACTION(_count_) hal_idle_thread_action(_count_)
    1135
    +
    1136
    +//--------------------------------------------------------------------------
    1137
    +// Minimal and sensible stack sizes: the intention is that applications
    1138
    +// will use these to provide a stack size in the first instance prior to
    1139
    +// proper analysis.  Idle thread stack should be this big.
    1140
    +
    1141
    +// *** THESE ARE NOT INTENDED TO BE GUARANTEED SUFFICIENT STACK SIZES ***
    1142
    +// They are, however, enough to start programming.
    1143
    +// You might, for example, need to make your stacks larger if you have
    1144
    +// large "auto" variables.
    1145
    +
    1146
    +// This is not a config option because it should not be adjusted except
    1147
    +// under "enough rope to hang yourself" sort of disclaimers.
    1148
    +
    1149
    +// Typical case stack frame size: return link + 10 caller-saved temporaries + 4 locals.
    1150
    +#define CYGNUM_HAL_STACK_FRAME_SIZE (15 * CYG_HAL_OPENRISC_REG_SIZE)
    1151
    +
    1152
    +// Stack needed for a context switch:
    1153
    +#define CYGNUM_HAL_STACK_CONTEXT_SIZE (38 * 4)  // sizeof(HAL_SavedRegisters)
    1154
    +
    1155
    +// Interrupt + call to ISR, interrupt_end() and the DSR
    1156
    +#define CYGNUM_HAL_STACK_INTERRUPT_SIZE (CYGNUM_HAL_STACK_CONTEXT_SIZE + 2*CYGNUM_HAL_STACK_FRAME_SIZE)
    1157
    +
    1158
    +// We define a minimum stack size as the minimum any thread could ever
    1159
    +// legitimately get away with. We can throw asserts if users ask for less
    1160
    +// than this. Allow enough for three interrupt sources - clock, serial and
    1161
    +// one other
    1162
    +
    1163
    +// If interrupts are segregated onto their own stack...
    1164
    +#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
    1165
    +
    1166
    +// An interrupt stack which is large enough for all possible interrupt
    1167
    +// conditions (and only used for that purpose) exists.  "User" stacks
    1168
    +// can therefore be much smaller
    1169
    +// NOTE - interrupt stack sizes can be smaller if we don't allow interrupts
    1170
    +//         to nest.
    1171
    +
    1172
    +# define CYGNUM_HAL_STACK_SIZE_MINIMUM \
    1173
    +         ((3 * 5)*CYGNUM_HAL_STACK_FRAME_SIZE + 2*CYGNUM_HAL_STACK_INTERRUPT_SIZE)
    1174
    +
    1175
    +#else
    1176
    +
    1177
    +// No separate interrupt stack exists.  Make sure all threads contain
    1178
    +// a stack sufficiently large
    1179
    +# define CYGNUM_HAL_STACK_SIZE_MINIMUM                  \
    1180
    +        (( 3*CYGNUM_HAL_STACK_INTERRUPT_SIZE) +         \
    1181
    +         (25*CYGNUM_HAL_STACK_FRAME_SIZE))
    1182
    +#endif
    1183
    +
    1184
    +// Now make a reasonable choice for a typical thread size. Pluck figures
    1185
    +// from thin air and say 40 call frames
    1186
    +#define CYGNUM_HAL_STACK_SIZE_TYPICAL                \
    1187
    +        (CYGNUM_HAL_STACK_SIZE_MINIMUM +             \
    1188
    +         40 * (CYGNUM_HAL_STACK_FRAME_SIZE))
    1189
    +
    1190
    +#endif /* __ASSEMBLER__ */
    1191
    +
    1192
    +//--------------------------------------------------------------------------
    1193
    +// Macros for switching context between two eCos instances (jump from
    1194
    +// code in ROM to code in RAM or vice versa).
    1195
    +// These are NOP's in the case of OpenRISC.
    1196
    +#define CYGARC_HAL_SAVE_GP()
    1197
    +#define CYGARC_HAL_RESTORE_GP()
    1198
    +
    1199
    +//--------------------------------------------------------------------------
    1200
    +// Macro for finding return address of current function
    1201
    +#define CYGARC_HAL_GET_RETURN_ADDRESS(_x_, _dummy_) \
    1202
    +  asm volatile ( "l.ori %0,r9,0;" : "=r" (_x_) )
    1203
    +
    1204
    +#define CYGARC_HAL_GET_RETURN_ADDRESS_BACKUP(_dummy_)
    1205
    +
    1206
    +//--------------------------------------------------------------------------
    1207
    +#endif // CYGONCE_HAL_HAL_ARCH_H
    1208
    +// End of hal_arch.h
    1209
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/include/hal_cache.h ./ecos-3.0/packages/hal/openrisc/arch/v3_0/include/hal_cache.h
    1210
    --- /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/include/hal_cache.h   1969-12-31 16:00:00.000000000 -0800
    1211
    +++ ./ecos-3.0/packages/hal/openrisc/arch/v3_0/include/hal_cache.h      2009-09-16 14:06:26.000000000 -0700
    1212
    @@ -0,0 +1,242 @@
    1213
    +#ifndef CYGONCE_HAL_CACHE_H
    1214
    +#define CYGONCE_HAL_CACHE_H
    1215
    +
    1216
    +//=============================================================================
    1217
    +//
    1218
    +//      hal_cache.h
    1219
    +//
    1220
    +//      HAL cache control API
    1221
    +//
    1222
    +//=============================================================================
    1223
    +//####ECOSGPLCOPYRIGHTBEGIN####
    1224
    +// -------------------------------------------
    1225
    +// This file is part of eCos, the Embedded Configurable Operating System.
    1226
    +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
    1227
    +//
    1228
    +// eCos is free software; you can redistribute it and/or modify it under
    1229
    +// the terms of the GNU General Public License as published by the Free
    1230
    +// Software Foundation; either version 2 or (at your option) any later version.
    1231
    +//
    1232
    +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
    1233
    +// WARRANTY; without even the implied warranty of MERCHANTABILITY or
    1234
    +// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    1235
    +// for more details.
    1236
    +//
    1237
    +// You should have received a copy of the GNU General Public License along
    1238
    +// with eCos; if not, write to the Free Software Foundation, Inc.,
    1239
    +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
    1240
    +//
    1241
    +// As a special exception, if other files instantiate templates or use macros
    1242
    +// or inline functions from this file, or you compile this file and link it
    1243
    +// with other works to produce a work based on this file, this file does not
    1244
    +// by itself cause the resulting work to be covered by the GNU General Public
    1245
    +// License. However the source code for this file must still be made available
    1246
    +// in accordance with section (3) of the GNU General Public License.
    1247
    +//
    1248
    +// This exception does not invalidate any other reasons why a work based on
    1249
    +// this file might be covered by the GNU General Public License.
    1250
    +//
    1251
    +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
    1252
    +// at http://sources.redhat.com/ecos/ecos-license/
    1253
    +// -------------------------------------------
    1254
    +//####ECOSGPLCOPYRIGHTEND####
    1255
    +//=============================================================================
    1256
    +//#####DESCRIPTIONBEGIN####
    1257
    +//
    1258
    +// Author(s):   Scott Furman
    1259
    +// Contributors:
    1260
    +// Date:        2003-02-08
    1261
    +// Purpose:     Cache control API
    1262
    +// Description: The macros defined here provide the HAL APIs for handling
    1263
    +//              cache control operations.
    1264
    +// Usage:
    1265
    +//              #include 
    1266
    +//              ...
    1267
    +//
    1268
    +//
    1269
    +//####DESCRIPTIONEND####
    1270
    +//
    1271
    +//=============================================================================
    1272
    +
    1273
    +//-----------------------------------------------------------------------------
    1274
    +// Cache dimensions.
    1275
    +// These really should be defined in var_cache.h. If they are not, then provide
    1276
    +// a set of numbers that are typical of many variants.
    1277
    +
    1278
    +#ifndef HAL_DCACHE_SIZE
    1279
    +
    1280
    +// Data cache
    1281
    +#define HAL_DCACHE_SIZE                 4096    // Size of data cache in bytes
    1282
    +#define HAL_DCACHE_LINE_SIZE            16      // Bytes in a data cache line
    1283
    +#define HAL_DCACHE_WAYS                 1       // Associativity of the cache
    1284
    +
    1285
    +// Instruction cache
    1286
    +#define HAL_ICACHE_SIZE                 4096    // Size of cache in bytes
    1287
    +#define HAL_ICACHE_LINE_SIZE            16      // Bytes in a cache line
    1288
    +#define HAL_ICACHE_WAYS                 1       // Associativity of the cache
    1289
    +
    1290
    +#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
    1291
    +#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
    1292
    +
    1293
    +#endif
    1294
    +
    1295
    +#ifndef __ASSEMBLER__
    1296
    +
    1297
    +//-----------------------------------------------------------------------------
    1298
    +// Global control of data cache
    1299
    +
    1300
    +// Enable the data cache
    1301
    +#define HAL_DCACHE_ENABLE() MTSPR(SPR_SR, MFSPR(SPR_SR) | SPR_SR_DCE)
    1302
    +
    1303
    +// Disable the data cache
    1304
    +#define HAL_DCACHE_DISABLE() MTSPR(SPR_SR, MFSPR(SPR_SR) & ~SPR_SR_DCE)
    1305
    +
    1306
    +// Enable or disable the data cache, depending on argument, which is required
    1307
    +// to be 0 or 1.
    1308
    +#define HAL_SET_DCACHE_ENABLED(enable)                          \
    1309
    +    MTSPR(SPR_SR, MFSPR(SPR_SR) | (SPR_SR_DCE & -(enable)))
    1310
    +
    1311
    +// Invalidate the entire data cache
    1312
    +#define HAL_DCACHE_INVALIDATE_ALL()                             \
    1313
    +    CYG_MACRO_START                                             \
    1314
    +    int cache_enabled, addr;                                    \
    1315
    +                                                                \
    1316
    +    /* Save current cache mode (disabled/enabled) */            \
    1317
    +    HAL_DCACHE_IS_ENABLED(cache_enabled);                       \
    1318
    +                                                                \
    1319
    +    /* Disable cache, so that invalidation ignores cache tags */\
    1320
    +    HAL_DCACHE_DISABLE();                                       \
    1321
    +    addr = HAL_DCACHE_SIZE;                                     \
    1322
    +    do {                                                        \
    1323
    +        MTSPR(SPR_DCBIR, addr);                                 \
    1324
    +        addr -= HAL_DCACHE_LINE_SIZE;                           \
    1325
    +    } while (addr > 0);                                         \
    1326
    +                                                                \
    1327
    +    /* Re-enable cache if it was enabled on entry */            \
    1328
    +    HAL_SET_DCACHE_ENABLED(cache_enabled);                      \
    1329
    +    CYG_MACRO_END
    1330
    +
    1331
    +// Synchronize the contents of the cache with memory.
    1332
    +// (Unnecessary on OR12K, since cache is write-through.)
    1333
    +#define HAL_DCACHE_SYNC()                       \
    1334
    +    CYG_MACRO_START                             \
    1335
    +    CYG_MACRO_END
    1336
    +
    1337
    +// Query the state (enabled/disabled) of the data cache
    1338
    +#define HAL_DCACHE_IS_ENABLED(_state_)                          \
    1339
    +    CYG_MACRO_START                                             \
    1340
    +    (_state_) = (1 - !(MFSPR(SPR_SR) & SPR_SR_DCE));            \
    1341
    +    CYG_MACRO_END
    1342
    +
    1343
    +// Load the contents of the given address range into the data cache
    1344
    +// and then lock the cache so that it stays there.
    1345
    +
    1346
    +// The OpenRISC architecture defines these operations, but no
    1347
    +// implementation supports them yet.
    1348
    +
    1349
    +//#define HAL_DCACHE_LOCK(_base_, _size_)
    1350
    +
    1351
    +// Undo a previous lock operation
    1352
    +//#define HAL_DCACHE_UNLOCK(_base_, _size_)
    1353
    +
    1354
    +// Unlock entire cache
    1355
    +//#define HAL_DCACHE_UNLOCK_ALL()
    1356
    +
    1357
    +
    1358
    +//-----------------------------------------------------------------------------
    1359
    +// Data cache line control
    1360
    +
    1361
    +// Write dirty cache lines to memory and invalidate the cache entries
    1362
    +// for the given address range.
    1363
    +// OR12k has write-through cache, so no flushing of writes to memory
    1364
    +// are necessary.
    1365
    +#define HAL_DCACHE_FLUSH( _base_ , _size_ )                          \
    1366
    +    HAL_DCACHE_INVALIDATE(_base_, _size_)
    1367
    +
    1368
    +// Invalidate cache lines in the given range without writing to memory.
    1369
    +#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )                     \
    1370
    +    CYG_MACRO_START                                                  \
    1371
    +    int addr;                                                        \
    1372
    +    int end = _base_ + _size_;                                       \
    1373
    +    for (addr = end; addr >= _base_; addr -= HAL_DCACHE_LINE_SIZE) { \
    1374
    +        MTSPR(SPR_DCBIR, addr);                                      \
    1375
    +    }                                                                \
    1376
    +    CYG_MACRO_END
    1377
    +
    1378
    +// Write dirty cache lines to memory for the given address range.
    1379
    +// OR12k has write-through cache, so this is a NOP
    1380
    +#define HAL_DCACHE_STORE( _base_ , _size_ )
    1381
    +
    1382
    +// Preread the given range into the cache with the intention of reading
    1383
    +// from it later.
    1384
    +//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
    1385
    +
    1386
    +// Preread the given range into the cache with the intention of writing
    1387
    +// to it later.
    1388
    +//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
    1389
    +
    1390
    +// Allocate and zero the cache lines associated with the given range.
    1391
    +//#define HAL_DCACHE_ZERO( _base_ , _size_ )
    1392
    +
    1393
    +//-----------------------------------------------------------------------------
    1394
    +// Global control of Instruction cache
    1395
    +
    1396
    +// Enable the instruction cache
    1397
    +#define HAL_ICACHE_ENABLE() MTSPR(SPR_SR, MFSPR(SPR_SR) | SPR_SR_ICE)
    1398
    +
    1399
    +// Disable the instruction cache
    1400
    +#define HAL_ICACHE_DISABLE() MTSPR(SPR_SR, MFSPR(SPR_SR) & ~SPR_SR_ICE)
    1401
    +
    1402
    +// Enable or disable the data cache, depending on argument, which must
    1403
    +// be 0 or 1.
    1404
    +#define HAL_SET_ICACHE_ENABLED(enable)                          \
    1405
    +    MTSPR(SPR_SR, MFSPR(SPR_SR) | (SPR_SR_ICE & -(enable)))
    1406
    +
    1407
    +// Invalidate the entire instruction cache
    1408
    +#define HAL_ICACHE_INVALIDATE_ALL()                             \
    1409
    +    CYG_MACRO_START                                             \
    1410
    +    int cache_enabled, addr;                                    \
    1411
    +                                                                \
    1412
    +    /* Save current cache mode (disabled/enabled) */            \
    1413
    +    HAL_ICACHE_IS_ENABLED(cache_enabled);                       \
    1414
    +                                                                \
    1415
    +    /* Disable cache, so that invalidation ignores cache tags */\
    1416
    +    HAL_ICACHE_DISABLE();                                       \
    1417
    +    addr = HAL_ICACHE_SIZE;                                     \
    1418
    +    do {                                                        \
    1419
    +        MTSPR(SPR_ICBIR, addr);                                 \
    1420
    +        addr -= HAL_ICACHE_LINE_SIZE;                           \
    1421
    +    } while (addr > 0);                                         \
    1422
    +                                                                \
    1423
    +    /* Re-enable cache if it was enabled on entry */            \
    1424
    +    HAL_SET_ICACHE_ENABLED(cache_enabled);                      \
    1425
    +    CYG_MACRO_END
    1426
    +
    1427
    +// Synchronize the contents of the cache with memory.
    1428
    +#define HAL_ICACHE_SYNC() HAL_ICACHE_INVALIDATE_ALL()
    1429
    +
    1430
    +// Query the state of the instruction cache
    1431
    +#define HAL_ICACHE_IS_ENABLED(_state_)                          \
    1432
    +    CYG_MACRO_START                                             \
    1433
    +    (_state_) = (1 - !(MFSPR(SPR_SR) & SPR_SR_ICE));            \
    1434
    +    CYG_MACRO_END
    1435
    +
    1436
    +
    1437
    +// Load the contents of the given address range into the instruction cache
    1438
    +// and then lock the cache so that it stays there.
    1439
    +
    1440
    +// The OpenRISC architecture defines these operations, but no
    1441
    +// implementation supports them yet.
    1442
    +
    1443
    +//#define HAL_ICACHE_LOCK(_base_, _size_)
    1444
    +
    1445
    +// Undo a previous lock operation
    1446
    +//#define HAL_ICACHE_UNLOCK(_base_, _size_)
    1447
    +
    1448
    +// Unlock entire cache
    1449
    +//#define HAL_ICACHE_UNLOCK_ALL()
    1450
    +
    1451
    +#endif /* __ASSEMBLER__ */
    1452
    +
    1453
    +#endif // ifndef CYGONCE_HAL_CACHE_H
    1454
    +// End of hal_cache.h
    1455
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/include/hal_intr.h ./ecos-3.0/packages/hal/openrisc/arch/v3_0/include/hal_intr.h
    1456
    --- /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/include/hal_intr.h    1969-12-31 16:00:00.000000000 -0800
    1457
    +++ ./ecos-3.0/packages/hal/openrisc/arch/v3_0/include/hal_intr.h       2009-09-16 14:06:24.000000000 -0700
    1458
    @@ -0,0 +1,458 @@
    1459
    +//==========================================================================
    1460
    +//
    1461
    +//      hal_intr.h
    1462
    +//
    1463
    +//      HAL Interrupt and clock support
    1464
    +//
    1465
    +//==========================================================================
    1466
    +//####ECOSGPLCOPYRIGHTBEGIN####
    1467
    +// -------------------------------------------
    1468
    +// This file is part of eCos, the Embedded Configurable Operating System.
    1469
    +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
    1470
    +//
    1471
    +// eCos is free software; you can redistribute it and/or modify it under
    1472
    +// the terms of the GNU General Public License as published by the Free
    1473
    +// Software Foundation; either version 2 or (at your option) any later version.
    1474
    +//
    1475
    +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
    1476
    +// WARRANTY; without even the implied warranty of MERCHANTABILITY or
    1477
    +// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    1478
    +// for more details.
    1479
    +//
    1480
    +// You should have received a copy of the GNU General Public License along
    1481
    +// with eCos; if not, write to the Free Software Foundation, Inc.,
    1482
    +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
    1483
    +//
    1484
    +// As a special exception, if other files instantiate templates or use macros
    1485
    +// or inline functions from this file, or you compile this file and link it
    1486
    +// with other works to produce a work based on this file, this file does not
    1487
    +// by itself cause the resulting work to be covered by the GNU General Public
    1488
    +// License. However the source code for this file must still be made available
    1489
    +// in accordance with section (3) of the GNU General Public License.
    1490
    +//
    1491
    +// This exception does not invalidate any other reasons why a work based on
    1492
    +// this file might be covered by the GNU General Public License.
    1493
    +//
    1494
    +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
    1495
    +// at http://sources.redhat.com/ecos/ecos-license/
    1496
    +// -------------------------------------------
    1497
    +//####ECOSGPLCOPYRIGHTEND####
    1498
    +//==========================================================================
    1499
    +//#####DESCRIPTIONBEGIN####
    1500
    +//
    1501
    +// Author(s):    sfurman
    1502
    +// Contributors:
    1503
    +// Date:         2003-01-24
    1504
    +// Purpose:      Define Interrupt support
    1505
    +// Description:  The macros defined here provide the HAL APIs for handling
    1506
    +//               both external interrupts and clock interrupts.
    1507
    +//
    1508
    +// Usage:
    1509
    +//              #include 
    1510
    +//              ...
    1511
    +//
    1512
    +//
    1513
    +//####DESCRIPTIONEND####
    1514
    +//
    1515
    +//==========================================================================
    1516
    +
    1517
    +#ifndef CYGONCE_HAL_HAL_INTR_H
    1518
    +#define CYGONCE_HAL_HAL_INTR_H
    1519
    +
    1520
    +#include 
    1521
    +
    1522
    +//--------------------------------------------------------------------------
    1523
    +// OpenRISC vectors.
    1524
    +
    1525
    +// These are the exception/interrupt causes defined by the hardware.
    1526
    +// These values are the ones to use for HAL_VSR_GET/SET
    1527
    +
    1528
    +// Reset
    1529
    +#define CYGNUM_HAL_VECTOR_RESET                0x01
    1530
    +
    1531
    +// Bus Error - probably invalid physical address
    1532
    +#define CYGNUM_HAL_VECTOR_BUS_ERROR            0x02
    1533
    +
    1534
    +// Either no matching page-table entry or protection fault
    1535
    +// while executing load/store operation
    1536
    +#define CYGNUM_HAL_VECTOR_DATA_PAGE_FAULT      0x03
    1537
    +
    1538
    +// Either no matching page-table entry or protection fault
    1539
    +// while fetching instruction
    1540
    +#define CYGNUM_HAL_VECTOR_INSTR_PAGE_FAULT     0x04
    1541
    +
    1542
    +// Tick Timer interrupt
    1543
    +#define CYGNUM_HAL_VECTOR_TICK_TIMER           0x05
    1544
    +
    1545
    +// Unaligned access
    1546
    +#define CYGNUM_HAL_VECTOR_UNALIGNED_ACCESS     0x06
    1547
    +
    1548
    +// Illegal instruction
    1549
    +#define CYGNUM_HAL_VECTOR_RESERVED_INSTRUCTION 0x07
    1550
    +
    1551
    +// External Interrupt from PIC
    1552
    +#define CYGNUM_HAL_VECTOR_INTERRUPT            0x08
    1553
    +
    1554
    +// D-TLB Miss
    1555
    +#define CYGNUM_HAL_VECTOR_DTLB_MISS            0x09
    1556
    +
    1557
    +// I-TLB Miss
    1558
    +#define CYGNUM_HAL_VECTOR_ITLB_MISS            0x0A
    1559
    +
    1560
    +// Numeric overflow, etc.
    1561
    +#define CYGNUM_HAL_VECTOR_RANGE                0x0B
    1562
    +
    1563
    +// System Call
    1564
    +#define CYGNUM_HAL_VECTOR_SYSTEM_CALL          0x0C
    1565
    +
    1566
    +// TRAP instruction executed
    1567
    +#define CYGNUM_HAL_VECTOR_TRAP                 0x0E
    1568
    +
    1569
    +#define CYGNUM_HAL_VSR_MIN                     CYGNUM_HAL_VECTOR_RESET
    1570
    +#define CYGNUM_HAL_VSR_MAX                     CYGNUM_HAL_VECTOR_TRAP
    1571
    +#define CYGNUM_HAL_VSR_COUNT                   (CYGNUM_HAL_VSR_MAX-CYGNUM_HAL_VSR_MIN+1)
    1572
    +
    1573
    +// Exception vectors. These are the values used when passed out to an
    1574
    +// external exception handler using cyg_hal_deliver_exception()
    1575
    +
    1576
    +#define CYGNUM_HAL_EXCEPTION_DATA_TLBMISS_ACCESS \
    1577
    +          CYGNUM_HAL_VECTOR_DTLB_MISS
    1578
    +#define CYGNUM_HAL_EXCEPTION_DATA_TLBMISS_ACCESS \
    1579
    +          CYGNUM_HAL_VECTOR_DTLB_MISS
    1580
    +#define CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_ACCESS \
    1581
    +          CYGNUM_HAL_VECTOR_UNALIGNED_ACCESS
    1582
    +#define CYGNUM_HAL_EXCEPTION_SYSTEM_CALL    CYGNUM_HAL_VECTOR_SYSTEM_CALL
    1583
    +#define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION \
    1584
    +          CYGNUM_HAL_VECTOR_RESERVED_INSTRUCTION
    1585
    +#define CYGNUM_HAL_EXCEPTION_OVERFLOW       CYGNUM_HAL_VECTOR_RANGE
    1586
    +#define CYGNUM_HAL_EXCEPTION_INTERRUPT      CYGNUM_HAL_VECTOR_INTERRUPT
    1587
    +
    1588
    +// Min/Max exception numbers and how many there are
    1589
    +#define CYGNUM_HAL_EXCEPTION_MIN                CYGNUM_HAL_VSR_MIN
    1590
    +#define CYGNUM_HAL_EXCEPTION_MAX                CYGNUM_HAL_VSR_MAX
    1591
    +#define CYGNUM_HAL_EXCEPTION_COUNT           \
    1592
    +                 ( CYGNUM_HAL_EXCEPTION_MAX - CYGNUM_HAL_EXCEPTION_MIN + 1 )
    1593
    +
    1594
    +
    1595
    +#ifndef CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
    1596
    +#define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
    1597
    +
    1598
    +// Interrupts 0-31 are connected to the PIC
    1599
    +#define CYGNUM_HAL_INTERRUPT_0                0
    1600
    +#define CYGNUM_HAL_INTERRUPT_1                1
    1601
    +#define CYGNUM_HAL_INTERRUPT_2                2
    1602
    +#define CYGNUM_HAL_INTERRUPT_3                3
    1603
    +#define CYGNUM_HAL_INTERRUPT_4                4
    1604
    +#define CYGNUM_HAL_INTERRUPT_5                5
    1605
    +#define CYGNUM_HAL_INTERRUPT_6                6
    1606
    +#define CYGNUM_HAL_INTERRUPT_7                7
    1607
    +#define CYGNUM_HAL_INTERRUPT_8                8
    1608
    +#define CYGNUM_HAL_INTERRUPT_9                9
    1609
    +#define CYGNUM_HAL_INTERRUPT_10               10
    1610
    +#define CYGNUM_HAL_INTERRUPT_11               11
    1611
    +#define CYGNUM_HAL_INTERRUPT_12               12
    1612
    +#define CYGNUM_HAL_INTERRUPT_13               13
    1613
    +#define CYGNUM_HAL_INTERRUPT_14               14
    1614
    +#define CYGNUM_HAL_INTERRUPT_15               15
    1615
    +#define CYGNUM_HAL_INTERRUPT_16               16
    1616
    +#define CYGNUM_HAL_INTERRUPT_17               17
    1617
    +#define CYGNUM_HAL_INTERRUPT_18               18
    1618
    +#define CYGNUM_HAL_INTERRUPT_19               19
    1619
    +#define CYGNUM_HAL_INTERRUPT_20               20
    1620
    +#define CYGNUM_HAL_INTERRUPT_21               21
    1621
    +#define CYGNUM_HAL_INTERRUPT_22               22
    1622
    +#define CYGNUM_HAL_INTERRUPT_23               23
    1623
    +#define CYGNUM_HAL_INTERRUPT_24               24
    1624
    +#define CYGNUM_HAL_INTERRUPT_25               25
    1625
    +#define CYGNUM_HAL_INTERRUPT_26               26
    1626
    +#define CYGNUM_HAL_INTERRUPT_27               27
    1627
    +#define CYGNUM_HAL_INTERRUPT_28               28
    1628
    +#define CYGNUM_HAL_INTERRUPT_29               29
    1629
    +#define CYGNUM_HAL_INTERRUPT_30               30
    1630
    +#define CYGNUM_HAL_INTERRUPT_31               31
    1631
    +
    1632
    +// By SW convention, interrupt #32 is the tick timer
    1633
    +#define CYGNUM_HAL_INTERRUPT_32               32
    1634
    +
    1635
    +// The interrupt vector used by the RTC, aka tick timer
    1636
    +#define CYGNUM_HAL_INTERRUPT_RTC            CYGNUM_HAL_INTERRUPT_32
    1637
    +
    1638
    +// Min/Max ISR numbers and how many there are
    1639
    +#define CYGNUM_HAL_ISR_MIN                     0
    1640
    +#define CYGNUM_HAL_ISR_MAX                     32
    1641
    +#define CYGNUM_HAL_ISR_COUNT                   33
    1642
    +
    1643
    +#endif
    1644
    +
    1645
    +#ifndef __ASSEMBLER__
    1646
    +#include 
    1647
    +
    1648
    +#include 
    1649
    +#include 
    1650
    +
    1651
    +#include 
    1652
    +
    1653
    +//--------------------------------------------------------------------------
    1654
    +// Static data used by HAL
    1655
    +
    1656
    +// ISR tables
    1657
    +externC volatile CYG_ADDRESS    hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
    1658
    +externC volatile CYG_ADDRWORD   hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];
    1659
    +externC volatile CYG_ADDRESS    hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];
    1660
    +
    1661
    +// VSR table
    1662
    +externC volatile CYG_ADDRESS    hal_vsr_table[CYGNUM_HAL_VSR_MAX+1];
    1663
    +
    1664
    +//--------------------------------------------------------------------------
    1665
    +// Default ISR
    1666
    +// The #define is used to test whether this routine exists, and to allow
    1667
    +// us to call it.
    1668
    +
    1669
    +externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
    1670
    +
    1671
    +#define HAL_DEFAULT_ISR hal_default_isr
    1672
    +
    1673
    +//--------------------------------------------------------------------------
    1674
    +// Interrupt state storage
    1675
    +
    1676
    +typedef cyg_uint32 CYG_INTERRUPT_STATE;
    1677
    +
    1678
    +//--------------------------------------------------------------------------
    1679
    +// Interrupt control macros
    1680
    +#ifndef CYGHWR_HAL_INTERRUPT_ENABLE_DISABLE_RESTORE_DEFINED
    1681
    +
    1682
    +// Clear both tick timer and external interrupts in the Supervisor Register
    1683
    +#define HAL_DISABLE_INTERRUPTS(_old_)                     \
    1684
    +    CYG_MACRO_START                                       \
    1685
    +    _old_ = MFSPR(SPR_SR);                                \
    1686
    +    MTSPR(SPR_SR, _old_ & ~(SPR_SR_IEE|SPR_SR_TEE));      \
    1687
    +    CYG_MACRO_END
    1688
    +
    1689
    +// Enable both tick timer and external interrupts in the Supervisor Register
    1690
    +#define HAL_ENABLE_INTERRUPTS()                           \
    1691
    +    MTSPR(SPR_SR, MFSPR(SPR_SR) | (SPR_SR_IEE|SPR_SR_TEE))
    1692
    +
    1693
    +// Copy interrupt flags from argument into Supervisor Register
    1694
    +#define HAL_RESTORE_INTERRUPTS(_old_)                     \
    1695
    +    CYG_MACRO_START                                       \
    1696
    +    cyg_uint32 t1,t2;                                     \
    1697
    +    t1 = MFSPR(SPR_SR) & ~(SPR_SR_IEE|SPR_SR_TEE);        \
    1698
    +    t2 = (_old_) & (SPR_SR_IEE|SPR_SR_TEE);               \
    1699
    +    MTSPR(SPR_SR, t1 | t2);                               \
    1700
    +    CYG_MACRO_END
    1701
    +
    1702
    +#define HAL_QUERY_INTERRUPTS( _state_ )                   \
    1703
    +    CYG_MACRO_START                                       \
    1704
    +    _state = MFSPR(SPR_SR);                               \
    1705
    +    CYG_MACRO_END
    1706
    +
    1707
    +#endif // CYGHWR_HAL_INTERRUPT_ENABLE_DISABLE_RESTORE_DEFINED
    1708
    +
    1709
    +//--------------------------------------------------------------------------
    1710
    +// Routine to execute DSRs using separate interrupt stack
    1711
    +
    1712
    +#ifdef  CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
    1713
    +externC void hal_interrupt_stack_call_pending_DSRs(void);
    1714
    +#define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \
    1715
    +    hal_interrupt_stack_call_pending_DSRs()
    1716
    +
    1717
    +// these are offered solely for stack usage testing
    1718
    +// if they are not defined, then there is no interrupt stack.
    1719
    +#define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base
    1720
    +#define HAL_INTERRUPT_STACK_TOP  cyg_interrupt_stack
    1721
    +// use them to declare these extern however you want:
    1722
    +//       extern char HAL_INTERRUPT_STACK_BASE[];
    1723
    +//       extern char HAL_INTERRUPT_STACK_TOP[];
    1724
    +// is recommended
    1725
    +#endif
    1726
    +
    1727
    +//--------------------------------------------------------------------------
    1728
    +// Vector translation.
    1729
    +// For chained interrupts we only have a single vector though which all
    1730
    +// are passed. For unchained interrupts we have a vector per interrupt.
    1731
    +
    1732
    +#ifndef HAL_TRANSLATE_VECTOR
    1733
    +
    1734
    +#if defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN)
    1735
    +
    1736
    +#define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = 0
    1737
    +
    1738
    +#else
    1739
    +
    1740
    +#define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = (_vector_)
    1741
    +
    1742
    +#endif
    1743
    +
    1744
    +#endif
    1745
    +
    1746
    +//--------------------------------------------------------------------------
    1747
    +// Interrupt and VSR attachment macros
    1748
    +
    1749
    +#define HAL_INTERRUPT_IN_USE( _vector_, _state_)                          \
    1750
    +    CYG_MACRO_START                                                       \
    1751
    +    cyg_uint32 _index_;                                                   \
    1752
    +    HAL_TRANSLATE_VECTOR ((_vector_), _index_);                           \
    1753
    +                                                                          \
    1754
    +    if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR ) \
    1755
    +        (_state_) = 0;                                                    \
    1756
    +    else                                                                  \
    1757
    +        (_state_) = 1;                                                    \
    1758
    +    CYG_MACRO_END
    1759
    +
    1760
    +#define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ )           \
    1761
    +{                                                                           \
    1762
    +    cyg_uint32 _index_;                                                     \
    1763
    +    HAL_TRANSLATE_VECTOR( _vector_, _index_ );                              \
    1764
    +                                                                            \
    1765
    +    if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR )   \
    1766
    +    {                                                                       \
    1767
    +        hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_;               \
    1768
    +        hal_interrupt_data[_index_] = (CYG_ADDRWORD)_data_;                 \
    1769
    +        hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_;             \
    1770
    +    }                                                                       \
    1771
    +}
    1772
    +
    1773
    +#define HAL_INTERRUPT_DETACH( _vector_, _isr_ )                         \
    1774
    +{                                                                       \
    1775
    +    cyg_uint32 _index_;                                                 \
    1776
    +    HAL_TRANSLATE_VECTOR( _vector_, _index_ );                          \
    1777
    +                                                                        \
    1778
    +    if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ )         \
    1779
    +    {                                                                   \
    1780
    +        hal_interrupt_handlers[_index_] = (CYG_ADDRESS)HAL_DEFAULT_ISR; \
    1781
    +        hal_interrupt_data[_index_] = 0;                                \
    1782
    +        hal_interrupt_objects[_index_] = 0;                             \
    1783
    +    }                                                                   \
    1784
    +}
    1785
    +
    1786
    +#define HAL_VSR_GET( _vector_, _pvsr_ )                 \
    1787
    +    *(_pvsr_) = (void (*)())hal_vsr_table[_vector_];
    1788
    +
    1789
    +
    1790
    +#define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) CYG_MACRO_START         \
    1791
    +    if( (void*)_poldvsr_ != NULL)                                         \
    1792
    +        *(CYG_ADDRESS *)_poldvsr_ = (CYG_ADDRESS)hal_vsr_table[_vector_]; \
    1793
    +    hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_;                         \
    1794
    +CYG_MACRO_END
    1795
    +
    1796
    +// This is an ugly name, but what it means is: grab the VSR back to eCos
    1797
    +// internal handling, or if you like, the default handler.  But if
    1798
    +// cooperating with GDB and CygMon, the default behaviour is to pass most
    1799
    +// exceptions to CygMon.  This macro undoes that so that eCos handles the
    1800
    +// exception.  So use it with care.
    1801
    +
    1802
    +externC void cyg_hal_default_exception_vsr(void);
    1803
    +externC void cyg_hal_default_interrupt_vsr(void);
    1804
    +
    1805
    +#define HAL_VSR_SET_TO_ECOS_HANDLER( _vector_, _poldvsr_ ) CYG_MACRO_START  \
    1806
    +    HAL_VSR_SET( _vector_, _vector_ == CYGNUM_HAL_VECTOR_INTERRUPT          \
    1807
    +                              ? (CYG_ADDRESS)cyg_hal_default_interrupt_vsr  \
    1808
    +                              : (CYG_ADDRESS)cyg_hal_default_exception_vsr, \
    1809
    +                 _poldvsr_ );                                               \
    1810
    +CYG_MACRO_END
    1811
    +
    1812
    +//--------------------------------------------------------------------------
    1813
    +// Interrupt controller access
    1814
    +
    1815
    +#ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
    1816
    +#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
    1817
    +
    1818
    +// Mask (disable) interrupts from specified source
    1819
    +#define HAL_INTERRUPT_MASK( _vector_ )            \
    1820
    +CYG_MACRO_START                                   \
    1821
    +    int mask;                                     \
    1822
    +    if ((_vector_) == CYGNUM_HAL_INTERRUPT_RTC) { \
    1823
    +        /* The tick timer interrupt isn't */      \
    1824
    +        /* controlled by the PIC; It has its own*/\
    1825
    +        /* enable bit in the SR. */               \
    1826
    +        MTSPR(SPR_SR, MFSPR(SPR_SR)& ~SPR_SR_TEE);\
    1827
    +    } else {                                      \
    1828
    +        mask = ~(1 << (_vector_));                \
    1829
    +        MTSPR(SPR_PICMR, MFSPR(SPR_PICMR)& mask); \
    1830
    +    }                                             \
    1831
    +CYG_MACRO_END
    1832
    +
    1833
    +// Allow interrupts from specified source
    1834
    +#define HAL_INTERRUPT_UNMASK( _vector_ )          \
    1835
    +CYG_MACRO_START                                   \
    1836
    +    int bit;                                      \
    1837
    +    if ((_vector_) == CYGNUM_HAL_INTERRUPT_RTC) { \
    1838
    +        /* The tick timer interrupt isn't */      \
    1839
    +        /* controlled by the PIC; It has its own*/\
    1840
    +        /* enable bit in the SR. */               \
    1841
    +        MTSPR(SPR_SR, MFSPR(SPR_SR) | SPR_SR_TEE);\
    1842
    +    } else {                                      \
    1843
    +        bit = (1 << (_vector_));                  \
    1844
    +        MTSPR(SPR_PICMR, MFSPR(SPR_PICMR) | bit); \
    1845
    +    }                                             \
    1846
    +CYG_MACRO_END
    1847
    +
    1848
    +// Reset interrupt request in the PIC for specified device
    1849
    +#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ )     \
    1850
    +CYG_MACRO_START                                   \
    1851
    +    int mask;                                     \
    1852
    +    if ((_vector_) != CYGNUM_HAL_INTERRUPT_RTC) { \
    1853
    +        mask = ~(1 << (_vector_));                \
    1854
    +        MTSPR(SPR_PICSR, MFSPR(SPR_PICSR) & mask);\
    1855
    +    }                                             \
    1856
    +CYG_MACRO_END
    1857
    +
    1858
    +#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) CYG_EMPTY_STATEMENT
    1859
    +
    1860
    +#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ )  CYG_EMPTY_STATEMENT
    1861
    +
    1862
    +#endif
    1863
    +
    1864
    +//--------------------------------------------------------------------------
    1865
    +// Clock control.
    1866
    +
    1867
    +externC CYG_WORD32 cyg_hal_clock_period;
    1868
    +#define CYGHWR_HAL_CLOCK_PERIOD_DEFINED
    1869
    +
    1870
    +// Start tick timer interrupts
    1871
    +#define HAL_CLOCK_INITIALIZE( _period_ )        \
    1872
    +CYG_MACRO_START                                 \
    1873
    +{                                               \
    1874
    +    int ttmr_new = _period_ | 0x60000000;       \
    1875
    +    MTSPR(SPR_TTMR, 0);                         \
    1876
    +    MTSPR(SPR_TTCR, 0);                         \
    1877
    +    MTSPR(SPR_TTMR, ttmr_new);                  \
    1878
    +    cyg_hal_clock_period = _period_;            \
    1879
    +}                                               \
    1880
    +CYG_MACRO_END
    1881
    +
    1882
    +// Acknowledge clock timer interrupt
    1883
    +#define HAL_CLOCK_RESET( _vector_, _period_ )   \
    1884
    +CYG_MACRO_START                                 \
    1885
    +    int ttmr_new = _period_ | 0x60000000;       \
    1886
    +    MTSPR(SPR_TTMR, ttmr_new);                  \
    1887
    +CYG_MACRO_END
    1888
    +
    1889
    +// Read the current value of the tick timer
    1890
    +#define HAL_CLOCK_READ( _pvalue_ )              \
    1891
    +CYG_MACRO_START                                 \
    1892
    +    *(_pvalue_) = MFSPR(SPR_TTCR);              \
    1893
    +CYG_MACRO_END
    1894
    +
    1895
    +#if defined(CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY) && \
    1896
    +    !defined(HAL_CLOCK_LATENCY)
    1897
    +#define HAL_CLOCK_LATENCY( _pvalue_ )                   \
    1898
    +CYG_MACRO_START                                         \
    1899
    +    register CYG_WORD32 _cval_;                         \
    1900
    +    HAL_CLOCK_READ(&_cval_);                            \
    1901
    +    *(_pvalue_) = _cval_ - cyg_hal_clock_period;        \
    1902
    +CYG_MACRO_END
    1903
    +#endif
    1904
    +
    1905
    +
    1906
    +//--------------------------------------------------------------------------
    1907
    +// Microsecond delay function provided in hal_misc.c
    1908
    +externC void hal_delay_us(int us);
    1909
    +
    1910
    +#define HAL_DELAY_US(n)          hal_delay_us(n)
    1911
    +
    1912
    +#endif /* #ifndef __ASSEMBLER__ */
    1913
    +
    1914
    +//--------------------------------------------------------------------------
    1915
    +#endif // ifndef CYGONCE_HAL_HAL_INTR_H
    1916
    +// End of hal_intr.h
    1917
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/include/hal_io.h ./ecos-3.0/packages/hal/openrisc/arch/v3_0/include/hal_io.h
    1918
    --- /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/include/hal_io.h      1969-12-31 16:00:00.000000000 -0800
    1919
    +++ ./ecos-3.0/packages/hal/openrisc/arch/v3_0/include/hal_io.h 2009-09-16 14:06:24.000000000 -0700
    1920
    @@ -0,0 +1,158 @@
    1921
    +#ifndef CYGONCE_HAL_HAL_IO_H
    1922
    +#define CYGONCE_HAL_HAL_IO_H
    1923
    +
    1924
    +//=============================================================================
    1925
    +//
    1926
    +//      hal_io.h
    1927
    +//
    1928
    +//      HAL device IO register support.
    1929
    +//
    1930
    +//=============================================================================
    1931
    +//####ECOSGPLCOPYRIGHTBEGIN####
    1932
    +// -------------------------------------------
    1933
    +// This file is part of eCos, the Embedded Configurable Operating System.
    1934
    +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
    1935
    +//
    1936
    +// eCos is free software; you can redistribute it and/or modify it under
    1937
    +// the terms of the GNU General Public License as published by the Free
    1938
    +// Software Foundation; either version 2 or (at your option) any later version.
    1939
    +//
    1940
    +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
    1941
    +// WARRANTY; without even the implied warranty of MERCHANTABILITY or
    1942
    +// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    1943
    +// for more details.
    1944
    +//
    1945
    +// You should have received a copy of the GNU General Public License along
    1946
    +// with eCos; if not, write to the Free Software Foundation, Inc.,
    1947
    +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
    1948
    +//
    1949
    +// As a special exception, if other files instantiate templates or use macros
    1950
    +// or inline functions from this file, or you compile this file and link it
    1951
    +// with other works to produce a work based on this file, this file does not
    1952
    +// by itself cause the resulting work to be covered by the GNU General Public
    1953
    +// License. However the source code for this file must still be made available
    1954
    +// in accordance with section (3) of the GNU General Public License.
    1955
    +//
    1956
    +// This exception does not invalidate any other reasons why a work based on
    1957
    +// this file might be covered by the GNU General Public License.
    1958
    +//
    1959
    +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
    1960
    +// at http://sources.redhat.com/ecos/ecos-license/
    1961
    +// -------------------------------------------
    1962
    +//####ECOSGPLCOPYRIGHTEND####
    1963
    +//=============================================================================
    1964
    +//#####DESCRIPTIONBEGIN####
    1965
    +//
    1966
    +// Author(s):   nickg
    1967
    +// Contributors:        nickg
    1968
    +// Date:        2003-02-28
    1969
    +// Purpose:     Define IO register support
    1970
    +// Description: The macros defined here provide the HAL APIs for handling
    1971
    +//              device IO control registers.
    1972
    +//
    1973
    +// Usage:
    1974
    +//              #include 
    1975
    +//              ...
    1976
    +//
    1977
    +//
    1978
    +//####DESCRIPTIONEND####
    1979
    +//
    1980
    +//=============================================================================
    1981
    +
    1982
    +#include 
    1983
    +
    1984
    +#include 
    1985
    +
    1986
    +//#include 
    1987
    +
    1988
    +//-----------------------------------------------------------------------------
    1989
    +// IO Register address.
    1990
    +// This type is for recording the address of an IO register.
    1991
    +
    1992
    +typedef volatile CYG_ADDRWORD HAL_IO_REGISTER;
    1993
    +
    1994
    +//-----------------------------------------------------------------------------
    1995
    +// HAL IO macros.
    1996
    +#ifndef HAL_IO_MACROS_DEFINED
    1997
    +
    1998
    +//-----------------------------------------------------------------------------
    1999
    +// BYTE Register access.
    2000
    +// Individual and vectorized access to 8 bit registers.
    2001
    +
    2002
    +#define HAL_READ_UINT8( _register_, _value_ ) \
    2003
    +        ((_value_) = *((volatile CYG_BYTE *)(_register_)))
    2004
    +
    2005
    +#define HAL_WRITE_UINT8( _register_, _value_ ) \
    2006
    +        (*((volatile CYG_BYTE *)(_register_)) = (_value_))
    2007
    +
    2008
    +#define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ )     \
    2009
    +{                                                                       \
    2010
    +    cyg_count32 _i_,_j_;                                                \
    2011
    +    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \
    2012
    +        (_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_j_];        \
    2013
    +}
    2014
    +
    2015
    +#define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ )    \
    2016
    +{                                                                       \
    2017
    +    cyg_count32 _i_,_j_;                                                \
    2018
    +    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \
    2019
    +        ((volatile CYG_BYTE *)(_register_))[_j_] = (_buf_)[_i_];        \
    2020
    +}
    2021
    +
    2022
    +
    2023
    +//-----------------------------------------------------------------------------
    2024
    +// 16 bit access.
    2025
    +// Individual and vectorized access to 16 bit registers.
    2026
    +
    2027
    +#define HAL_READ_UINT16( _register_, _value_ ) \
    2028
    +        ((_value_) = *((volatile CYG_WORD16 *)(_register_)))
    2029
    +
    2030
    +#define HAL_WRITE_UINT16( _register_, _value_ ) \
    2031
    +        (*((volatile CYG_WORD16 *)(_register_)) = (_value_))
    2032
    +
    2033
    +#define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ )    \
    2034
    +{                                                                       \
    2035
    +    cyg_count32 _i_,_j_;                                                \
    2036
    +    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \
    2037
    +        (_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_j_];      \
    2038
    +}
    2039
    +
    2040
    +#define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ )   \
    2041
    +{                                                                       \
    2042
    +    cyg_count32 _i_,_j_;                                                \
    2043
    +    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \
    2044
    +        ((volatile CYG_WORD16 *)(_register_))[_j_] = (_buf_)[_i_];      \
    2045
    +}
    2046
    +
    2047
    +//-----------------------------------------------------------------------------
    2048
    +// 32 bit access.
    2049
    +// Individual and vectorized access to 32 bit registers.
    2050
    +
    2051
    +#define HAL_READ_UINT32( _register_, _value_ ) \
    2052
    +        ((_value_) = *((volatile CYG_WORD32 *)(_register_)))
    2053
    +
    2054
    +#define HAL_WRITE_UINT32( _register_, _value_ ) \
    2055
    +        (*((volatile CYG_WORD32 *)(_register_)) = (_value_))
    2056
    +
    2057
    +#define HAL_READ_UINT32_VECTOR( _register_, _buf_, _count_, _step_ )    \
    2058
    +{                                                                       \
    2059
    +    cyg_count32 _i_,_j_;                                                \
    2060
    +    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \
    2061
    +        (_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_j_];      \
    2062
    +}
    2063
    +
    2064
    +#define HAL_WRITE_UINT32_VECTOR( _register_, _buf_, _count_, _step_ )   \
    2065
    +{                                                                       \
    2066
    +    cyg_count32 _i_,_j_;                                                \
    2067
    +    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \
    2068
    +        ((volatile CYG_WORD32 *)(_register_))[_j_] = (_buf_)[_i_];      \
    2069
    +}
    2070
    +
    2071
    +#define HAL_IO_MACROS_DEFINED
    2072
    +
    2073
    +#endif
    2074
    +
    2075
    +
    2076
    +//-----------------------------------------------------------------------------
    2077
    +#endif // ifndef CYGONCE_HAL_HAL_IO_H
    2078
    +// End of hal_io.h
    2079
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/include/openrisc.inc ./ecos-3.0/packages/hal/openrisc/arch/v3_0/include/openrisc.inc
    2080
    --- /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/include/openrisc.inc  1969-12-31 16:00:00.000000000 -0800
    2081
    +++ ./ecos-3.0/packages/hal/openrisc/arch/v3_0/include/openrisc.inc     2009-09-16 14:06:26.000000000 -0700
    2082
    @@ -0,0 +1,59 @@
    2083
    +# ====================================================================
    2084
    +#
    2085
    +#      openrisc.inc
    2086
    +#
    2087
    +#      OpenRISC architectural definitions for assembly code
    2088
    +#
    2089
    +# ====================================================================
    2090
    +#####ECOSGPLCOPYRIGHTBEGIN####
    2091
    +## -------------------------------------------
    2092
    +## This file is part of eCos, the Embedded Configurable Operating System.
    2093
    +## Copyright (C) 2003 Red Hat, Inc.
    2094
    +##
    2095
    +## eCos is free software; you can redistribute it and/or modify it under
    2096
    +## the terms of the GNU General Public License as published by the Free
    2097
    +## Software Foundation; either version 2 or (at your option) any later version.
    2098
    +##
    2099
    +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
    2100
    +## WARRANTY; without even the implied warranty of MERCHANTABILITY or
    2101
    +## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    2102
    +## for more details.
    2103
    +##
    2104
    +## You should have received a copy of the GNU General Public License along
    2105
    +## with eCos; if not, write to the Free Software Foundation, Inc.,
    2106
    +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
    2107
    +##
    2108
    +## As a special exception, if other files instantiate templates or use macros
    2109
    +## or inline functions from this file, or you compile this file and link it
    2110
    +## with other works to produce a work based on this file, this file does not
    2111
    +## by itself cause the resulting work to be covered by the GNU General Public
    2112
    +## License. However the source code for this file must still be made available
    2113
    +## in accordance with section (3) of the GNU General Public License.
    2114
    +##
    2115
    +## This exception does not invalidate any other reasons why a work based on
    2116
    +## this file might be covered by the GNU General Public License.
    2117
    +##
    2118
    +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
    2119
    +## at http://sources.redhat.com/ecos/ecos-license/
    2120
    +## -------------------------------------------
    2121
    +#####ECOSGPLCOPYRIGHTEND####
    2122
    +# ====================================================================
    2123
    +######DESCRIPTIONBEGIN####
    2124
    +#
    2125
    +# Author(s):      sfurman
    2126
    +# Original data:
    2127
    +# Contributors:
    2128
    +# Date:           2003-02-28
    2129
    +#
    2130
    +#####DESCRIPTIONEND####
    2131
    +#
    2132
    +# ====================================================================
    2133
    +
    2134
    +
    2135
    +#ifndef _OPENRISC_INC_
    2136
    +#define _OPENRISC_INC_
    2137
    +
    2138
    +/* Definition of special-purpose registers (SPRs) */
    2139
    +#include 
    2140
    +
    2141
    +#endif /* ifdef _OPENRISC_INC_ */
    2142
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/include/openrisc_opcode.h ./ecos-3.0/packages/hal/openrisc/arch/v3_0/include/openrisc_opcode.h
    2143
    --- /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/include/openrisc_opcode.h     1969-12-31 16:00:00.000000000 -0800
    2144
    +++ ./ecos-3.0/packages/hal/openrisc/arch/v3_0/include/openrisc_opcode.h        2009-09-16 14:06:24.000000000 -0700
    2145
    @@ -0,0 +1,92 @@
    2146
    +//=============================================================================
    2147
    +//
    2148
    +//      openrisc_opcode.h
    2149
    +//
    2150
    +//  Define the instruction formats and opcode values for the OpenRISC
    2151
    +//  instruction set...or at least just enough of them to implement
    2152
    +//  single-stepping.
    2153
    +//
    2154
    +//=============================================================================
    2155
    +//####ECOSGPLCOPYRIGHTBEGIN####
    2156
    +// -------------------------------------------
    2157
    +// This file is part of eCos, the Embedded Configurable Operating System.
    2158
    +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
    2159
    +//
    2160
    +// eCos is free software; you can redistribute it and/or modify it under
    2161
    +// the terms of the GNU General Public License as published by the Free
    2162
    +// Software Foundation; either version 2 or (at your option) any later version.
    2163
    +//
    2164
    +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
    2165
    +// WARRANTY; without even the implied warranty of MERCHANTABILITY or
    2166
    +// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    2167
    +// for more details.
    2168
    +//
    2169
    +// You should have received a copy of the GNU General Public License along
    2170
    +// with eCos; if not, write to the Free Software Foundation, Inc.,
    2171
    +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
    2172
    +//
    2173
    +// As a special exception, if other files instantiate templates or use macros
    2174
    +// or inline functions from this file, or you compile this file and link it
    2175
    +// with other works to produce a work based on this file, this file does not
    2176
    +// by itself cause the resulting work to be covered by the GNU General Public
    2177
    +// License. However the source code for this file must still be made available
    2178
    +// in accordance with section (3) of the GNU General Public License.
    2179
    +//
    2180
    +// This exception does not invalidate any other reasons why a work based on
    2181
    +// this file might be covered by the GNU General Public License.
    2182
    +//
    2183
    +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
    2184
    +// at http://sources.redhat.com/ecos/ecos-license/
    2185
    +// -------------------------------------------
    2186
    +//####ECOSGPLCOPYRIGHTEND####
    2187
    +//=============================================================================
    2188
    +//#####DESCRIPTIONBEGIN####
    2189
    +//
    2190
    +// Author(s):   sfurman
    2191
    +// Contributors:
    2192
    +// Date:        2003-02-28
    2193
    +// Purpose:     Allow dissection of OpenRISC instructions
    2194
    +// Description: The types and macros defined here define the instruction
    2195
    +//              formats of the OpenRISC instruction set...or at least the
    2196
    +//              very limited subset necessary to allow single-stepping.
    2197
    +//
    2198
    +//####DESCRIPTIONEND####
    2199
    +//
    2200
    +//=============================================================================
    2201
    +
    2202
    +#ifndef _OPENRISC_OPCODE_H
    2203
    +#define _OPENRISC_OPCODE_H
    2204
    +
    2205
    +
    2206
    +// Define the instruction formats.
    2207
    +typedef union {
    2208
    +    unsigned word;
    2209
    +
    2210
    +    // (Possibly conditional) relative jump w/ immediate displacement
    2211
    +    struct {
    2212
    +        unsigned op:      6;    // OP_J, OP_JAL, OP_BNF, or OP_BF
    2213
    +        signed   target: 26;
    2214
    +    } JType;
    2215
    +
    2216
    +    // Absolute jump w/ register contents used as PC target address
    2217
    +    struct {
    2218
    +        unsigned op:      6;   // OP_JR or OP_JALR
    2219
    +        unsigned unused1:10;
    2220
    +        unsigned rB:      5;   // Register containing new PC
    2221
    +        unsigned unused2:11;
    2222
    +    } JRType;
    2223
    +
    2224
    +} InstFmt;
    2225
    +
    2226
    +/*
    2227
    + * Values for the 'op' field.
    2228
    + */
    2229
    +#define OP_J            0x00
    2230
    +#define OP_JAL          0x01
    2231
    +#define OP_BNF          0x03
    2232
    +#define OP_BF           0x04
    2233
    +#define OP_RFE          0x09
    2234
    +#define OP_JR           0x11
    2235
    +#define OP_JALR         0x12
    2236
    +
    2237
    +#endif  /* _OPENRISC_OPCODE_H */
    2238
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/include/openrisc_stub.h ./ecos-3.0/packages/hal/openrisc/arch/v3_0/include/openrisc_stub.h
    2239
    --- /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/include/openrisc_stub.h       1969-12-31 16:00:00.000000000 -0800
    2240
    +++ ./ecos-3.0/packages/hal/openrisc/arch/v3_0/include/openrisc_stub.h  2009-09-16 14:06:24.000000000 -0700
    2241
    @@ -0,0 +1,166 @@
    2242
    +//========================================================================
    2243
    +//
    2244
    +//      openrisc_stub.h
    2245
    +//
    2246
    +//      OpenRISC-specific definitions for remote debugging via gdb
    2247
    +//
    2248
    +//========================================================================
    2249
    +//####ECOSGPLCOPYRIGHTBEGIN####
    2250
    +// -------------------------------------------
    2251
    +// This file is part of eCos, the Embedded Configurable Operating System.
    2252
    +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
    2253
    +//
    2254
    +// eCos is free software; you can redistribute it and/or modify it under
    2255
    +// the terms of the GNU General Public License as published by the Free
    2256
    +// Software Foundation; either version 2 or (at your option) any later version.
    2257
    +//
    2258
    +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
    2259
    +// WARRANTY; without even the implied warranty of MERCHANTABILITY or
    2260
    +// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    2261
    +// for more details.
    2262
    +//
    2263
    +// You should have received a copy of the GNU General Public License along
    2264
    +// with eCos; if not, write to the Free Software Foundation, Inc.,
    2265
    +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
    2266
    +//
    2267
    +// As a special exception, if other files instantiate templates or use macros
    2268
    +// or inline functions from this file, or you compile this file and link it
    2269
    +// with other works to produce a work based on this file, this file does not
    2270
    +// by itself cause the resulting work to be covered by the GNU General Public
    2271
    +// License. However the source code for this file must still be made available
    2272
    +// in accordance with section (3) of the GNU General Public License.
    2273
    +//
    2274
    +// This exception does not invalidate any other reasons why a work based on
    2275
    +// this file might be covered by the GNU General Public License.
    2276
    +//
    2277
    +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
    2278
    +// at http://sources.redhat.com/ecos/ecos-license/
    2279
    +// -------------------------------------------
    2280
    +//####ECOSGPLCOPYRIGHTEND####
    2281
    +//========================================================================
    2282
    +//#####DESCRIPTIONBEGIN####
    2283
    +//
    2284
    +// Author(s):   sfurman
    2285
    +// Contributors:Red Hat, nickg, dmoseley
    2286
    +// Date:        2003-02-18
    2287
    +// Purpose:     OpenRISC-specific definitions for gdb stubs support
    2288
    +//
    2289
    +//
    2290
    +//####DESCRIPTIONEND####
    2291
    +//
    2292
    +//=============================================================================
    2293
    +
    2294
    +#ifndef CYGONCE_HAL_OPENRISC_STUB_H
    2295
    +#define CYGONCE_HAL_OPENRISC_STUB_H
    2296
    +
    2297
    +#include 
    2298
    +#include 
    2299
    +
    2300
    +#ifdef CYGPKG_IO_SERIAL
    2301
    +#include 
    2302
    +#endif
    2303
    +
    2304
    +#include 
    2305
    +
    2306
    +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
    2307
    +
    2308
    +#include          // CYG_UNUSED_PARAM, externC
    2309
    +
    2310
    +#define HAL_STUB_PLATFORM_INIT_SERIAL()       HAL_DIAG_INIT()
    2311
    +
    2312
    +#define HAL_STUB_PLATFORM_GET_CHAR()                                        \
    2313
    +((cyg_int8)({                                                               \
    2314
    +    cyg_int8 _ch_;                                                          \
    2315
    +    HAL_DIAG_READ_CHAR(_ch_);                                               \
    2316
    +    _ch_;                                                                   \
    2317
    +}))
    2318
    +
    2319
    +#define HAL_STUB_PLATFORM_PUT_CHAR(c)         HAL_DIAG_WRITE_CHAR((c))
    2320
    +
    2321
    +#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int,(baud))
    2322
    +
    2323
    +#define HAL_STUB_PLATFORM_RESET()             HAL_DIAG_INIT()
    2324
    +
    2325
    +#define HAL_STUB_PLATFORM_INIT()              HAL_DIAG_INIT()
    2326
    +
    2327
    +#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
    2328
    +
    2329
    +// 32 GPRs + 32 VFRs + PC reg + SR reg
    2330
    +#define NUMREGS 66
    2331
    +
    2332
    +// VFR regs are unimplemented so they are 0 bytes in length
    2333
    +#define REGSIZE( _x_ ) ((((_x_) <= R31) || ((_x_) > VFR31)) ? 4 : 0)
    2334
    +
    2335
    +typedef unsigned long target_register_t;
    2336
    +
    2337
    +enum regnames {
    2338
    +     R0,   SP,   R2,   R3,   R4,   R5,   R6,   R7,
    2339
    +     R8,   R9,  R10,  R11,  R12,  R13,  R14,  R15,
    2340
    +    R16,  R17,  R18,  R19,  R20,  R21,  R22,  R23,
    2341
    +    R24,  R25,  R26,  R27,  R28,  R29,  R30,  R31,
    2342
    +
    2343
    +
    2344
    +     // Vector/Float registers, which are as yet unimplemented,
    2345
    +     // but defined in the or32 gdb back-end.
    2346
    +
    2347
    +    VFR0,  VFR1,  VFR2,  VFR3,  VFR4,  VFR5,  VFR6,  VFR7,
    2348
    +    VFR8,  VFR9, VFR10, VFR11, VFR12, VFR13, VFR14, VFR15,
    2349
    +   VFR16, VFR17, VFR18, VFR19, VFR20, VFR21, VFR22, VFR23,
    2350
    +   VFR24, VFR25, VFR26, VFR27, VFR28, VFR29, VFR30, VFR31,
    2351
    +
    2352
    +     // Special-purpose registers
    2353
    +      PC,    SR
    2354
    +};
    2355
    +
    2356
    +typedef enum regnames regnames_t;
    2357
    +
    2358
    +// Override generic stubs get_register() and use arch-specific version
    2359
    +#define CYGARC_STUB_REGISTER_ACCESS_DEFINED
    2360
    +
    2361
    +#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) || defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT)
    2362
    +#define HAL_GET_PROFILE_INFO( _thepc_, _thesp_ )                \
    2363
    +    CYG_MACRO_START                                             \
    2364
    +    extern HAL_SavedRegisters *hal_saved_interrupt_state;       \
    2365
    +    if ( hal_saved_interrupt_state ) {                          \
    2366
    +        (_thepc_) = (char *)(hal_saved_interrupt_state->pc);    \
    2367
    +        (_thesp_) = (char *)(hal_saved_interrupt_state->sp);    \
    2368
    +    }                                                           \
    2369
    +    CYG_MACRO_END
    2370
    +#endif
    2371
    +
    2372
    +/* Given a trap value TRAP, return the corresponding signal. */
    2373
    +externC int __computeSignal (unsigned int trap_number);
    2374
    +
    2375
    +/* Return the trap number corresponding to the last-taken trap. */
    2376
    +externC int __get_trap_number (void);
    2377
    +
    2378
    +/* Return the currently-saved value corresponding to register REG. */
    2379
    +externC target_register_t get_register (regnames_t reg);
    2380
    +
    2381
    +/* Store VALUE in the register corresponding to WHICH. */
    2382
    +externC void put_register (regnames_t which, target_register_t value);
    2383
    +
    2384
    +/* Set the currently-saved pc register value to PC. This also updates NPC
    2385
    +   as needed. */
    2386
    +externC void set_pc (target_register_t pc);
    2387
    +
    2388
    +/* Set things up so that the next user resume will execute one instruction.
    2389
    +   This may be done by setting breakpoints or setting a single step flag
    2390
    +   in the saved user registers, for example. */
    2391
    +externC void __single_step (void);
    2392
    +
    2393
    +/* Clear the single-step state. */
    2394
    +externC void __clear_single_step (void);
    2395
    +
    2396
    +/* If the breakpoint we hit is in the breakpoint() instruction, return a
    2397
    +   non-zero value. */
    2398
    +externC int __is_breakpoint_function (void);
    2399
    +
    2400
    +/* Skip the current instruction. */
    2401
    +externC void __skipinst (void);
    2402
    +
    2403
    +externC void __install_breakpoints (void);
    2404
    +
    2405
    +externC void __clear_breakpoints (void);
    2406
    +
    2407
    +#endif // ifndef CYGONCE_HAL_OPENRISC_STUB_H
    2408
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/include/spr_defs.h ./ecos-3.0/packages/hal/openrisc/arch/v3_0/include/spr_defs.h
    2409
    --- /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/include/spr_defs.h    1969-12-31 16:00:00.000000000 -0800
    2410
    +++ ./ecos-3.0/packages/hal/openrisc/arch/v3_0/include/spr_defs.h       2009-09-16 14:06:26.000000000 -0700
    2411
    @@ -0,0 +1,464 @@
    2412
    +//==========================================================================
    2413
    +//
    2414
    +//      spr_defs.h
    2415
    +//
    2416
    +//      Defines OR1K architecture specific special-purpose registers (SPRs)
    2417
    +//
    2418
    +//==========================================================================
    2419
    +//####ECOSGPLCOPYRIGHTBEGIN####
    2420
    +// -------------------------------------------
    2421
    +// This file is part of eCos, the Embedded Configurable Operating System.
    2422
    +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
    2423
    +//
    2424
    +// eCos is free software; you can redistribute it and/or modify it under
    2425
    +// the terms of the GNU General Public License as published by the Free
    2426
    +// Software Foundation; either version 2 or (at your option) any later version.
    2427
    +//
    2428
    +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
    2429
    +// WARRANTY; without even the implied warranty of MERCHANTABILITY or
    2430
    +// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    2431
    +// for more details.
    2432
    +//
    2433
    +// You should have received a copy of the GNU General Public License along
    2434
    +// with eCos; if not, write to the Free Software Foundation, Inc.,
    2435
    +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
    2436
    +//
    2437
    +// As a special exception, if other files instantiate templates or use macros
    2438
    +// or inline functions from this file, or you compile this file and link it
    2439
    +// with other works to produce a work based on this file, this file does not
    2440
    +// by itself cause the resulting work to be covered by the GNU General Public
    2441
    +// License. However the source code for this file must still be made available
    2442
    +// in accordance with section (3) of the GNU General Public License.
    2443
    +//
    2444
    +// This exception does not invalidate any other reasons why a work based on
    2445
    +// this file might be covered by the GNU General Public License.
    2446
    +//
    2447
    +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
    2448
    +// at http://sources.redhat.com/ecos/ecos-license/
    2449
    +// -------------------------------------------
    2450
    +//####ECOSGPLCOPYRIGHTEND####
    2451
    +//==========================================================================
    2452
    +//#####DESCRIPTIONBEGIN####
    2453
    +//
    2454
    +// Author(s):    sfurman
    2455
    +// Contributors: Damjan Lambert
    2456
    +// Date:         2003-01-17
    2457
    +// Purpose:      Define OpenRISC architecture special-purpose registers
    2458
    +// Usage:        #include 
    2459
    +//
    2460
    +//####DESCRIPTIONEND####
    2461
    +//
    2462
    +//==========================================================================
    2463
    +
    2464
    +/* Definition of special-purpose registers (SPRs) */
    2465
    +
    2466
    +#ifndef _ASM_SPR_DEFS_H
    2467
    +#define _ASM_SPR_DEFS_H
    2468
    +
    2469
    +#define MAX_GRPS (32)
    2470
    +#define MAX_SPRS_PER_GRP_BITS (11)
    2471
    +#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS)
    2472
    +#define MAX_SPRS (0x10000)
    2473
    +
    2474
    +/* Base addresses for the groups */
    2475
    +#define SPRGROUP_SYS    (0<< MAX_SPRS_PER_GRP_BITS)
    2476
    +#define SPRGROUP_DMMU   (1<< MAX_SPRS_PER_GRP_BITS)
    2477
    +#define SPRGROUP_IMMU   (2<< MAX_SPRS_PER_GRP_BITS)
    2478
    +#define SPRGROUP_DC     (3<< MAX_SPRS_PER_GRP_BITS)
    2479
    +#define SPRGROUP_IC     (4<< MAX_SPRS_PER_GRP_BITS)
    2480
    +#define SPRGROUP_MAC    (5<< MAX_SPRS_PER_GRP_BITS)
    2481
    +#define SPRGROUP_D      (6<< MAX_SPRS_PER_GRP_BITS)
    2482
    +#define SPRGROUP_PC     (7<< MAX_SPRS_PER_GRP_BITS)
    2483
    +#define SPRGROUP_PM     (8<< MAX_SPRS_PER_GRP_BITS)
    2484
    +#define SPRGROUP_PIC    (9<< MAX_SPRS_PER_GRP_BITS)
    2485
    +#define SPRGROUP_TT     (10<< MAX_SPRS_PER_GRP_BITS)
    2486
    +
    2487
    +/* System control and status group */
    2488
    +#define SPR_VR          (SPRGROUP_SYS + 0)
    2489
    +#define SPR_UPR         (SPRGROUP_SYS + 1)
    2490
    +#define SPR_PC          (SPRGROUP_SYS + 16)  /* CZ 21/06/01 */
    2491
    +#define SPR_SR          (SPRGROUP_SYS + 17)  /* CZ 21/06/01 */
    2492
    +#define SPR_EPCR_BASE   (SPRGROUP_SYS + 32)  /* CZ 21/06/01 */
    2493
    +#define SPR_EPCR_LAST   (SPRGROUP_SYS + 47)  /* CZ 21/06/01 */
    2494
    +#define SPR_EEAR_BASE   (SPRGROUP_SYS + 48)
    2495
    +#define SPR_EEAR_LAST   (SPRGROUP_SYS + 63)
    2496
    +#define SPR_ESR_BASE    (SPRGROUP_SYS + 64)
    2497
    +#define SPR_ESR_LAST    (SPRGROUP_SYS + 79)
    2498
    +
    2499
    +#if 0
    2500
    +/* Data MMU group */
    2501
    +#define SPR_DMMUCR      (SPRGROUP_DMMU + 0)
    2502
    +#define SPR_DTLBMR_BASE(WAY)    (SPRGROUP_DMMU + 0x200 + (WAY) * 0x200)
    2503
    +#define SPR_DTLBMR_LAST(WAY)    (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x200)
    2504
    +#define SPR_DTLBTR_BASE(WAY)    (SPRGROUP_DMMU + 0x300 + (WAY) * 0x200)
    2505
    +#define SPR_DTLBTR_LAST(WAY)    (SPRGROUP_DMMU + 0x3ff + (WAY) * 0x200)
    2506
    +
    2507
    +/* Instruction MMU group */
    2508
    +#define SPR_IMMUCR      (SPRGROUP_IMMU + 0)
    2509
    +#define SPR_ITLBMR_BASE(WAY)    (SPRGROUP_IMMU + 0x200 + (WAY) * 0x200)
    2510
    +#define SPR_ITLBMR_LAST(WAY)    (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x200)
    2511
    +#define SPR_ITLBTR_BASE(WAY)    (SPRGROUP_IMMU + 0x300 + (WAY) * 0x200)
    2512
    +#define SPR_ITLBTR_LAST(WAY)    (SPRGROUP_IMMU + 0x3ff + (WAY) * 0x200)
    2513
    +#else
    2514
    +/* Data MMU group */
    2515
    +#define SPR_DMMUCR      (SPRGROUP_DMMU + 0)
    2516
    +#define SPR_DTLBMR_BASE(WAY)    (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
    2517
    +#define SPR_DTLBMR_LAST(WAY)    (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
    2518
    +#define SPR_DTLBTR_BASE(WAY)    (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
    2519
    +#define SPR_DTLBTR_LAST(WAY)    (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)
    2520
    +
    2521
    +/* Instruction MMU group */
    2522
    +#define SPR_IMMUCR      (SPRGROUP_IMMU + 0)
    2523
    +#define SPR_ITLBMR_BASE(WAY)    (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)
    2524
    +#define SPR_ITLBMR_LAST(WAY)    (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100)
    2525
    +#define SPR_ITLBTR_BASE(WAY)    (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100)
    2526
    +#define SPR_ITLBTR_LAST(WAY)    (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100)
    2527
    +#endif
    2528
    +
    2529
    +/* Data cache group */
    2530
    +#define SPR_DCCR        (SPRGROUP_DC + 0)
    2531
    +#define SPR_DCBPR       (SPRGROUP_DC + 1)
    2532
    +#define SPR_DCBFR       (SPRGROUP_DC + 2)
    2533
    +#define SPR_DCBIR       (SPRGROUP_DC + 3)
    2534
    +#define SPR_DCBWR       (SPRGROUP_DC + 4)
    2535
    +#define SPR_DCBLR       (SPRGROUP_DC + 5)
    2536
    +#define SPR_DCR_BASE(WAY)       (SPRGROUP_DC + 0x200 + (WAY) * 0x200)
    2537
    +#define SPR_DCR_LAST(WAY)       (SPRGROUP_DC + 0x3ff + (WAY) * 0x200)
    2538
    +
    2539
    +/* Instruction cache group */
    2540
    +#define SPR_ICCR        (SPRGROUP_IC + 0)
    2541
    +#define SPR_ICBPR       (SPRGROUP_IC + 1)
    2542
    +#define SPR_ICBIR       (SPRGROUP_IC + 2)
    2543
    +#define SPR_ICBLR       (SPRGROUP_IC + 3)
    2544
    +#define SPR_ICR_BASE(WAY)       (SPRGROUP_IC + 0x200 + (WAY) * 0x200)
    2545
    +#define SPR_ICR_LAST(WAY)       (SPRGROUP_IC + 0x3ff + (WAY) * 0x200)
    2546
    +
    2547
    +/* MAC group */
    2548
    +#define SPR_MACLO       (SPRGROUP_MAC + 1)
    2549
    +#define SPR_MACHI       (SPRGROUP_MAC + 2)
    2550
    +
    2551
    +/* Debug group */
    2552
    +#define SPR_DVR(N)      (SPRGROUP_D + (N))
    2553
    +#define SPR_DCR(N)      (SPRGROUP_D + 8 + (N))
    2554
    +#define SPR_DMR1        (SPRGROUP_D + 16)
    2555
    +#define SPR_DMR2        (SPRGROUP_D + 17)
    2556
    +#define SPR_DWCR0       (SPRGROUP_D + 18)
    2557
    +#define SPR_DWCR1       (SPRGROUP_D + 19)
    2558
    +#define SPR_DSR         (SPRGROUP_D + 20)
    2559
    +#define SPR_DRR         (SPRGROUP_D + 21)
    2560
    +#define SPR_DIR         (SPRGROUP_D + 22)
    2561
    +
    2562
    +/* Performance counters group */
    2563
    +#define SPR_PCCR(N)     (SPRGROUP_PC + (N))
    2564
    +#define SPR_PCMR(N)     (SPRGROUP_PC + 8 + (N))
    2565
    +
    2566
    +/* Power management group */
    2567
    +#define SPR_PMR (SPRGROUP_PM + 0)
    2568
    +
    2569
    +/* PIC group */
    2570
    +#define SPR_PICMR (SPRGROUP_PIC + 0)
    2571
    +#define SPR_PICPR (SPRGROUP_PIC + 1)
    2572
    +#define SPR_PICSR (SPRGROUP_PIC + 2)
    2573
    +
    2574
    +/* Tick Timer group */
    2575
    +#define SPR_TTMR (SPRGROUP_TT + 0)
    2576
    +#define SPR_TTCR (SPRGROUP_TT + 1)
    2577
    +
    2578
    +/*
    2579
    + * Bit definitions for the Version Register
    2580
    + *
    2581
    + */
    2582
    +#define SPR_VR_VER      0xffff0000  /* Processor version */
    2583
    +#define SPR_VR_REV      0x0000003f  /* Processor revision */
    2584
    +
    2585
    +/*
    2586
    + * Bit definitions for the Unit Present Register
    2587
    + *
    2588
    + */
    2589
    +#define SPR_UPR_UP      0x00000001  /* UPR present */
    2590
    +#define SPR_UPR_DCP     0x00000002  /* Data cache present */
    2591
    +#define SPR_UPR_ICP     0x00000004  /* Instruction cache present */
    2592
    +#define SPR_UPR_DMP     0x00000008  /* Data MMU present */
    2593
    +#define SPR_UPR_IMP     0x00000010  /* Instruction MMU present */
    2594
    +#define SPR_UPR_OB32P   0x00000020  /* ORBIS32 present */
    2595
    +#define SPR_UPR_OB64P   0x00000040  /* ORBIS64 present */
    2596
    +#define SPR_UPR_OF32P   0x00000080  /* ORFPX32 present */
    2597
    +#define SPR_UPR_OF64P   0x00000100  /* ORFPX64 present */
    2598
    +#define SPR_UPR_OV32P   0x00000200  /* ORVDX32 present */
    2599
    +#define SPR_UPR_OV64P   0x00000400  /* ORVDX64 present */
    2600
    +#define SPR_UPR_DUP     0x00000800  /* Debug unit present */
    2601
    +#define SPR_UPR_PCUP    0x00001000  /* Performance counters unit present */
    2602
    +#define SPR_UPR_PMP     0x00002000  /* Power management present */
    2603
    +#define SPR_UPR_PICP    0x00004000  /* PIC present */
    2604
    +#define SPR_UPR_TTP     0x00008000  /* Tick timer present */
    2605
    +#define SPR_UPR_SRP     0x00010000  /* Shadow registers present */
    2606
    +#define SPR_UPR_RES     0x00fe0000  /* ORVDX32 present */
    2607
    +#define SPR_UPR_CUST    0xff000000  /* Custom units */
    2608
    +
    2609
    +/*
    2610
    + * Bit definitions for the Supervision Register
    2611
    + *
    2612
    + */
    2613
    +#define SPR_SR_CID      0xf0000000  /* Context ID */
    2614
    +#define SPR_SR_FO       0x00008000  /* Fixed one */
    2615
    +#define SPR_SR_EPH      0x00004000  /* Exception Prefixi High */
    2616
    +#define SPR_SR_DSX      0x00002000  /* Delay Slot Exception */
    2617
    +#define SPR_SR_OVE      0x00001000  /* Overflow flag Exception */
    2618
    +#define SPR_SR_OV       0x00000800  /* Overflow flag */
    2619
    +#define SPR_SR_CY       0x00000400  /* Carry flag */
    2620
    +#define SPR_SR_F        0x00000200  /* Condition Flag */
    2621
    +#define SPR_SR_CE       0x00000100  /* CID Enable */
    2622
    +#define SPR_SR_LEE      0x00000080  /* Little Endian Enable */
    2623
    +#define SPR_SR_IME      0x00000040  /* Instruction MMU Enable */
    2624
    +#define SPR_SR_DME      0x00000020  /* Data MMU Enable */
    2625
    +#define SPR_SR_ICE      0x00000010  /* Instruction Cache Enable */
    2626
    +#define SPR_SR_DCE      0x00000008  /* Data Cache Enable */
    2627
    +#define SPR_SR_IEE      0x00000004  /* Interrupt Exception Enable */
    2628
    +#define SPR_SR_TEE      0x00000002  /* Tick timer Exception Enable */
    2629
    +#define SPR_SR_SM       0x00000001  /* Supervisor Mode */
    2630
    +#define SPR_SR_FO_BIT    15
    2631
    +#define SPR_SR_EPH_BIT   14
    2632
    +#define SPR_SR_DSX_BIT   13
    2633
    +#define SPR_SR_OVE_BIT   12
    2634
    +#define SPR_SR_OV_BIT    11
    2635
    +#define SPR_SR_CY_BIT    10
    2636
    +#define SPR_SR_F_BIT     9
    2637
    +#define SPR_SR_CE_BIT    8
    2638
    +#define SPR_SR_LEE_BIT   7
    2639
    +#define SPR_SR_IME_BIT   6
    2640
    +#define SPR_SR_DME_BIT   5
    2641
    +#define SPR_SR_ICE_BIT   4
    2642
    +#define SPR_SR_DCE_BIT   3
    2643
    +#define SPR_SR_IEE_BIT   2
    2644
    +#define SPR_SR_TEE_BIT   1
    2645
    +#define SPR_SR_SM_BIT    0
    2646
    +
    2647
    +
    2648
    +/*
    2649
    + * Bit definitions for the Data MMU Control Register
    2650
    + *
    2651
    + */
    2652
    +#define SPR_DMMUCR_P2S  0x0000003e  /* Level 2 Page Size */
    2653
    +#define SPR_DMMUCR_P1S  0x000007c0  /* Level 1 Page Size */
    2654
    +#define SPR_DMMUCR_VADDR_WIDTH  0x0000f800  /* Virtual ADDR Width */
    2655
    +#define SPR_DMMUCR_PADDR_WIDTH  0x000f0000  /* Physical ADDR Width */
    2656
    +
    2657
    +/*
    2658
    + * Bit definitions for the Instruction MMU Control Register
    2659
    + *
    2660
    + */
    2661
    +#define SPR_IMMUCR_P2S  0x0000003e  /* Level 2 Page Size */
    2662
    +#define SPR_IMMUCR_P1S  0x000007c0  /* Level 1 Page Size */
    2663
    +#define SPR_IMMUCR_VADDR_WIDTH  0x0000f800  /* Virtual ADDR Width */
    2664
    +#define SPR_IMMUCR_PADDR_WIDTH  0x000f0000  /* Physical ADDR Width */
    2665
    +
    2666
    +/*
    2667
    + * Bit definitions for the Data TLB Match Register
    2668
    + *
    2669
    + */
    2670
    +#define SPR_DTLBMR_V    0x00000001  /* Valid */
    2671
    +#define SPR_DTLBMR_PL1  0x00000002  /* Page Level 1 (if 0 then PL2) */
    2672
    +#define SPR_DTLBMR_CID  0x0000003c  /* Context ID */
    2673
    +#define SPR_DTLBMR_LRU  0x000000c0  /* Least Recently Used */
    2674
    +#define SPR_DTLBMR_VPN  0xfffff000  /* Virtual Page Number */
    2675
    +
    2676
    +/*
    2677
    + * Bit definitions for the Data TLB Translate Register
    2678
    + *
    2679
    + */
    2680
    +#define SPR_DTLBTR_CC   0x00000001  /* Cache Coherency */
    2681
    +#define SPR_DTLBTR_CI   0x00000002  /* Cache Inhibit */
    2682
    +#define SPR_DTLBTR_WBC  0x00000004  /* Write-Back Cache */
    2683
    +#define SPR_DTLBTR_WOM  0x00000008  /* Weakly-Ordered Memory */
    2684
    +#define SPR_DTLBTR_A    0x00000010  /* Accessed */
    2685
    +#define SPR_DTLBTR_D    0x00000020  /* Dirty */
    2686
    +#define SPR_DTLBTR_URE  0x00000040  /* User Read Enable */
    2687
    +#define SPR_DTLBTR_UWE  0x00000080  /* User Write Enable */
    2688
    +#define SPR_DTLBTR_SRE  0x00000100  /* Supervisor Read Enable */
    2689
    +#define SPR_DTLBTR_SWE  0x00000200  /* Supervisor Write Enable */
    2690
    +#define SPR_DTLBTR_PPN  0xfffff000  /* Physical Page Number */
    2691
    +#define DTLBTR_NO_LIMIT ( SPR_DTLBTR_URE |  \
    2692
    +                          SPR_DTLBTR_UWE |  \
    2693
    +                          SPR_DTLBTR_SRE |  \
    2694
    +                          SPR_DTLBTR_SWE )
    2695
    +
    2696
    +/*
    2697
    + * Bit definitions for the Instruction TLB Match Register
    2698
    + *
    2699
    + */
    2700
    +#define SPR_ITLBMR_V    0x00000001  /* Valid */
    2701
    +#define SPR_ITLBMR_PL1  0x00000002  /* Page Level 1 (if 0 then PL2) */
    2702
    +#define SPR_ITLBMR_CID  0x0000003c  /* Context ID */
    2703
    +#define SPR_ITLBMR_LRU  0x000000c0  /* Least Recently Used */
    2704
    +#define SPR_ITLBMR_VPN  0xfffff000  /* Virtual Page Number */
    2705
    +
    2706
    +/*
    2707
    + * Bit definitions for the Instruction TLB Translate Register
    2708
    + *
    2709
    + */
    2710
    +#define SPR_ITLBTR_CC   0x00000001  /* Cache Coherency */
    2711
    +#define SPR_ITLBTR_CI   0x00000002  /* Cache Inhibit */
    2712
    +#define SPR_ITLBTR_WBC  0x00000004  /* Write-Back Cache */
    2713
    +#define SPR_ITLBTR_WOM  0x00000008  /* Weakly-Ordered Memory */
    2714
    +#define SPR_ITLBTR_A    0x00000010  /* Accessed */
    2715
    +#define SPR_ITLBTR_D    0x00000020  /* Dirty */
    2716
    +#define SPR_ITLBTR_SXE  0x00000040  /* User Read Enable */
    2717
    +#define SPR_ITLBTR_UXE  0x00000080  /* User Write Enable */
    2718
    +#define SPR_ITLBTR_PPN  0xfffff000  /* Physical Page Number */
    2719
    +#define ITLBTR_NO_LIMIT (SPR_ITLBTR_SXE | SPR_ITLBTR_UXE)
    2720
    +
    2721
    +/*
    2722
    + * Bit definitions for Data Cache Control register
    2723
    + *
    2724
    + */
    2725
    +#define SPR_DCCR_EW     0x000000ff  /* Enable ways */
    2726
    +
    2727
    +/*
    2728
    + * Bit definitions for Insn Cache Control register
    2729
    + *
    2730
    + */
    2731
    +#define SPR_ICCR_EW     0x000000ff  /* Enable ways */
    2732
    +
    2733
    +/*
    2734
    + * Bit definitions for Debug Control registers
    2735
    + *
    2736
    + */
    2737
    +#define SPR_DCR_DP      0x00000001  /* DVR/DCR present */
    2738
    +#define SPR_DCR_CC      0x0000000e  /* Compare condition */
    2739
    +#define SPR_DCR_SC      0x00000010  /* Signed compare */
    2740
    +#define SPR_DCR_CT      0x000000e0  /* Compare to */
    2741
    +
    2742
    +/*
    2743
    + * Bit definitions for Debug Mode 1 register
    2744
    + *
    2745
    + */
    2746
    +#define SPR_DMR1_CW0    0x00000003  /* Chain watchpoint 0 */
    2747
    +#define SPR_DMR1_CW1    0x0000000c  /* Chain watchpoint 1 */
    2748
    +#define SPR_DMR1_CW2    0x00000030  /* Chain watchpoint 2 */
    2749
    +#define SPR_DMR1_CW3    0x000000c0  /* Chain watchpoint 3 */
    2750
    +#define SPR_DMR1_CW4    0x00000300  /* Chain watchpoint 4 */
    2751
    +#define SPR_DMR1_CW5    0x00000c00  /* Chain watchpoint 5 */
    2752
    +#define SPR_DMR1_CW6    0x00003000  /* Chain watchpoint 6 */
    2753
    +#define SPR_DMR1_CW7    0x0000c000  /* Chain watchpoint 7 */
    2754
    +#define SPR_DMR1_CW8    0x00030000  /* Chain watchpoint 8 */
    2755
    +#define SPR_DMR1_CW9    0x000c0000  /* Chain watchpoint 9 */
    2756
    +#define SPR_DMR1_CW10   0x00300000  /* Chain watchpoint 10 */
    2757
    +#define SPR_DMR1_ST     0x00400000  /* Single-step trace*/
    2758
    +#define SPR_DMR1_BT     0x00800000  /* Branch trace */
    2759
    +#define SPR_DMR1_DXFW   0x01000000  /* Disable external force watchpoint */
    2760
    +
    2761
    +/*
    2762
    + * Bit definitions for Debug Mode 2 register
    2763
    + *
    2764
    + */
    2765
    +#define SPR_DMR2_WCE0   0x00000001  /* Watchpoint counter 0 enable */
    2766
    +#define SPR_DMR2_WCE1   0x00000002  /* Watchpoint counter 0 enable */
    2767
    +#define SPR_DMR2_AWTC   0x00001ffc  /* Assign watchpoints to counters */
    2768
    +#define SPR_DMR2_WGB    0x00ffe000  /* Watchpoints generating breakpoint */
    2769
    +
    2770
    +/*
    2771
    + * Bit definitions for Debug watchpoint counter registers
    2772
    + *
    2773
    + */
    2774
    +#define SPR_DWCR_COUNT  0x0000ffff  /* Count */
    2775
    +#define SPR_DWCR_MATCH  0xffff0000  /* Match */
    2776
    +
    2777
    +/*
    2778
    + * Bit definitions for Debug stop register
    2779
    + *
    2780
    + */
    2781
    +#define SPR_DSR_RSTE    0x00000001  /* Reset exception */
    2782
    +#define SPR_DSR_BUSEE   0x00000002  /* Bus error exception */
    2783
    +#define SPR_DSR_DPFE    0x00000004  /* Data Page Fault exception */
    2784
    +#define SPR_DSR_IPFE    0x00000008  /* Insn Page Fault exception */
    2785
    +#define SPR_DSR_LPINTE  0x00000010  /* Low priority interrupt exception */
    2786
    +#define SPR_DSR_AE      0x00000020  /* Alignment exception */
    2787
    +#define SPR_DSR_IIE     0x00000040  /* Illegal Instruction exception */
    2788
    +#define SPR_DSR_HPINTE  0x00000080  /* High priority interrupt exception */
    2789
    +#define SPR_DSR_DME     0x00000100  /* DTLB miss exception */
    2790
    +#define SPR_DSR_IME     0x00000200  /* ITLB miss exception */
    2791
    +#define SPR_DSR_RE      0x00000400  /* Range exception */
    2792
    +#define SPR_DSR_SCE     0x00000800  /* System call exception */
    2793
    +#define SPR_DSR_BE      0x00001000  /* Breakpoint exception */
    2794
    +
    2795
    +/*
    2796
    + * Bit definitions for Debug reason register
    2797
    + *
    2798
    + */
    2799
    +#define SPR_DRR_RSTE    0x00000001  /* Reset exception */
    2800
    +#define SPR_DRR_BUSEE   0x00000002  /* Bus error exception */
    2801
    +#define SPR_DRR_DPFE    0x00000004  /* Data Page Fault exception */
    2802
    +#define SPR_DRR_IPFE    0x00000008  /* Insn Page Fault exception */
    2803
    +#define SPR_DRR_LPINTE  0x00000010  /* Low priority interrupt exception */
    2804
    +#define SPR_DRR_AE      0x00000020  /* Alignment exception */
    2805
    +#define SPR_DRR_IIE     0x00000040  /* Illegal Instruction exception */
    2806
    +#define SPR_DRR_HPINTE  0x00000080  /* High priority interrupt exception */
    2807
    +#define SPR_DRR_DME     0x00000100  /* DTLB miss exception */
    2808
    +#define SPR_DRR_IME     0x00000200  /* ITLB miss exception */
    2809
    +#define SPR_DRR_RE      0x00000400  /* Range exception */
    2810
    +#define SPR_DRR_SCE     0x00000800  /* System call exception */
    2811
    +#define SPR_DRR_BE      0x00001000  /* Breakpoint exception */
    2812
    +
    2813
    +/*
    2814
    + * Bit definitions for Performance counters mode registers
    2815
    + *
    2816
    + */
    2817
    +#define SPR_PCMR_CP     0x00000001  /* Counter present */
    2818
    +#define SPR_PCMR_UMRA   0x00000002  /* User mode read access */
    2819
    +#define SPR_PCMR_CISM   0x00000004  /* Count in supervisor mode */
    2820
    +#define SPR_PCMR_CIUM   0x00000008  /* Count in user mode */
    2821
    +#define SPR_PCMR_LA     0x00000010  /* Load access event */
    2822
    +#define SPR_PCMR_SA     0x00000020  /* Store access event */
    2823
    +#define SPR_PCMR_IF     0x00000040  /* Instruction fetch event*/
    2824
    +#define SPR_PCMR_DCM    0x00000080  /* Data cache miss event */
    2825
    +#define SPR_PCMR_ICM    0x00000100  /* Insn cache miss event */
    2826
    +#define SPR_PCMR_IFS    0x00000200  /* Insn fetch stall event */
    2827
    +#define SPR_PCMR_LSUS   0x00000400  /* LSU stall event */
    2828
    +#define SPR_PCMR_BS     0x00000800  /* Branch stall event */
    2829
    +#define SPR_PCMR_DTLBM  0x00001000  /* DTLB miss event */
    2830
    +#define SPR_PCMR_ITLBM  0x00002000  /* ITLB miss event */
    2831
    +#define SPR_PCMR_DDS    0x00004000  /* Data dependency stall event */
    2832
    +#define SPR_PCMR_WPE    0x03ff8000  /* Watchpoint events */
    2833
    +
    2834
    +/*
    2835
    + * Bit definitions for the Power management register
    2836
    + *
    2837
    + */
    2838
    +#define SPR_PMR_SDF     0x00000001  /* Slow down factor */
    2839
    +#define SPR_PMR_DME     0x00000002  /* Doze mode enable */
    2840
    +#define SPR_PMR_SME     0x00000004  /* Sleep mode enable */
    2841
    +#define SPR_PMR_DCGE    0x00000008  /* Dynamic clock gating enable */
    2842
    +#define SPR_PMR_SUME    0x00000010  /* Suspend mode enable */
    2843
    +
    2844
    +/*
    2845
    + * Bit definitions for PICMR
    2846
    + *
    2847
    + */
    2848
    +#define SPR_PICMR_IUM   0xfffffffc  /* Interrupt unmask */
    2849
    +
    2850
    +/*
    2851
    + * Bit definitions for PICPR
    2852
    + *
    2853
    + */
    2854
    +#define SPR_PICPR_IPRIO 0xfffffffc  /* Interrupt priority */
    2855
    +
    2856
    +/*
    2857
    + * Bit definitions for PICSR
    2858
    + *
    2859
    + */
    2860
    +#define SPR_PICSR_IS    0xffffffff  /* Interrupt status */
    2861
    +
    2862
    +/*
    2863
    + * Bit definitions for Tick Timer Control Register
    2864
    + *
    2865
    + */
    2866
    +#define SPR_TTCR_PERIOD 0x0fffffff  /* Time Period */
    2867
    +#define SPR_TTMR_PERIOD SPR_TTCR_PERIOD
    2868
    +#define SPR_TTMR_IP 0x10000000  /* Interrupt Pending */
    2869
    +#define SPR_TTMR_IE 0x20000000  /* Interrupt Enable */
    2870
    +#define SPR_TTMR_RT 0x40000000  /* Restart tick */
    2871
    +#define SPR_TTMR_SR     0x80000000  /* Single run */
    2872
    +#define SPR_TTMR_CR     0xc0000000  /* Continuous run */
    2873
    +#define SPR_TTMR_M      0xc0000000  /* Tick mode */
    2874
    +
    2875
    +#endif
    2876
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/src/context.S ./ecos-3.0/packages/hal/openrisc/arch/v3_0/src/context.S
    2877
    --- /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/src/context.S 1969-12-31 16:00:00.000000000 -0800
    2878
    +++ ./ecos-3.0/packages/hal/openrisc/arch/v3_0/src/context.S    2010-02-15 15:20:32.989490600 -0800
    2879
    @@ -0,0 +1,296 @@
    2880
    +##=============================================================================##
    2881
    +##      context.S
    2882
    +##
    2883
    +##      OpenRISC context switch code
    2884
    +##
    2885
    +##=============================================================================
    2886
    +#####ECOSGPLCOPYRIGHTBEGIN####
    2887
    +## -------------------------------------------
    2888
    +## This file is part of eCos, the Embedded Configurable Operating System.
    2889
    +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
    2890
    +##
    2891
    +## eCos is free software; you can redistribute it and/or modify it under
    2892
    +## the terms of the GNU General Public License as published by the Free
    2893
    +## Software Foundation; either version 2 or (at your option) any later version.
    2894
    +##
    2895
    +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
    2896
    +## WARRANTY; without even the implied warranty of MERCHANTABILITY or
    2897
    +## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    2898
    +## for more details.
    2899
    +##
    2900
    +## You should have received a copy of the GNU General Public License along
    2901
    +## with eCos; if not, write to the Free Software Foundation, Inc.,
    2902
    +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
    2903
    +##
    2904
    +## As a special exception, if other files instantiate templates or use macros
    2905
    +## or inline functions from this file, or you compile this file and link it
    2906
    +## with other works to produce a work based on this file, this file does not
    2907
    +## by itself cause the resulting work to be covered by the GNU General Public
    2908
    +## License. However the source code for this file must still be made available
    2909
    +## in accordance with section (3) of the GNU General Public License.
    2910
    +##
    2911
    +## This exception does not invalidate any other reasons why a work based on
    2912
    +## this file might be covered by the GNU General Public License.
    2913
    +##
    2914
    +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
    2915
    +## at http://sources.redhat.com/ecos/ecos-license/
    2916
    +## -------------------------------------------
    2917
    +#####ECOSGPLCOPYRIGHTEND####
    2918
    +##=============================================================================
    2919
    +#######DESCRIPTIONBEGIN####
    2920
    +##
    2921
    +## Author(s):   Scott Furman
    2922
    +## Contributors:
    2923
    +## Date:        2003-01-21
    2924
    +## Purpose:     OpenRISC context switch code
    2925
    +## Description: This file contains implementations of the thread context
    2926
    +##              switch routines. It also contains the longjmp() and setjmp()
    2927
    +##              routines.
    2928
    +##
    2929
    +######DESCRIPTIONEND####
    2930
    +##
    2931
    +##=============================================================================
    2932
    +
    2933
    +#include 
    2934
    +
    2935
    +#include 
    2936
    +#include 
    2937
    +
    2938
    +
    2939
    +
    2940
    +#------------------------------------------------------------------------------
    2941
    +# hal_thread_switch_context()
    2942
    +# Switch thread contexts
    2943
    +# R3 = address of sp of next thread to execute
    2944
    +# R4 = address of sp save location of current thread
    2945
    +
    2946
    +FUNC_START(hal_thread_switch_context)
    2947
    +        l.addi  sp,sp,-SIZEOF_OR1KREGS  # space for registers
    2948
    +
    2949
    +        # Store General Purpose Registers (GPRs).
    2950
    +        l.sw     2 * OR1K_GPRSIZE(sp), r2
    2951
    +        l.sw     9 * OR1K_GPRSIZE(sp), r9
    2952
    +        l.sw    10 * OR1K_GPRSIZE(sp), r10
    2953
    +        l.sw    12 * OR1K_GPRSIZE(sp), r12
    2954
    +        l.sw    14 * OR1K_GPRSIZE(sp), r14
    2955
    +        l.sw    16 * OR1K_GPRSIZE(sp), r16
    2956
    +        l.sw    18 * OR1K_GPRSIZE(sp), r18
    2957
    +        l.sw    20 * OR1K_GPRSIZE(sp), r20
    2958
    +        l.sw    22 * OR1K_GPRSIZE(sp), r22
    2959
    +        l.sw    24 * OR1K_GPRSIZE(sp), r24
    2960
    +        l.sw    26 * OR1K_GPRSIZE(sp), r26
    2961
    +        l.sw    28 * OR1K_GPRSIZE(sp), r28
    2962
    +        l.sw    30 * OR1K_GPRSIZE(sp), r30
    2963
    +
    2964
    +#ifndef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
    2965
    +
    2966
    +        # R0 is not typically stored because it is always zero-valued,
    2967
    +        # but we store it here for consistency when examining registers
    2968
    +        # in the debugger.
    2969
    +        l.sw     0 * OR1K_GPRSIZE(sp), r0
    2970
    +
    2971
    +        # Caller-saved regs don't need to be preserved across
    2972
    +        # context switches, but we do so to make debugging easier.
    2973
    +
    2974
    +        l.sw     3 * OR1K_GPRSIZE(sp), r3
    2975
    +        l.sw     4 * OR1K_GPRSIZE(sp), r4
    2976
    +        l.sw     5 * OR1K_GPRSIZE(sp), r5
    2977
    +        l.sw     6 * OR1K_GPRSIZE(sp), r6
    2978
    +        l.sw     7 * OR1K_GPRSIZE(sp), r7
    2979
    +        l.sw     8 * OR1K_GPRSIZE(sp), r8
    2980
    +        l.sw    11 * OR1K_GPRSIZE(sp), r11
    2981
    +        l.sw    13 * OR1K_GPRSIZE(sp), r13
    2982
    +        l.sw    15 * OR1K_GPRSIZE(sp), r15
    2983
    +        l.sw    17 * OR1K_GPRSIZE(sp), r17
    2984
    +        l.sw    19 * OR1K_GPRSIZE(sp), r19
    2985
    +        l.sw    21 * OR1K_GPRSIZE(sp), r21
    2986
    +        l.sw    23 * OR1K_GPRSIZE(sp), r23
    2987
    +        l.sw    25 * OR1K_GPRSIZE(sp), r25
    2988
    +        l.sw    27 * OR1K_GPRSIZE(sp), r27
    2989
    +        l.sw    29 * OR1K_GPRSIZE(sp), r29
    2990
    +        l.sw    31 * OR1K_GPRSIZE(sp), r31
    2991
    +
    2992
    +        # save MAC LO and HI regs
    2993
    +        l.mfspr r5,r0,SPR_MACLO
    2994
    +        l.sw    OR1KREG_MACLO(sp),r5
    2995
    +        l.mfspr r5,r0,SPR_MACHI
    2996
    +        l.sw    OR1KREG_MACHI(sp),r5
    2997
    +
    2998
    +#endif
    2999
    +
    3000
    +#ifdef CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
    3001
    +        # Make the thread context look like an exception context if thread-
    3002
    +        # aware debugging is required. This state does not need restoring.
    3003
    +        l.sw    OR1KREG_PC(sp),r9
    3004
    +#endif
    3005
    +
    3006
    +        l.addi  r5,sp,SIZEOF_OR1KREGS           # save SP in reg dump
    3007
    +        l.sw     1 * OR1K_GPRSIZE(sp), r5
    3008
    +
    3009
    +        l.mfspr  r5,r0,SPR_SR                   # save SR in reg dump
    3010
    +        l.sw     OR1KREG_SR(sp), r5
    3011
    +
    3012
    +        # Return resulting new SP to caller via second argument
    3013
    +        l.sw     0(r4), sp
    3014
    +
    3015
    +        # Now load the destination thread by dropping through
    3016
    +        # to hal_thread_load_context...
    3017
    +FUNC_END(hal_thread_switch_context)
    3018
    +
    3019
    +
    3020
    +#------------------------------------------------------------------------------
    3021
    +# hal_thread_load_context()
    3022
    +# Load thread context
    3023
    +# R3 = address of sp of next thread to execute
    3024
    +# Note that this function is also the second half of hal_thread_switch_context()
    3025
    +# and is simply dropped into from it.
    3026
    +
    3027
    +FUNC_START(hal_thread_load_context)
    3028
    +
    3029
    +        # Copy R3 to SP
    3030
    +        l.lwz   sp, 0(r3)
    3031
    +
    3032
    +        # Restore General Purpose Registers (GPRs).
    3033
    +        # R0 is not restored because it is always zero-valued.
    3034
    +        l.lwz   r2,   2 * OR1K_GPRSIZE(sp)
    3035
    +        l.lwz   r9,   9 * OR1K_GPRSIZE(sp)
    3036
    +        l.lwz   r10, 10 * OR1K_GPRSIZE(sp)
    3037
    +        l.lwz   r12, 12 * OR1K_GPRSIZE(sp)
    3038
    +        l.lwz   r14, 14 * OR1K_GPRSIZE(sp)
    3039
    +        l.lwz   r16, 16 * OR1K_GPRSIZE(sp)
    3040
    +        l.lwz   r18, 18 * OR1K_GPRSIZE(sp)
    3041
    +        l.lwz   r20, 20 * OR1K_GPRSIZE(sp)
    3042
    +        l.lwz   r22, 22 * OR1K_GPRSIZE(sp)
    3043
    +        l.lwz   r24, 24 * OR1K_GPRSIZE(sp)
    3044
    +        l.lwz   r26, 26 * OR1K_GPRSIZE(sp)
    3045
    +        l.lwz   r28, 28 * OR1K_GPRSIZE(sp)
    3046
    +        l.lwz   r30, 30 * OR1K_GPRSIZE(sp)
    3047
    +
    3048
    +        # Merge interrupt-enable state of new thread into
    3049
    +        # current SR
    3050
    +        load32i r5,~(SPR_SR_TEE|SPR_SR_IEE)
    3051
    +        l.mfspr r6, r0, SPR_SR
    3052
    +        l.and   r6, r5, r6
    3053
    +        l.lwz   r5,  OR1KREG_SR(sp)
    3054
    +        l.andi  r5, r5, (SPR_SR_TEE|SPR_SR_IEE)
    3055
    +        l.or    r5, r5, r6
    3056
    +        l.mtspr r0, r5, SPR_SR
    3057
    +
    3058
    +#ifndef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
    3059
    +
    3060
    +        # Caller-saved regs don't need to be preserved across
    3061
    +        # context switches, but we do so here to make debugging
    3062
    +        # easier.
    3063
    +
    3064
    +        # Restore MAC LO and HI regs
    3065
    +        l.lwz   r5, OR1KREG_MACLO(sp)
    3066
    +        l.mtspr r0,r5,SPR_MACLO
    3067
    +        l.lwz   r5, OR1KREG_MACHI(sp)
    3068
    +        l.mtspr r0,r5,SPR_MACHI
    3069
    +
    3070
    +        l.lwz    r4,  4 * OR1K_GPRSIZE(sp)
    3071
    +        l.lwz    r5,  5 * OR1K_GPRSIZE(sp)
    3072
    +        l.lwz    r6,  6 * OR1K_GPRSIZE(sp)
    3073
    +        l.lwz    r7,  7 * OR1K_GPRSIZE(sp)
    3074
    +        l.lwz    r8,  8 * OR1K_GPRSIZE(sp)
    3075
    +        l.lwz   r11, 11 * OR1K_GPRSIZE(sp)
    3076
    +        l.lwz   r13, 13 * OR1K_GPRSIZE(sp)
    3077
    +        l.lwz   r15, 15 * OR1K_GPRSIZE(sp)
    3078
    +        l.lwz   r17, 17 * OR1K_GPRSIZE(sp)
    3079
    +        l.lwz   r19, 19 * OR1K_GPRSIZE(sp)
    3080
    +        l.lwz   r21, 21 * OR1K_GPRSIZE(sp)
    3081
    +        l.lwz   r23, 23 * OR1K_GPRSIZE(sp)
    3082
    +        l.lwz   r25, 25 * OR1K_GPRSIZE(sp)
    3083
    +        l.lwz   r27, 27 * OR1K_GPRSIZE(sp)
    3084
    +        l.lwz   r29, 29 * OR1K_GPRSIZE(sp)
    3085
    +        l.lwz   r31, 31 * OR1K_GPRSIZE(sp)
    3086
    +
    3087
    +#endif
    3088
    +
    3089
    +       # If this is the first time we're running a thread, R3
    3090
    +       # contains the argument to the thread entry point function,
    3091
    +       # So we always have to restore it even though it's a callee-saved
    3092
    +       # register.
    3093
    +        l.lwz    r3,  3 * OR1K_GPRSIZE(sp)
    3094
    +
    3095
    +        # Finally, restore target thread's true SP
    3096
    +        l.lwz   sp,   1 * OR1K_GPRSIZE(sp)
    3097
    +
    3098
    +        l.jr    lr
    3099
    +        l.nop                                   # delay slot - must be nop
    3100
    +
    3101
    +FUNC_END(hal_thread_load_context)
    3102
    +
    3103
    +#------------------------------------------------------------------------------
    3104
    +# HAL longjmp, setjmp implementations
    3105
    +# hal_setjmp saves only callee-saved registers into buffer supplied in r3:
    3106
    +#       1,2,9,10,13,15,17,19,21,23,25,27,29,31
    3107
    +# Note: These definitions are repeated in hal_arch.h. If changes are required
    3108
    +# remember to update both sets.
    3109
    +
    3110
    +#define CYGARC_JMP_BUF_R1        0
    3111
    +#define CYGARC_JMP_BUF_R2        1
    3112
    +#define CYGARC_JMP_BUF_R9        2
    3113
    +#define CYGARC_JMP_BUF_R10       3
    3114
    +#define CYGARC_JMP_BUF_R12       4
    3115
    +#define CYGARC_JMP_BUF_R14       5
    3116
    +#define CYGARC_JMP_BUF_R16       6
    3117
    +#define CYGARC_JMP_BUF_R18       7
    3118
    +#define CYGARC_JMP_BUF_R20       8
    3119
    +#define CYGARC_JMP_BUF_R22       9
    3120
    +#define CYGARC_JMP_BUF_R24      10
    3121
    +#define CYGARC_JMP_BUF_R26      11
    3122
    +#define CYGARC_JMP_BUF_R28      12
    3123
    +#define CYGARC_JMP_BUF_R30      13
    3124
    +
    3125
    +#define CYGARC_JMP_BUF_SIZE     14
    3126
    +
    3127
    +#define jmpbuf_regsize 4
    3128
    +
    3129
    +FUNC_START(hal_setjmp)
    3130
    +        # Store General Purpose Registers (GPRs).
    3131
    +        # R0 is not stored because it is always zero-valued.
    3132
    +        # Caller-saved registers are not stored
    3133
    +        l.sw    CYGARC_JMP_BUF_R1  * OR1K_GPRSIZE(r3), r1
    3134
    +        l.sw    CYGARC_JMP_BUF_R2  * OR1K_GPRSIZE(r3), r2
    3135
    +        l.sw    CYGARC_JMP_BUF_R9  * OR1K_GPRSIZE(r3), r9
    3136
    +        l.sw    CYGARC_JMP_BUF_R10 * OR1K_GPRSIZE(r3), r10
    3137
    +        l.sw    CYGARC_JMP_BUF_R12 * OR1K_GPRSIZE(r3), r12
    3138
    +        l.sw    CYGARC_JMP_BUF_R14 * OR1K_GPRSIZE(r3), r14
    3139
    +        l.sw    CYGARC_JMP_BUF_R16 * OR1K_GPRSIZE(r3), r16
    3140
    +        l.sw    CYGARC_JMP_BUF_R18 * OR1K_GPRSIZE(r3), r18
    3141
    +        l.sw    CYGARC_JMP_BUF_R20 * OR1K_GPRSIZE(r3), r20
    3142
    +        l.sw    CYGARC_JMP_BUF_R22 * OR1K_GPRSIZE(r3), r22
    3143
    +        l.sw    CYGARC_JMP_BUF_R24 * OR1K_GPRSIZE(r3), r24
    3144
    +        l.sw    CYGARC_JMP_BUF_R26 * OR1K_GPRSIZE(r3), r26
    3145
    +        l.sw    CYGARC_JMP_BUF_R28 * OR1K_GPRSIZE(r3), r28
    3146
    +        l.sw    CYGARC_JMP_BUF_R30 * OR1K_GPRSIZE(r3), r30
    3147
    +        load32i rv, 0
    3148
    +        l.jr    lr
    3149
    +        l.nop                   # delay slot
    3150
    +FUNC_END(hal_setjmp)
    3151
    +
    3152
    +
    3153
    +FUNC_START(hal_longjmp)
    3154
    +        l.lwz    r1, CYGARC_JMP_BUF_R1  * OR1K_GPRSIZE(r3)
    3155
    +        l.lwz    r2, CYGARC_JMP_BUF_R2  * OR1K_GPRSIZE(r3)
    3156
    +        l.lwz    r9, CYGARC_JMP_BUF_R9  * OR1K_GPRSIZE(r3)
    3157
    +        l.lwz   r10, CYGARC_JMP_BUF_R10 * OR1K_GPRSIZE(r3)
    3158
    +        l.lwz   r12, CYGARC_JMP_BUF_R12 * OR1K_GPRSIZE(r3)
    3159
    +        l.lwz   r14, CYGARC_JMP_BUF_R14 * OR1K_GPRSIZE(r3)
    3160
    +        l.lwz   r16, CYGARC_JMP_BUF_R16 * OR1K_GPRSIZE(r3)
    3161
    +        l.lwz   r18, CYGARC_JMP_BUF_R18 * OR1K_GPRSIZE(r3)
    3162
    +        l.lwz   r20, CYGARC_JMP_BUF_R20 * OR1K_GPRSIZE(r3)
    3163
    +        l.lwz   r22, CYGARC_JMP_BUF_R22 * OR1K_GPRSIZE(r3)
    3164
    +        l.lwz   r24, CYGARC_JMP_BUF_R24 * OR1K_GPRSIZE(r3)
    3165
    +        l.lwz   r26, CYGARC_JMP_BUF_R26 * OR1K_GPRSIZE(r3)
    3166
    +        l.lwz   r28, CYGARC_JMP_BUF_R28 * OR1K_GPRSIZE(r3)
    3167
    +        l.lwz   r30, CYGARC_JMP_BUF_R30 * OR1K_GPRSIZE(r3)
    3168
    +
    3169
    +        l.jr    lr
    3170
    +        l.nop                   # delay slot
    3171
    +FUNC_END(hal_longjmp)
    3172
    +
    3173
    +
    3174
    +#------------------------------------------------------------------------------
    3175
    +# end of context.S
    3176
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/src/hal_misc.c ./ecos-3.0/packages/hal/openrisc/arch/v3_0/src/hal_misc.c
    3177
    --- /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/src/hal_misc.c        1969-12-31 16:00:00.000000000 -0800
    3178
    +++ ./ecos-3.0/packages/hal/openrisc/arch/v3_0/src/hal_misc.c   2009-09-16 14:06:26.000000000 -0700
    3179
    @@ -0,0 +1,283 @@
    3180
    +//==========================================================================
    3181
    +//
    3182
    +//      hal_misc.c
    3183
    +//
    3184
    +//      HAL miscellaneous functions
    3185
    +//
    3186
    +//==========================================================================
    3187
    +//####ECOSGPLCOPYRIGHTBEGIN####
    3188
    +// -------------------------------------------
    3189
    +// This file is part of eCos, the Embedded Configurable Operating System.
    3190
    +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
    3191
    +//
    3192
    +// eCos is free software; you can redistribute it and/or modify it under
    3193
    +// the terms of the GNU General Public License as published by the Free
    3194
    +// Software Foundation; either version 2 or (at your option) any later version.
    3195
    +//
    3196
    +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
    3197
    +// WARRANTY; without even the implied warranty of MERCHANTABILITY or
    3198
    +// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    3199
    +// for more details.
    3200
    +//
    3201
    +// You should have received a copy of the GNU General Public License along
    3202
    +// with eCos; if not, write to the Free Software Foundation, Inc.,
    3203
    +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
    3204
    +//
    3205
    +// As a special exception, if other files instantiate templates or use macros
    3206
    +// or inline functions from this file, or you compile this file and link it
    3207
    +// with other works to produce a work based on this file, this file does not
    3208
    +// by itself cause the resulting work to be covered by the GNU General Public
    3209
    +// License. However the source code for this file must still be made available
    3210
    +// in accordance with section (3) of the GNU General Public License.
    3211
    +//
    3212
    +// This exception does not invalidate any other reasons why a work based on
    3213
    +// this file might be covered by the GNU General Public License.
    3214
    +//
    3215
    +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
    3216
    +// at http://sources.redhat.com/ecos/ecos-license/
    3217
    +// -------------------------------------------
    3218
    +//####ECOSGPLCOPYRIGHTEND####
    3219
    +//==========================================================================
    3220
    +//#####DESCRIPTIONBEGIN####
    3221
    +//
    3222
    +// Author(s):    nickg
    3223
    +// Contributors: nickg, jlarmour
    3224
    +// Date:         1999-01-21
    3225
    +// Purpose:      HAL miscellaneous functions
    3226
    +// Description:  This file contains miscellaneous functions provided by the
    3227
    +//               HAL.
    3228
    +//
    3229
    +//####DESCRIPTIONEND####
    3230
    +//
    3231
    +//========================================================================*/
    3232
    +
    3233
    +#include 
    3234
    +
    3235
    +#include          // Base types
    3236
    +#include          // tracing macros
    3237
    +#include           // assertion macros
    3238
    +
    3239
    +#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
    3240
    +#include            // architectural definitions
    3241
    +#include            // Interrupt handling
    3242
    +#include              // hal_ctrlc_isr()
    3243
    +
    3244
    +#include CYGHWR_MEMORY_LAYOUT_H
    3245
    +
    3246
    +/*------------------------------------------------------------------------*/
    3247
    +/* If required, define a variable to store the clock period.              */
    3248
    +
    3249
    +#ifdef CYGHWR_HAL_CLOCK_PERIOD_DEFINED
    3250
    +
    3251
    +CYG_WORD32 cyg_hal_clock_period;
    3252
    +
    3253
    +#endif
    3254
    +
    3255
    +/*------------------------------------------------------------------------*/
    3256
    +/* First level C exception handler.                                       */
    3257
    +
    3258
    +externC void __handle_exception (void);
    3259
    +
    3260
    +externC HAL_SavedRegisters *_hal_registers;
    3261
    +
    3262
    +externC void* volatile __mem_fault_handler;
    3263
    +
    3264
    +externC cyg_uint8 cyg_hal_mips_process_fpe( HAL_SavedRegisters *regs );
    3265
    +
    3266
    +externC cyg_uint32 cyg_hal_exception_handler(HAL_SavedRegisters *regs)
    3267
    +{
    3268
    +#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
    3269
    +
    3270
    +    // If we caught an exception inside the stubs, see if we were expecting it
    3271
    +    // and if so jump to the saved address
    3272
    +    if (__mem_fault_handler) {
    3273
    +        regs->pc = (CYG_HAL_OPENRISC_REG)(signed long)__mem_fault_handler;
    3274
    +        return 0; // Caught an exception inside stubs
    3275
    +    }
    3276
    +
    3277
    +    // Set the pointer to the registers of the current exception
    3278
    +    // context. At entry the GDB stub will expand the
    3279
    +    // HAL_SavedRegisters structure into a (bigger) register array.
    3280
    +    _hal_registers = regs;
    3281
    +    __handle_exception();
    3282
    +
    3283
    +#elif defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && defined(CYGPKG_HAL_EXCEPTIONS)
    3284
    +
    3285
    +    // We should decode the vector and pass a more appropriate
    3286
    +    // value as the second argument. For now we simply pass a
    3287
    +    // pointer to the saved registers. We should also divert
    3288
    +    // breakpoint and other debug vectors into the debug stubs.
    3289
    +
    3290
    +    cyg_hal_deliver_exception( regs->vector, (CYG_ADDRWORD)regs );
    3291
    +
    3292
    +#else
    3293
    +
    3294
    +    CYG_FAIL("Exception!!!");
    3295
    +
    3296
    +#endif
    3297
    +    return 0;
    3298
    +}
    3299
    +
    3300
    +/*------------------------------------------------------------------------*/
    3301
    +/* default ISR                                                            */
    3302
    +
    3303
    +externC cyg_uint32
    3304
    +hal_arch_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data)
    3305
    +{
    3306
    +    return 0;
    3307
    +}
    3308
    +
    3309
    +/*------------------------------------------------------------------------*/
    3310
    +// Come here if interrupt triggered, but no apparent cause
    3311
    +void hal_spurious_IRQ(HAL_SavedRegisters *regs) CYGBLD_ATTRIB_WEAK;
    3312
    +void
    3313
    +hal_spurious_IRQ(HAL_SavedRegisters *regs)
    3314
    +{
    3315
    +#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
    3316
    +    cyg_hal_exception_handler(regs);
    3317
    +#else
    3318
    +    CYG_FAIL("Spurious interrupt!!");
    3319
    +#endif
    3320
    +}
    3321
    +/*------------------------------------------------------------------------*/
    3322
    +
    3323
    +#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG
    3324
    +cyg_bool cyg_hal_stop_constructors;
    3325
    +#endif
    3326
    +
    3327
    +typedef void (*pfunc) (void);
    3328
    +extern pfunc __CTOR_LIST__[];
    3329
    +extern pfunc __CTOR_END__[];
    3330
    +
    3331
    +void
    3332
    +cyg_hal_invoke_constructors(void)
    3333
    +{
    3334
    +#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG
    3335
    +    static pfunc *p = &__CTOR_END__[-1];
    3336
    +
    3337
    +    cyg_hal_stop_constructors = 0;
    3338
    +    for (; p >= __CTOR_LIST__; p--) {
    3339
    +        (*p) ();
    3340
    +        if (cyg_hal_stop_constructors) {
    3341
    +            p--;
    3342
    +            break;
    3343
    +        }
    3344
    +    }
    3345
    +#else
    3346
    +    pfunc *p;
    3347
    +
    3348
    +    for (p = &__CTOR_END__[-1]; p >= __CTOR_LIST__; p--)
    3349
    +        (*p) ();
    3350
    +#endif
    3351
    +
    3352
    +} // cyg_hal_invoke_constructors()
    3353
    +
    3354
    +/*------------------------------------------------------------------------*/
    3355
    +/* Determine the index of the ls bit of the supplied mask.                */
    3356
    +
    3357
    +cyg_uint32 hal_lsbit_index(cyg_uint32 mask)
    3358
    +{
    3359
    +    cyg_uint32 n = mask;
    3360
    +
    3361
    +    static const signed char tab[64] =
    3362
    +    { -1, 0, 1, 12, 2, 6, 0, 13, 3, 0, 7, 0, 0, 0, 0, 14, 10,
    3363
    +      4, 0, 0, 8, 0, 0, 25, 0, 0, 0, 0, 0, 21, 27 , 15, 31, 11,
    3364
    +      5, 0, 0, 0, 0, 0, 9, 0, 0, 24, 0, 0 , 20, 26, 30, 0, 0, 0,
    3365
    +      0, 23, 0, 19, 29, 0, 22, 18, 28, 17, 16, 0
    3366
    +    };
    3367
    +
    3368
    +    n &= ~(n-1UL);
    3369
    +    n = (n<<16)-n;
    3370
    +    n = (n<<6)+n;
    3371
    +    n = (n<<4)+n;
    3372
    +
    3373
    +    return tab[n>>26];
    3374
    +}
    3375
    +
    3376
    +/*------------------------------------------------------------------------*/
    3377
    +/* Determine the index of the ms bit of the supplied mask.                */
    3378
    +
    3379
    +cyg_uint32 hal_msbit_index(cyg_uint32 mask)
    3380
    +{
    3381
    +    cyg_uint32 x = mask;
    3382
    +    cyg_uint32 w;
    3383
    +
    3384
    +    /* Phase 1: make word with all ones from that one to the right */
    3385
    +    x |= x >> 16;
    3386
    +    x |= x >> 8;
    3387
    +    x |= x >> 4;
    3388
    +    x |= x >> 2;
    3389
    +    x |= x >> 1;
    3390
    +
    3391
    +    /* Phase 2: calculate number of "1" bits in the word        */
    3392
    +    w = (x & 0x55555555) + ((x >> 1) & 0x55555555);
    3393
    +    w = (w & 0x33333333) + ((w >> 2) & 0x33333333);
    3394
    +    w = w + (w >> 4);
    3395
    +    w = (w & 0x000F000F) + ((w >> 8) & 0x000F000F);
    3396
    +    return (cyg_uint32)((w + (w >> 16)) & 0xFF) - 1;
    3397
    +
    3398
    +}
    3399
    +
    3400
    +/*------------------------------------------------------------------------*/
    3401
    +/* Delay for some number of useconds.                                     */
    3402
    +void
    3403
    +hal_delay_us(int us)
    3404
    +{
    3405
    +    cyg_uint32 val1, val2;
    3406
    +    int diff;
    3407
    +    long usticks;
    3408
    +    long ticks;
    3409
    +
    3410
    +    // Calculate the number of counter register ticks per microsecond.
    3411
    +
    3412
    +    usticks = (CYGNUM_HAL_RTC_PERIOD * CYGNUM_HAL_RTC_DENOMINATOR) / 1000000;
    3413
    +
    3414
    +    // Make sure that the value is not zero.
    3415
    +    if( usticks == 0 ) usticks = 1;
    3416
    +
    3417
    +    while( us > 0 )
    3418
    +    {
    3419
    +        int us1 = us;
    3420
    +
    3421
    +        // Wait in bursts of less than 10000us to avoid any overflow
    3422
    +        // problems in the multiply.
    3423
    +        if( us1 > 10000 )
    3424
    +            us1 = 10000;
    3425
    +
    3426
    +        us -= us1;
    3427
    +
    3428
    +        ticks = us1 * usticks;
    3429
    +
    3430
    +        HAL_CLOCK_READ(&val1);
    3431
    +        while (ticks > 0) {
    3432
    +            do {
    3433
    +                HAL_CLOCK_READ(&val2);
    3434
    +            } while (val1 == val2);
    3435
    +            diff = val2 - val1;
    3436
    +            if (diff < 0) diff += CYGNUM_HAL_RTC_PERIOD;
    3437
    +            ticks -= diff;
    3438
    +            val1 = val2;
    3439
    +        }
    3440
    +    }
    3441
    +}
    3442
    +
    3443
    +/*------------------------------------------------------------------------*/
    3444
    +
    3445
    +void hal_arch_program_new_stack(void *_func)
    3446
    +{
    3447
    +    externC void hal_program_new_stack( void *func, CYG_ADDRESS addr);
    3448
    +    hal_program_new_stack( (void *)_func,
    3449
    +                   (CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - sizeof(CYG_ADDRESS)) & ~7 );
    3450
    +}
    3451
    +
    3452
    +/*------------------------------------------------------------------------*/
    3453
    +/* Idle thread action                                                     */
    3454
    +
    3455
    +#include 
    3456
    +
    3457
    +void hal_idle_thread_action( cyg_uint32 count )
    3458
    +{
    3459
    +}
    3460
    +
    3461
    +/*------------------------------------------------------------------------*/
    3462
    +/* End of hal_misc.c                                                      */
    3463
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/src/openrisc.ld ./ecos-3.0/packages/hal/openrisc/arch/v3_0/src/openrisc.ld
    3464
    --- /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/src/openrisc.ld       1969-12-31 16:00:00.000000000 -0800
    3465
    +++ ./ecos-3.0/packages/hal/openrisc/arch/v3_0/src/openrisc.ld  2010-02-17 12:34:39.947560200 -0800
    3466
    @@ -0,0 +1,177 @@
    3467
    +//==========================================================================
    3468
    +//
    3469
    +//      openrisc.ld
    3470
    +//
    3471
    +//      Linker script for OpenRISC architecture
    3472
    +//
    3473
    +//==========================================================================
    3474
    +//####ECOSGPLCOPYRIGHTBEGIN####
    3475
    +// -------------------------------------------
    3476
    +// This file is part of eCos, the Embedded Configurable Operating System.
    3477
    +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
    3478
    +//
    3479
    +// eCos is free software; you can redistribute it and/or modify it under
    3480
    +// the terms of the GNU General Public License as published by the Free
    3481
    +// Software Foundation; either version 2 or (at your option) any later version.
    3482
    +//
    3483
    +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
    3484
    +// WARRANTY; without even the implied warranty of MERCHANTABILITY or
    3485
    +// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    3486
    +// for more details.
    3487
    +//
    3488
    +// You should have received a copy of the GNU General Public License along
    3489
    +// with eCos; if not, write to the Free Software Foundation, Inc.,
    3490
    +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
    3491
    +//
    3492
    +// As a special exception, if other files instantiate templates or use macros
    3493
    +// or inline functions from this file, or you compile this file and link it
    3494
    +// with other works to produce a work based on this file, this file does not
    3495
    +// by itself cause the resulting work to be covered by the GNU General Public
    3496
    +// License. However the source code for this file must still be made available
    3497
    +// in accordance with section (3) of the GNU General Public License.
    3498
    +//
    3499
    +// This exception does not invalidate any other reasons why a work based on
    3500
    +// this file might be covered by the GNU General Public License.
    3501
    +//
    3502
    +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
    3503
    +// at http://sources.redhat.com/ecos/ecos-license/
    3504
    +// -------------------------------------------
    3505
    +//####ECOSGPLCOPYRIGHTEND####
    3506
    +//==========================================================================
    3507
    +//#####DESCRIPTIONBEGIN####
    3508
    +//
    3509
    +// Author(s):   sfurman
    3510
    +// Contributors:jskov
    3511
    +// Date:        2002-02-28
    3512
    +// Purpose:     OpenRISC Linker script
    3513
    +//
    3514
    +//####DESCRIPTIONEND####
    3515
    +//
    3516
    +//==========================================================================
    3517
    +STARTUP(vectors.o)
    3518
    +ENTRY(__exception_reset)
    3519
    +#ifdef EXTRAS
    3520
    +INPUT(extras.o)
    3521
    +#endif
    3522
    +GROUP(libtarget.a libgcc.a)
    3523
    +
    3524
    +#define ALIGN_LMA 8
    3525
    +#define FOLLOWING(_section_) AT ((LOADADDR (_section_) + SIZEOF (_section_) + ALIGN_LMA - 1) & ~ (ALIGN_LMA - 1))
    3526
    +#define LMA_EQ_VMA
    3527
    +#define FORCE_OUTPUT . = .
    3528
    +
    3529
    +
    3530
    +#define SECTIONS_BEGIN
    3531
    +
    3532
    +#define SECTION_vectors(_region_, _vma_, _lma_)        \
    3533
    +  .vectors _vma_ : _lma_                                              \
    3534
    +  { FORCE_OUTPUT; KEEP(*(.vectors)) }         \
    3535
    +  > _region_
    3536
    +
    3537
    +// Code that might be executed out of either RAM or ROM
    3538
    +#define SECTION_text(_region_, _vma_, _lma_)           \
    3539
    +  .text _vma_ : _lma_                                                 \
    3540
    +  { __stext = .;       \
    3541
    +    *(.text*) *(.gnu.warning) *(.gnu.linkonce*) *(.init) }      \
    3542
    +  > _region_                                                    \
    3543
    +  __etext = .;  PROVIDE (etext = .);
    3544
    +
    3545
    +// The .text.ram section is for performance-sensitive code that is
    3546
    +// always executed from RAM.  (If the code is loaded into ROM, it will
    3547
    +// be copied into RAM prior to execution.)
    3548
    +//
    3549
    +// Note: The SECTION_text_ram() macro must be listed in the linker
    3550
    +// include script (*.ldi file) prior to SECTION_text().
    3551
    +//
    3552
    +// All eCos code is put in the .text section unless explicitly placed
    3553
    +// into a section named section .text.ram*.
    3554
    +
    3555
    +#define SECTION_text_ram(_region_, _vma_, _lma_)           \
    3556
    +  .text.ram _vma_ : _lma_                                  \
    3557
    +  { __stext_ram = .;                                       \
    3558
    +    __ram_text_start = ABSOLUTE(.);                        \
    3559
    +    *(.text.ram*)                                          \
    3560
    +  } > _region_                                             \
    3561
    +  __load_addr_text_ram = LOADADDR(.text.ram);              \
    3562
    +  __ram_text_end = .; PROVIDE(__ram_text_end = .);         \
    3563
    +  __etext_ram = .;  PROVIDE (etext_ram = .);
    3564
    +
    3565
    +#define SECTION_fini(_region_, _vma_, _lma_)   \
    3566
    +    .fini _vma_ : _lma_                                       \
    3567
    +    { FORCE_OUTPUT; *(.fini) }        \
    3568
    +    > _region_
    3569
    +
    3570
    +#define SECTION_rodata1(_region_, _vma_, _lma_)        \
    3571
    +    .rodata1 _vma_ : _lma_                                            \
    3572
    +    { FORCE_OUTPUT; *(.rodata1*) }             \
    3573
    +    > _region_
    3574
    +
    3575
    +#define SECTION_rodata(_region_, _vma_, _lma_) \
    3576
    +    .rodata _vma_ : _lma_                                     \
    3577
    +    { FORCE_OUTPUT; *(.rodata*) }     \
    3578
    +    > _region_
    3579
    +
    3580
    +#define SECTION_fixup(_region_, _vma_, _lma_)                      \
    3581
    +    .fixup _vma_ : _lma_                                                          \
    3582
    +    { __FIXUP_START__ = ABSOLUTE(.); *(.fixup) __FIXUP_END__ = ABSOLUTE(.);}\
    3583
    +    > _region_
    3584
    +
    3585
    +#define SECTION_gcc_except_table(_region_, _vma_, _lma_)       \
    3586
    +    .gcc_except_table _vma_ : _lma_                                           \
    3587
    +    { __EXCEPT_START__ = ABSOLUTE(.); *(.gcc_except_table)              \
    3588
    +      __EXCEPT_END__ = ABSOLUTE(.);}                                    \
    3589
    +    > _region_
    3590
    +
    3591
    +#define SECTION_data(_region_, _vma_, _lma_)                         \
    3592
    +    .data _vma_ : _lma_                                                             \
    3593
    +    { __ram_data_start = ABSOLUTE(.); *(.data*)                                 \
    3594
    +    __GOT1_START__ = ABSOLUTE(.); *(.got1) __GOT1_END__ = ABSOLUTE(.);        \
    3595
    +      /* Put .ctors and .dtors next to the .got2 section, so that */          \
    3596
    +      /* the pointers get relocated with -mrelocatable.           */          \
    3597
    +     . = ALIGN(8); ___CTOR_LIST__ = ABSOLUTE(.);                               \
    3598
    +      KEEP(*(SORT(.ctors*))) ___CTOR_END__ = ABSOLUTE(.);                      \
    3599
    +    ___DTOR_LIST__ = ABSOLUTE(.);                                              \
    3600
    +      KEEP(*(SORT(.dtors*))) ___DTOR_END__ = ABSOLUTE(.);                      \
    3601
    +      . = ALIGN(8);                                                           \
    3602
    +      KEEP(*( SORT (.ecos.table.*))) ;                                        \
    3603
    +      . = ALIGN(4);                                                           \
    3604
    +      *( .2ram.*) ;                                                           \
    3605
    +    __GOT2_START__ = ABSOLUTE(.); *(.got2) __GOT2_END__ = ABSOLUTE(.);        \
    3606
    +    __GOT_START = ABSOLUTE(.); _GLOBAL_OFFSET_TABLE_ = ABSOLUTE(. + 32768);   \
    3607
    +    _SDA_BASE_ = ABSOLUTE(.); *(.got.plt) *(.got)                             \
    3608
    +    __GOT_END__ = ABSOLUTE(.);  *(.dynamic)                                   \
    3609
    +      /* We want the small data sections together, so single-instruction */   \
    3610
    +      /* offsets can access them all, and initialized data all before    */   \
    3611
    +      /* uninitialized, so we can shorten the on-disk segment size.      */   \
    3612
    +    __SDATA_START__ = ABSOLUTE(.); *(.sdata) *(.sdata.*)                      \
    3613
    +    __SDATA2_START__ = ABSOLUTE(.); *(.sdata2*) }                             \
    3614
    +    > _region_                                                                \
    3615
    +    __rom_data_start = LOADADDR(.data);                                       \
    3616
    +    __ram_data_end = .; PROVIDE(__ram_data_end = .);                          \
    3617
    +    _edata = .; PROVIDE (edata = .);
    3618
    +
    3619
    +#define SECTION_sbss(_region_, _vma_, _lma_)                     \
    3620
    +    .sbss _vma_ : _lma_                                                         \
    3621
    +    { __sbss_start = ABSOLUTE (.);                                        \
    3622
    +    __SBSS_START__ = ABSOLUTE(.); *(.sbss.*) __SBSS_END__ = ABSOLUTE(.);   \
    3623
    +    __SBSSx_START__ = ABSOLUTE(.); *(.sbss*) __SBSSx_END__ = ABSOLUTE(.);\
    3624
    +    *(.scommon*)                                                          \
    3625
    +    __sbss_end = ABSOLUTE (.); }                                          \
    3626
    +    > _region_
    3627
    +
    3628
    +#define SECTION_bss(_region_, _vma_, _lma_)                      \
    3629
    +    .bss _vma_ : _lma_                                                          \
    3630
    +    { __bss_start = ABSOLUTE (.);                       \
    3631
    +      FORCE_OUTPUT; *(.dynbss*) *(.bss*) *(COMMON)      \
    3632
    +      __bss_end = ABSOLUTE (.); }                       \
    3633
    +    > _region_
    3634
    +
    3635
    +#define SECTIONS_END . = ALIGN(4); _end = .; PROVIDE (end = .);
    3636
    +
    3637
    +#include 
    3638
    +#include CYGHWR_MEMORY_LAYOUT_LDI
    3639
    +
    3640
    +// Define VSR and virtual tables to reside at fixed addresses.
    3641
    +#include CYGBLD_HAL_TARGET_H
    3642
    +_hal_vsr_table = CYGHWR_HAL_VSR_TABLE;
    3643
    +_hal_virtual_vector_table = CYGHWR_HAL_VIRTUAL_VECTOR_TABLE;
    3644
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/src/openrisc_stub.c ./ecos-3.0/packages/hal/openrisc/arch/v3_0/src/openrisc_stub.c
    3645
    --- /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/src/openrisc_stub.c   1969-12-31 16:00:00.000000000 -0800
    3646
    +++ ./ecos-3.0/packages/hal/openrisc/arch/v3_0/src/openrisc_stub.c      2009-09-16 14:06:26.000000000 -0700
    3647
    @@ -0,0 +1,298 @@
    3648
    +//========================================================================
    3649
    +//
    3650
    +//      openrisc_stub.c
    3651
    +//
    3652
    +//      OpenRISC-specific code for remote debugging via gdb
    3653
    +//
    3654
    +//========================================================================
    3655
    +//####ECOSGPLCOPYRIGHTBEGIN####
    3656
    +// -------------------------------------------
    3657
    +// This file is part of eCos, the Embedded Configurable Operating System.
    3658
    +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
    3659
    +//
    3660
    +// eCos is free software; you can redistribute it and/or modify it under
    3661
    +// the terms of the GNU General Public License as published by the Free
    3662
    +// Software Foundation; either version 2 or (at your option) any later version.
    3663
    +//
    3664
    +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
    3665
    +// WARRANTY; without even the implied warranty of MERCHANTABILITY or
    3666
    +// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    3667
    +// for more details.
    3668
    +//
    3669
    +// You should have received a copy of the GNU General Public License along
    3670
    +// with eCos; if not, write to the Free Software Foundation, Inc.,
    3671
    +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
    3672
    +//
    3673
    +// As a special exception, if other files instantiate templates or use macros
    3674
    +// or inline functions from this file, or you compile this file and link it
    3675
    +// with other works to produce a work based on this file, this file does not
    3676
    +// by itself cause the resulting work to be covered by the GNU General Public
    3677
    +// License. However the source code for this file must still be made available
    3678
    +// in accordance with section (3) of the GNU General Public License.
    3679
    +//
    3680
    +// This exception does not invalidate any other reasons why a work based on
    3681
    +// this file might be covered by the GNU General Public License.
    3682
    +//
    3683
    +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
    3684
    +// at http://sources.redhat.com/ecos/ecos-license/
    3685
    +// -------------------------------------------
    3686
    +//####ECOSGPLCOPYRIGHTEND####
    3687
    +//========================================================================
    3688
    +//#####DESCRIPTIONBEGIN####
    3689
    +//
    3690
    +// Author(s):     sfurman
    3691
    +// Contributors:  Red Hat, jskov, gthomas
    3692
    +// Date:          2003-02-07
    3693
    +// Purpose:
    3694
    +// Description:   Helper functions for gdb stub for OpenRISC processors
    3695
    +// Usage:
    3696
    +//
    3697
    +//####DESCRIPTIONEND####
    3698
    +//
    3699
    +//========================================================================
    3700
    +
    3701
    +#include 
    3702
    +
    3703
    +#include 
    3704
    +
    3705
    +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
    3706
    +
    3707
    +#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
    3708
    +
    3709
    +#include 
    3710
    +#include 
    3711
    +#include 
    3712
    +#include 
    3713
    +#include           // assertion macros
    3714
    +
    3715
    +#ifdef CYGNUM_HAL_NO_VECTOR_TRACE
    3716
    +#define USE_BREAKPOINTS_FOR_SINGLE_STEP
    3717
    +#endif
    3718
    +
    3719
    +#ifdef CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
    3720
    +#include     // dbg_currthread_id
    3721
    +#endif
    3722
    +
    3723
    +/* Given a trap value TRAP, return the corresponding signal. */
    3724
    +
    3725
    +int __computeSignal (unsigned int trap_number)
    3726
    +{
    3727
    +    switch (trap_number)
    3728
    +    {
    3729
    +        // Either no matching page-table entry or protection fault
    3730
    +        // while executing load/store operation
    3731
    +    case CYGNUM_HAL_VECTOR_DATA_PAGE_FAULT:
    3732
    +        // Either no matching page-table entry or protection fault
    3733
    +        // while executing load/store operation
    3734
    +    case CYGNUM_HAL_VECTOR_INSTR_PAGE_FAULT:
    3735
    +        return SIGSEGV;
    3736
    +
    3737
    +        // No matching entry in D-TLB
    3738
    +    case CYGNUM_HAL_VECTOR_DTLB_MISS:
    3739
    +        // No matching entry in I-TLB
    3740
    +    case CYGNUM_HAL_VECTOR_ITLB_MISS:
    3741
    +        // Unaligned load/store memory access
    3742
    +    case CYGNUM_HAL_VECTOR_UNALIGNED_ACCESS:
    3743
    +        // Access to non-existent physical memory/device
    3744
    +    case CYGNUM_HAL_VECTOR_BUS_ERROR:
    3745
    +        return SIGBUS;
    3746
    +
    3747
    +        // TRAP instruction executed
    3748
    +    case CYGNUM_HAL_VECTOR_TRAP:
    3749
    +        return SIGTRAP;
    3750
    +
    3751
    +        /* System call instruction executed */
    3752
    +    case CYGNUM_HAL_VECTOR_SYSTEM_CALL:
    3753
    +        return SIGSYS;
    3754
    +
    3755
    +        /* Tick timer interrupt fired */
    3756
    +    case CYGNUM_HAL_VECTOR_TICK_TIMER:
    3757
    +        return SIGALRM;
    3758
    +
    3759
    +        /* External interrupt */
    3760
    +    case CYGNUM_HAL_VECTOR_INTERRUPT:
    3761
    +      return SIGINT;
    3762
    +
    3763
    +      // Illegal or reserved instruction
    3764
    +    case CYGNUM_HAL_VECTOR_RESERVED_INSTRUCTION:
    3765
    +        return SIGILL;
    3766
    +
    3767
    +        // Numeric overflow, etc.
    3768
    +    case CYGNUM_HAL_VECTOR_RANGE:
    3769
    +        return SIGFPE;
    3770
    +
    3771
    +    default:
    3772
    +        return SIGTERM;
    3773
    +    }
    3774
    +}
    3775
    +
    3776
    +
    3777
    +/* Return the trap number corresponding to the last-taken trap. */
    3778
    +
    3779
    +int __get_trap_number (void)
    3780
    +{
    3781
    +    // The vector is not not part of the GDB register set so get it
    3782
    +    // directly from the save context.
    3783
    +    return _hal_registers->vector;
    3784
    +}
    3785
    +
    3786
    +/* Set the currently-saved pc register value to PC. This also updates NPC
    3787
    +   as needed. */
    3788
    +
    3789
    +void set_pc (target_register_t pc)
    3790
    +{
    3791
    +    put_register (PC, pc);
    3792
    +}
    3793
    +
    3794
    +
    3795
    +
    3796
    +/*----------------------------------------------------------------------
    3797
    + * Single-step support
    3798
    + */
    3799
    +
    3800
    +// Type of a single OpenRISC instruction
    3801
    +typedef cyg_uint32 t_inst;
    3802
    +
    3803
    +/* Saved instruction data for single step support.  */
    3804
    +static struct
    3805
    +{
    3806
    +  t_inst *targetAddr;
    3807
    +  t_inst savedInstr;
    3808
    +} instrBuffer;
    3809
    +
    3810
    +
    3811
    +/* Set things up so that the next user resume will execute one instruction.
    3812
    +   This may be done by setting breakpoints or setting a single step flag
    3813
    +   in the saved user registers, for example. */
    3814
    +
    3815
    +void __single_step (void)
    3816
    +{
    3817
    +  t_inst *pc = (t_inst *) get_register (PC);
    3818
    +  t_inst *targetAddr;
    3819
    +  InstFmt insn;
    3820
    +  int flag;
    3821
    +
    3822
    +  targetAddr = pc + 1;              /* set default */
    3823
    +
    3824
    +  insn.word = *pc;
    3825
    +  switch (insn.JType.op) {
    3826
    +  case OP_J:
    3827
    +  case OP_JAL:
    3828
    +    targetAddr = pc + insn.JType.target;
    3829
    +    break;
    3830
    +
    3831
    +  case OP_BNF:
    3832
    +    flag = get_register(SR) & SPR_SR_F;
    3833
    +    if (!flag)
    3834
    +      targetAddr = pc + insn.JType.target;
    3835
    +    break;
    3836
    +
    3837
    +  case OP_BF:
    3838
    +    flag = get_register(SR) & SPR_SR_F;
    3839
    +    if (flag)
    3840
    +      targetAddr = pc + insn.JType.target;
    3841
    +    break;
    3842
    +
    3843
    +  case OP_JR:
    3844
    +  case OP_JALR:
    3845
    +    targetAddr = (t_inst*)get_register(insn.JRType.rB);
    3846
    +    break;
    3847
    +
    3848
    +    /* We don't step into interrupts, syscalls or traps */
    3849
    +  default:
    3850
    +    break;
    3851
    +  }
    3852
    +
    3853
    +  instrBuffer.targetAddr = targetAddr;
    3854
    +  instrBuffer.savedInstr = *targetAddr;
    3855
    +  *targetAddr = __break_opcode ();
    3856
    +
    3857
    +  // No need to flush caches; Generic stub code will handle this.
    3858
    +}
    3859
    +
    3860
    +/* Clear the single-step state. */
    3861
    +void __clear_single_step (void)
    3862
    +{
    3863
    +  if (instrBuffer.targetAddr != NULL)
    3864
    +    {
    3865
    +      *instrBuffer.targetAddr = instrBuffer.savedInstr;
    3866
    +      instrBuffer.targetAddr = NULL;
    3867
    +      instrBuffer.savedInstr = 0;
    3868
    +    }
    3869
    +}
    3870
    +
    3871
    +
    3872
    +void __install_breakpoints ()
    3873
    +{
    3874
    +  /*  if (instrBuffer.targetAddr != NULL)
    3875
    +    {
    3876
    +      instrBuffer.savedInstr = *instrBuffer.targetAddr;
    3877
    +      *instrBuffer.targetAddr = __break_opcode ();
    3878
    +      } */
    3879
    +
    3880
    +  /* Install the breakpoints in the breakpoint list */
    3881
    +  __install_breakpoint_list();
    3882
    +
    3883
    +  // No need to flush caches here; Generic stub code will handle this.
    3884
    +}
    3885
    +
    3886
    +void __clear_breakpoints (void)
    3887
    +{
    3888
    +  __clear_breakpoint_list();
    3889
    +}
    3890
    +
    3891
    +/* If the breakpoint we hit is in the breakpoint() instruction, return a
    3892
    +   non-zero value. */
    3893
    +
    3894
    +int
    3895
    +__is_breakpoint_function ()
    3896
    +{
    3897
    +    return get_register (PC) == (target_register_t)&_breakinst;
    3898
    +}
    3899
    +
    3900
    +
    3901
    +/* Skip the current instruction.  Since this is only called by the
    3902
    +   stub when the PC points to a breakpoint or trap instruction,
    3903
    +   we can safely just skip 4. */
    3904
    +
    3905
    +void __skipinst (void)
    3906
    +{
    3907
    +    put_register (PC, get_register (PC) + 4);
    3908
    +}
    3909
    +
    3910
    +target_register_t
    3911
    +get_register (regnames_t reg)
    3912
    +{
    3913
    +    GDB_Registers* gdb_regs;
    3914
    +
    3915
    +    gdb_regs = (GDB_Registers*)_registers;
    3916
    +
    3917
    +    if (reg >= R0 && reg <= R31)
    3918
    +        return gdb_regs->r[reg];
    3919
    +    if (reg == PC)
    3920
    +        return gdb_regs->pc;
    3921
    +    if (reg == SR)
    3922
    +        return gdb_regs->sr;
    3923
    +    return 0xdeadbeef;
    3924
    +}
    3925
    +
    3926
    +void
    3927
    +put_register (regnames_t reg, target_register_t value)
    3928
    +{
    3929
    +    GDB_Registers* gdb_regs;
    3930
    +
    3931
    +    gdb_regs = (GDB_Registers*)_registers;
    3932
    +
    3933
    +    if (reg >= R0 && reg <= R31) {
    3934
    +        gdb_regs->r[reg] = value;
    3935
    +    } else if (reg == PC) {
    3936
    +        gdb_regs->pc = value;
    3937
    +    } else if (reg == SR) {
    3938
    +        gdb_regs->sr = value;
    3939
    +    } else {
    3940
    +        CYG_FAIL("Attempt to write to non-existent register ");
    3941
    +    }
    3942
    +}
    3943
    +
    3944
    +#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
    3945
    +
    3946
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/src/vectors.S ./ecos-3.0/packages/hal/openrisc/arch/v3_0/src/vectors.S
    3947
    --- /opt/ecos-3.0/packages/hal/openrisc/arch/v3_0/src/vectors.S 1969-12-31 16:00:00.000000000 -0800
    3948
    +++ ./ecos-3.0/packages/hal/openrisc/arch/v3_0/src/vectors.S    2010-02-17 12:38:23.429074600 -0800
    3949
    @@ -0,0 +1,859 @@
    3950
    +##==========================================================================
    3951
    +##
    3952
    +##      Vectors.S
    3953
    +##
    3954
    +##      OpenRISC exception vectors, interrupt-handling, reset and
    3955
    +##        platform-indepent initialization
    3956
    +##
    3957
    +##==========================================================================
    3958
    +#####ECOSGPLCOPYRIGHTBEGIN####
    3959
    +## -------------------------------------------
    3960
    +## This file is part of eCos, the Embedded Configurable Operating System.
    3961
    +## Copyright (C) 2002 Red Hat, Inc.
    3962
    +##
    3963
    +## eCos is free software; you can redistribute it and/or modify it under
    3964
    +## the terms of the GNU General Public License as published by the Free
    3965
    +## Software Foundation; either version 2 or (at your option) any later version.
    3966
    +##
    3967
    +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
    3968
    +## WARRANTY; without even the implied warranty of MERCHANTABILITY or
    3969
    +## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    3970
    +## for more details.
    3971
    +##
    3972
    +## You should have received a copy of the GNU General Public License along
    3973
    +## with eCos; if not, write to the Free Software Foundation, Inc.,
    3974
    +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
    3975
    +##
    3976
    +## As a special exception, if other files instantiate templates or use macros
    3977
    +## or inline functions from this file, or you compile this file and link it
    3978
    +## with other works to produce a work based on this file, this file does not
    3979
    +## by itself cause the resulting work to be covered by the GNU General Public
    3980
    +## License. However the source code for this file must still be made available
    3981
    +## in accordance with section (3) of the GNU General Public License.
    3982
    +##
    3983
    +## This exception does not invalidate any other reasons why a work based on
    3984
    +## this file might be covered by the GNU General Public License.
    3985
    +##
    3986
    +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
    3987
    +## at http://sources.redhat.com/ecos/ecos-license/
    3988
    +## -------------------------------------------
    3989
    +#####ECOSGPLCOPYRIGHTEND####
    3990
    +##==========================================================================
    3991
    +#######DESCRIPTIONBEGIN####
    3992
    +##
    3993
    +## Author(s):    sfurman
    3994
    +## Contributors:
    3995
    +## Date:         2003-01-20
    3996
    +## Purpose:      OpenRISC interrupts, exception vectors and reset
    3997
    +## Description:  This file defines the code placed into the exception
    3998
    +##               vectors. It also contains the first level default VSRs
    3999
    +##               that save and restore state for both exceptions and
    4000
    +##               interrupts.
    4001
    +##
    4002
    +######DESCRIPTIONEND####
    4003
    +##
    4004
    +##==========================================================================
    4005
    +
    4006
    +#include 
    4007
    +
    4008
    +#ifdef CYGPKG_KERNEL
    4009
    +#include      // CYGPKG_KERNEL_INSTRUMENT
    4010
    +#endif
    4011
    +
    4012
    +#include 
    4013
    +#include 
    4014
    +
    4015
    +#===========================================================================
    4016
    +
    4017
    +
    4018
    +        .extern _hal_vsr_table
    4019
    +
    4020
    +        .extern _cyg_hal_invoke_constructors
    4021
    +        .extern _cyg_instrument
    4022
    +        .extern _cyg_start
    4023
    +        .extern _hal_IRQ_init
    4024
    +        .extern _hal_platform_init
    4025
    +        .extern _initialize_stub
    4026
    +
    4027
    +        .extern __bss_start
    4028
    +        .extern __bss_end
    4029
    +        .extern __sbss_start
    4030
    +        .extern __sbss_end
    4031
    +
    4032
    +# Include variant macros after MSR definition.
    4033
    +#include 
    4034
    +#include 
    4035
    +
    4036
    +
    4037
    +#===========================================================================
    4038
    +# Start by defining the exceptions vectors that must be placed in low
    4039
    +# memory, starting at location 0x000.
    4040
    +
    4041
    +        .section ".vectors","ax"
    4042
    +
    4043
    +#---------------------------------------------------------------------------
    4044
    +# Macros for generating an exception vector service routine
    4045
    +
    4046
    +# dummy Macros for the first 0x100 bytes
    4047
    +        .macro  dummy_vector name org
    4048
    +        .p2align 8
    4049
    +        .globl  __exception_\name
    4050
    +__exception_\name:
    4051
    +        l.nop
    4052
    +        l.nop
    4053
    +        l.nop
    4054
    +        .endm
    4055
    +
    4056
    +# Reset vector macro
    4057
    +
    4058
    +        .macro  reset_vector name org
    4059
    +        .p2align 8
    4060
    +        .globl  __exception_\name
    4061
    +__exception_\name:
    4062
    +        load32i r3,_start
    4063
    +        l.jr    r3
    4064
    +        l.nop           # delay slot
    4065
    +        .endm
    4066
    +
    4067
    +# Generic vector macro
    4068
    +
    4069
    +        .macro  exception_vector name org
    4070
    +        .p2align 8
    4071
    +        .globl  __exception_\name
    4072
    +__exception_\name:
    4073
    +        l.addi  sp,sp,-SIZEOF_OR1KREGS  # space for registers
    4074
    +
    4075
    +        # Store General Purpose Registers (GPRs).
    4076
    +
    4077
    +        l.sw     3 * OR1K_GPRSIZE(sp), r3
    4078
    +        l.sw     4 * OR1K_GPRSIZE(sp), r4
    4079
    +        l.sw     5 * OR1K_GPRSIZE(sp), r5
    4080
    +        l.sw     6 * OR1K_GPRSIZE(sp), r6
    4081
    +        l.sw     7 * OR1K_GPRSIZE(sp), r7
    4082
    +        l.sw     8 * OR1K_GPRSIZE(sp), r8
    4083
    +        l.sw     9 * OR1K_GPRSIZE(sp), r9
    4084
    +        l.sw    11 * OR1K_GPRSIZE(sp), r11
    4085
    +        l.sw    13 * OR1K_GPRSIZE(sp), r13
    4086
    +        l.sw    15 * OR1K_GPRSIZE(sp), r15
    4087
    +        l.sw    17 * OR1K_GPRSIZE(sp), r17
    4088
    +        l.sw    19 * OR1K_GPRSIZE(sp), r19
    4089
    +        l.sw    21 * OR1K_GPRSIZE(sp), r21
    4090
    +        l.sw    23 * OR1K_GPRSIZE(sp), r23
    4091
    +        l.sw    25 * OR1K_GPRSIZE(sp), r25
    4092
    +        l.sw    27 * OR1K_GPRSIZE(sp), r27
    4093
    +        l.sw    29 * OR1K_GPRSIZE(sp), r29
    4094
    +        l.sw    31 * OR1K_GPRSIZE(sp), r31
    4095
    +
    4096
    +
    4097
    +#ifndef CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
    4098
    +
    4099
    +        # R0 is not typically stored because it is always zero-valued,
    4100
    +        # but we store it here for consistency when examining registers
    4101
    +        # in the debugger.
    4102
    +        l.sw     0 * OR1K_GPRSIZE(sp), r0
    4103
    +
    4104
    +        # Callee-saved regs don't need to be preserved across a call into
    4105
    +        # an ISR, but we can do so to make debugging easier.
    4106
    +        l.sw     2 * OR1K_GPRSIZE(sp), r2
    4107
    +        l.sw    10 * OR1K_GPRSIZE(sp), r10
    4108
    +        l.sw    12 * OR1K_GPRSIZE(sp), r12
    4109
    +        l.sw    14 * OR1K_GPRSIZE(sp), r14
    4110
    +        l.sw    16 * OR1K_GPRSIZE(sp), r16
    4111
    +        l.sw    18 * OR1K_GPRSIZE(sp), r18
    4112
    +        l.sw    20 * OR1K_GPRSIZE(sp), r20
    4113
    +        l.sw    22 * OR1K_GPRSIZE(sp), r22
    4114
    +        l.sw    24 * OR1K_GPRSIZE(sp), r24
    4115
    +        l.sw    26 * OR1K_GPRSIZE(sp), r26
    4116
    +        l.sw    28 * OR1K_GPRSIZE(sp), r28
    4117
    +        l.sw    30 * OR1K_GPRSIZE(sp), r30
    4118
    +
    4119
    +       # save MAC LO and HI regs
    4120
    +        l.mfspr r5,r0,SPR_MACLO
    4121
    +        l.sw    OR1KREG_MACLO(sp),r5
    4122
    +        l.mfspr r5,r0,SPR_MACHI
    4123
    +        l.sw    OR1KREG_MACHI(sp),r5
    4124
    +#endif
    4125
    +
    4126
    +        # Save SP of interruptee in reg dump
    4127
    +        l.addi  r5,sp,SIZEOF_OR1KREGS
    4128
    +        l.sw     1 * OR1K_GPRSIZE(sp),r5
    4129
    +
    4130
    +        # ...and the PC
    4131
    +        l.mfspr r5,r0,SPR_EPCR_BASE
    4132
    +        l.sw    OR1KREG_PC(sp),r5
    4133
    +
    4134
    +        # ... and the Supervisor Register
    4135
    +        l.mfspr r5,r0,SPR_ESR_BASE
    4136
    +        l.sw    OR1KREG_SR(sp),r5
    4137
    +
    4138
    +        # ... and the exception's effective address, if there is one.
    4139
    +        # FIXME - don't need to do this for some exceptions
    4140
    +        l.mfspr r5,r0,SPR_EEAR_BASE
    4141
    +        l.sw    OR1KREG_EEAR(sp),r5
    4142
    +
    4143
    +        # Second arg to VSR is exception number
    4144
    +        # First vector is located at 0x100, second at 0x200, etc.
    4145
    +        # Shift right to get vector number for address lookup.
    4146
    +        l.ori   r4,r0,(\org>>8)
    4147
    +        l.sw    OR1KREG_VECTOR(sp),r4
    4148
    +
    4149
    +        # Lookup address of VSR in table and jump to it
    4150
    +        #   Arg 0: Pointer to HAL_SavedRegisters struct
    4151
    +        #   Arg 1: Vector #
    4152
    +        load32i r5,_hal_vsr_table+(\org>>6)
    4153
    +        l.lwz   r5,0(r5)
    4154
    +        l.jr    r5                           # To the VSR, Batman
    4155
    +
    4156
    +        # First arg to VSR is SP
    4157
    +        l.or    r3,r0,sp                     # Delay slot
    4158
    +
    4159
    +        .endm
    4160
    +
    4161
    +#---------------------------------------------------------------------------
    4162
    +# Define the exception vectors.
    4163
    +
    4164
    +rom_vectors:
    4165
    +        # These are the architecture-defined vectors that
    4166
    +        # are always present.
    4167
    +
    4168
    +        dummy_vector            dummy                   0x000
    4169
    +        reset_vector            reset                   0x100
    4170
    +        exception_vector        bus_error               0x200
    4171
    +        exception_vector        data_page_fault         0x300
    4172
    +        exception_vector        instruction_page_fault  0x400
    4173
    +        exception_vector        tick_timer              0x500
    4174
    +        exception_vector        unaligned_access        0x600
    4175
    +        exception_vector        illegal_instruction     0x700
    4176
    +        exception_vector        external_interrupt      0x800
    4177
    +        exception_vector        dtlb_miss               0x900
    4178
    +        exception_vector        itlb_miss               0xa00
    4179
    +        exception_vector        range                   0xb00
    4180
    +        exception_vector        syscall                 0xc00
    4181
    +        exception_vector        reserved                0xd00
    4182
    +        exception_vector        trap                    0xe00
    4183
    +
    4184
    +rom_vectors_end:
    4185
    +
    4186
    +
    4187
    +#if     defined(CYG_HAL_STARTUP_ROM) ||                 \
    4188
    +        (       defined(CYG_HAL_STARTUP_RAM) &&         \
    4189
    +                !defined(CYGSEM_HAL_USE_ROM_MONITOR))
    4190
    +
    4191
    +        .macro  hal_vsr_table_init
    4192
    +
    4193
    +        # Next initialize the VSR table. This happens whether the
    4194
    +        # vectors were copied to RAM or not.
    4195
    +
    4196
    +        # First fill with exception handlers
    4197
    +        load32i r3,_cyg_hal_default_exception_vsr
    4198
    +        load32i r4,_hal_vsr_table+4  # First entry in table is unused
    4199
    +        l.ori   r5,r0,CYGNUM_HAL_VSR_COUNT
    4200
    +1:      l.sw    0(r4),r3
    4201
    +        l.addi  r5,r5,-1
    4202
    +        l.sfgtsi r5,0
    4203
    +        l.bf    1b
    4204
    +        l.addi  r4,r4,4         # delay slot
    4205
    +
    4206
    +        # Then fill in the interrupt handlers
    4207
    +        load32i r4,_hal_vsr_table
    4208
    +        load32i r3,_cyg_hal_default_interrupt_vsr
    4209
    +        l.sw    CYGNUM_HAL_VECTOR_INTERRUPT*4(r4),r3
    4210
    +        l.sw    CYGNUM_HAL_VECTOR_TICK_TIMER*4(r4),r3
    4211
    +        .endm
    4212
    +
    4213
    +#elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR)
    4214
    +
    4215
    +        # Initialize the VSR table entries
    4216
    +        # We only take control of the interrupt vectors,
    4217
    +        # the rest are left to the ROM for now...
    4218
    +
    4219
    +        .macro  hal_vsr_table_init
    4220
    +        load32i r4,_hal_vsr_table
    4221
    +        load32i r3,_cyg_hal_default_interrupt_vsr
    4222
    +        l.sw    CYGNUM_HAL_VECTOR_INTERRUPT*4(r4),r3
    4223
    +        l.sw    CYGNUM_HAL_VECTOR_TICK_TIMER*4(r4),r3
    4224
    +        .endm
    4225
    +
    4226
    +
    4227
    +#else
    4228
    +
    4229
    +#error "Need to define hal_vsr_table_init"
    4230
    +
    4231
    +#endif
    4232
    +
    4233
    +# I-Cache initialization macro
    4234
    +        .macro  hal_icache_init
    4235
    +        /* Disable I-Cache */
    4236
    +        l.mfspr r13,r0,SPR_SR
    4237
    +        l.addi  r11,r0,-1
    4238
    +        l.xori  r11,r11,SPR_SR_ICE
    4239
    +        l.and   r11,r13,r11
    4240
    +        l.mtspr r0,r11,SPR_SR
    4241
    +
    4242
    +        /* Invalidate I-Cache */
    4243
    +        l.addi  r13,r0,0
    4244
    +        l.addi  r11,r0,HAL_ICACHE_SIZE
    4245
    +1:
    4246
    +        l.mtspr r0,r13,SPR_ICBIR
    4247
    +        l.sfne  r13,r11
    4248
    +        l.bf    1b
    4249
    +        l.addi  r13,r13,HAL_ICACHE_LINE_SIZE
    4250
    +
    4251
    +        /* Enable I-Cache */
    4252
    +        l.mfspr r13,r0,SPR_SR
    4253
    +        l.ori   r13,r13,SPR_SR_ICE
    4254
    +        l.mtspr r0,r13,SPR_SR
    4255
    +
    4256
    +        /* Flush instructions out of instruction buffer */
    4257
    +        l.nop
    4258
    +        l.nop
    4259
    +        l.nop
    4260
    +        l.nop
    4261
    +        l.nop
    4262
    +        .endm
    4263
    +
    4264
    +# D-Cache initialization macro
    4265
    +        .macro  hal_dcache_init
    4266
    +
    4267
    +        /* Flush DC */
    4268
    +        l.addi  r10,r0,0
    4269
    +        l.addi  r11,r0,HAL_DCACHE_SIZE
    4270
    +1:
    4271
    +        l.mtspr r0,r10,SPR_DCBIR
    4272
    +        l.sfne  r10,r11
    4273
    +        l.bf    1b
    4274
    +        l.addi  r10,r10,HAL_DCACHE_LINE_SIZE
    4275
    +
    4276
    +        /* Enable DC */
    4277
    +        l.mfspr r10,r0,SPR_SR
    4278
    +        l.ori   r10,r10,SPR_SR_DCE
    4279
    +        l.mtspr r0,r10,SPR_SR
    4280
    +        .endm
    4281
    +
    4282
    +#===========================================================================
    4283
    +# Startup code:  We jump here from the reset vector to set up the world.
    4284
    +
    4285
    +        .text
    4286
    +
    4287
    +FUNC_START(start)
    4288
    +
    4289
    +        # Initialize Supervision Register:
    4290
    +        #   Supervisor mode on, all interrupts off, caches off
    4291
    +        #
    4292
    +        # (If we've entered here from a hardware reset, then the SR is already
    4293
    +        # set to this value, but we may have jumped here as part of a soft
    4294
    +        # system reset.)
    4295
    +        l.ori   r3,r0,SPR_SR_SM
    4296
    +        l.mtspr r0,r3,SPR_SR
    4297
    +
    4298
    +        # Run platform-specific hardware initialization code.
    4299
    +        # This may include memory controller initialization.
    4300
    +        # Hence, it is not safe to access RAM until after this point.
    4301
    +        hal_hardware_init
    4302
    +
    4303
    +#ifdef CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP
    4304
    +        # Enable I-Cache
    4305
    +        hal_icache_init
    4306
    +#endif
    4307
    +
    4308
    +#ifdef CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP
    4309
    +        # Enable D-Cache
    4310
    +        hal_dcache_init
    4311
    +#endif
    4312
    +
    4313
    +       # Start the tick timer, in case timer polling routine hal_delay_us() is called.
    4314
    +       # Initially, no interrupts are generated by the tick timer.  Later on, that
    4315
    +       # may change when the kernel is initialized.
    4316
    +       l.movhi r3, hi(0x40000000|CYGNUM_HAL_RTC_PERIOD)
    4317
    +       l.mtspr r0,r3, SPR_TTMR
    4318
    +
    4319
    +        .globl  _hal_hardware_init_done
    4320
    +_hal_hardware_init_done:
    4321
    +
    4322
    +        # set up stack
    4323
    +        load32i sp,__interrupt_stack
    4324
    +
    4325
    +        # Make a dummy frame on the stack, so that stack backtraces are sane
    4326
    +        # for debugging.  On return from that function, the restore_state()
    4327
    +        # function is called to resume the interrupted thread.
    4328
    +        l.addi  sp,sp,-8
    4329
    +        l.sw    4(sp),r0        # Dummy saved FP
    4330
    +        l.sw    0(sp),r0        # Dummy saved LR
    4331
    +
    4332
    +        # Set up exception handlers and VSR table, taking care not to
    4333
    +        # step on any ROM monitor VSRs.
    4334
    +        hal_vsr_table_init
    4335
    +
    4336
    +#if defined(CYG_HAL_STARTUP_ROM)
    4337
    +        # Copy exception/interrupt vectors from ROM to address 0x100
    4338
    +        load32i r4,0x100
    4339
    +        load32i r3,rom_vectors
    4340
    +        load32i r5,rom_vectors_end
    4341
    +1:      l.sfeq  r3,r5
    4342
    +        l.bf    2f
    4343
    +        l.lwz   r6,0(r3)
    4344
    +        l.sw    0(r4),r6
    4345
    +        l.addi  r3,r3,4
    4346
    +        l.j     1b
    4347
    +        l.addi  r4,r4,4         # delay slot
    4348
    +2:
    4349
    +
    4350
    +        # Copy .data section into RAM
    4351
    +        load32i r3,__rom_data_start
    4352
    +        load32i r4,__ram_data_start
    4353
    +        load32i r5,__ram_data_end
    4354
    +1:      l.sfeq  r4,r5
    4355
    +        l.bf    2f
    4356
    +        l.lwz   r6,0(r3)
    4357
    +        l.sw    0(r4),r6
    4358
    +        l.addi  r3,r3,4
    4359
    +        l.j     1b
    4360
    +        l.addi  r4,r4,4         # delay slot
    4361
    +2:
    4362
    +
    4363
    +#endif
    4364
    +
    4365
    +        # clear BSS
    4366
    +        load32i r4,__bss_start
    4367
    +        load32i r5,__bss_end
    4368
    +1:      l.sfeq  r4,r5
    4369
    +        l.bf    2f
    4370
    +        l.nop
    4371
    +        l.sw    0(r4),r0
    4372
    +        l.j     1b
    4373
    +        l.addi  r4,r4,4
    4374
    +2:
    4375
    +
    4376
    +        # Note:  no SBSS section to clear with OpenRISC target
    4377
    +
    4378
    +        # Platform-specific initialization
    4379
    +        l.jal   _hal_platform_init
    4380
    +        l.nop   # delay slot
    4381
    +
    4382
    +        # call c++ constructors
    4383
    +        l.jal   _cyg_hal_invoke_constructors
    4384
    +        l.nop   # delay slot
    4385
    +
    4386
    +# pause sim
    4387
    +load32i r3,0x5ffffffc
    4388
    +load32i r5,0xcea5e0ff
    4389
    +l.sw    (0)(r3),r5
    4390
    +
    4391
    +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
    4392
    +        l.jal   _initialize_stub
    4393
    +        l.nop   # delay slot
    4394
    +#endif
    4395
    +
    4396
    +#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) \
    4397
    +    || defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT)
    4398
    +        .extern _hal_ctrlc_isr_init
    4399
    +        l.jal   _hal_ctrlc_isr_init
    4400
    +        l.nop   # delay slot
    4401
    +#endif
    4402
    +
    4403
    +# pause sim
    4404
    +load32i r3,0x5ffffffc
    4405
    +load32i r5,0xcea5e0ff
    4406
    +l.sw    (0)(r3),r5
    4407
    +
    4408
    +        l.jal   _cyg_start       # call cyg_start()
    4409
    +        l.nop   # delay slot
    4410
    +9:
    4411
    +        l.j     9b              # if we return, loop
    4412
    +
    4413
    +FUNC_END(start)
    4414
    +
    4415
    +#---------------------------------------------------------------------------
    4416
    +# This code handles the common part of all exception handlers.
    4417
    +# On entry, the machine state is already saved on the stack.
    4418
    +#
    4419
    +# R3 = pointer to HAL_SavedRegisters struct containing saved machine state
    4420
    +# R4 = Vector number
    4421
    +#
    4422
    +# It calls a C routine to do any work, which may result in
    4423
    +# thread switches and changes to the saved state. When we return
    4424
    +# here, the saved state is restored and execution is continued.
    4425
    +
    4426
    +        .text
    4427
    +
    4428
    +FUNC_START(cyg_hal_default_exception_vsr)
    4429
    +
    4430
    +        .extern _cyg_hal_exception_handler
    4431
    +
    4432
    +        # Call C code
    4433
    +
    4434
    +        # When cyg_hal_exception_handler() returns, it will jump
    4435
    +       # directly to restore_state(), which will resume execution
    4436
    +       # at the location of the exception.
    4437
    +        l.movhi r9, hi(restore_state)
    4438
    +        l.j     _cyg_hal_exception_handler
    4439
    +        l.ori   r9,r9,lo(restore_state) #Delay slot
    4440
    +
    4441
    +        # Control never reaches this point,
    4442
    +
    4443
    +FUNC_END(cyg_hal_default_exception_vsr)
    4444
    +
    4445
    +#---------------------------------------------------------------------------
    4446
    +# This code handles all interrupts and dispatches to a C ISR function
    4447
    +# On entry, the machine state is already saved on the stack.
    4448
    +#
    4449
    +# R3 = pointer to HAL_SavedRegisters struct containing saved machine state
    4450
    +# R4 = Vector number
    4451
    +#
    4452
    +# After we return here, the saved state is restored and execution is continued.
    4453
    +
    4454
    +#ifdef CYGIMP_FORCE_INTERRUPT_HANDLING_CODE_IN_RAM
    4455
    +       .section .text.ram,"ax"
    4456
    +#else
    4457
    +       .section .text,"ax"
    4458
    +#endif
    4459
    +
    4460
    +FUNC_START(cyg_hal_default_interrupt_vsr)
    4461
    +
    4462
    +        # Stash away pointer to saved regs for later
    4463
    +        l.or    r31,r3,r3
    4464
    +
    4465
    +        # Set scheduler lock to prevent thread rescheduling while the ISR runs
    4466
    +#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
    4467
    +        .extern _cyg_scheduler_sched_lock
    4468
    +        load32i r5, _cyg_scheduler_sched_lock
    4469
    +        l.lwz   r6,0(r5)
    4470
    +        l.addi  r6,r6,1
    4471
    +        l.sw    0(r5),r6
    4472
    +#endif
    4473
    +
    4474
    +#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
    4475
    +        # Interrupts execute on their own dedicated stack.
    4476
    +        # If we're on a thread stack, switch to the interrupt stack.
    4477
    +        # If we're called inside a nested interrupt, do nothing.
    4478
    +        l.or    r6,sp,sp                        # Stash SP for later
    4479
    +        load32i r7,__interrupt_stack            # stack top (highest addr + 1)
    4480
    +        load32i r8,__interrupt_stack_base       # stack base (lowest addr)
    4481
    +        l.sfltu sp,r8                           # if (sp < __interrupt_stack_base)
    4482
    +        l.bf    1f                              #    switch to interrupt stack
    4483
    +        l.sfltu sp,r7                           # if (sp < __interrupt_stack_top)
    4484
    +        l.bf   2f                               #    already on interrupt stack
    4485
    +        l.nop                                   # delay slot
    4486
    +1:      l.or    sp,r7,r7                        # Switch to interrupt stack
    4487
    +2:      l.addi  sp,sp,-8                        # Make space to save old SP...
    4488
    +        l.sw    0(sp),r6                        # ...and save it on the stack
    4489
    +#endif
    4490
    +
    4491
    +        # Call C code
    4492
    +
    4493
    +#if defined(CYGPKG_KERNEL_INSTRUMENT) && defined(CYGDBG_KERNEL_INSTRUMENT_INTR)
    4494
    +        # Log the interrupt if kernel tracing is enabled
    4495
    +        l.ori   r3,r0,0x0301                    # arg1 = type = INTR,RAISE
    4496
    +                                                # arg2 = vector number
    4497
    +        l.ori   r5,r0,r0                        # arg3 = 0
    4498
    +        l.jal   _cyg_instrument                  # call instrument function
    4499
    +
    4500
    +#endif
    4501
    +
    4502
    +#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) \
    4503
    +    || defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT)
    4504
    +        # If we are supporting Ctrl-C interrupts from GDB, we must squirrel
    4505
    +        # away a pointer to the save interrupt state here so that we can
    4506
    +        # plant a breakpoint at some later time.
    4507
    +
    4508
    +        .extern _hal_saved_interrupt_state
    4509
    +        load32i r8,_hal_saved_interrupt_state
    4510
    +        l.sw    0(r8),r31
    4511
    +
    4512
    +#endif
    4513
    +
    4514
    +        # In the event of multiple pending interrupts, determine which
    4515
    +        # one will be serviced first.  By software convention, the lowest
    4516
    +        # numbered external interrupt gets priority.
    4517
    +        #
    4518
    +        # The (internal) tick timer interrupt is serviced only if no
    4519
    +        # external interrupts are pending.
    4520
    +
    4521
    +        # Read the PIC interrupt controller's status register
    4522
    +        l.mfspr r9,r0,SPR_PICSR
    4523
    +
    4524
    +        # Any pending external interrupts ?
    4525
    +        l.sfnei r9,0
    4526
    +        l.bf    check_for_external_interrupts
    4527
    +
    4528
    +        # Theoretically, the only way we could get here is if the tick timer
    4529
    +        # interrupt fired, but we check to be sure that's what happened.
    4530
    +        l.sfeqi r4,CYGNUM_HAL_VECTOR_TICK_TIMER
    4531
    +        l.bf    3f
    4532
    +        l.ori   r3,r0,CYGNUM_HAL_INTERRUPT_RTC  # delay slot
    4533
    +
    4534
    +#ifndef CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS
    4535
    +        l.jal   _hal_spurious_IRQ
    4536
    +        l.nop
    4537
    +#endif // CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS
    4538
    +        l.j     ignore_spurious_interrupt
    4539
    +
    4540
    +        # Identify the lowest numbered interrupt bit in the PIC's PSR,
    4541
    +        # numbering the MSB as 31 and the LSB as 0
    4542
    +check_for_external_interrupts:
    4543
    +        l.ori   r3,r0,0
    4544
    +2:      l.andi  r11,r9,1                        # Test low bit
    4545
    +        l.sfnei r11,0
    4546
    +        l.bf    3f
    4547
    +        l.srli  r9,r9,1                         # Shift right 1 bit
    4548
    +        l.j     2b
    4549
    +        l.addi  r3,r3,1                         # Delay slot
    4550
    +3:
    4551
    +
    4552
    +        # At this point, r3 contains the ISR number, from 0-32
    4553
    +        # which will be used to index the table of ISRs
    4554
    +        l.slli  r15,r3,2
    4555
    +        load32i r9, _hal_interrupt_handlers     # get interrupt handler table
    4556
    +        l.add   r9,r9,r15
    4557
    +        l.lwz   r11,0(r9)                       # load ISR pointer
    4558
    +        load32i r9, _hal_interrupt_data         # get interrupt data table
    4559
    +        l.add   r9,r9,r15
    4560
    +        l.lwz   r4,0(r9)                        # load data arg to ISR
    4561
    +
    4562
    +        # Call ISR
    4563
    +        #   arg0 = ISR #
    4564
    +        #   arg1 = data arg associated with interrupt
    4565
    +        l.jalr  r11
    4566
    +        l.nop
    4567
    +
    4568
    +ignore_spurious_interrupt:
    4569
    +
    4570
    +#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
    4571
    +
    4572
    +        # If we are returning from the last nested interrupt, move back
    4573
    +        # to the thread stack. interrupt_end() must be called on the
    4574
    +        # thread stack since it potentially causes a context switch.
    4575
    +        # Since we have arranged for the top of stack location to
    4576
    +        # contain the sp we need to go back to here, just pop it off
    4577
    +        # and put it in SP.
    4578
    +
    4579
    +        l.lwz   sp,0(sp)
    4580
    +#endif
    4581
    +
    4582
    +#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
    4583
    +
    4584
    +        # We only need to call _interrupt_end() when there is a kernel
    4585
    +        # present to do any tidying up.
    4586
    +
    4587
    +        # on return r11 bit 1 will indicate whether a DSR is
    4588
    +        # to be posted. Pass this together with a pointer to
    4589
    +        # the interrupt object we have just used to the
    4590
    +        # interrupt tidy up routine.
    4591
    +        l.or    r3,r11,r11
    4592
    +
    4593
    +        # Get pointer to HAL_SavedRegisters struct, stashed earlier
    4594
    +        l.or    r5,r31,r31
    4595
    +
    4596
    +        # Get opaque object associated w/ interrupt vector
    4597
    +        load32i r9, _hal_interrupt_objects          # get interrupt data table
    4598
    +        l.add   r9,r9,r15
    4599
    +        l.lwz   r4,0(r9)
    4600
    +
    4601
    +        # Call interrupt_end() to execute any pending DSRs
    4602
    +        #   Arg 0 = return value from ISR
    4603
    +        #   Arg 1 = object associated with interrupt
    4604
    +        #   Arg 2 = HAL_SavedRegisters struct
    4605
    +
    4606
    +        .extern _interrupt_end
    4607
    +        l.jal   _interrupt_end                   # call into C to finish off
    4608
    +        l.nop
    4609
    +#endif
    4610
    +
    4611
    +        # Fall through to restore_state...
    4612
    +
    4613
    +# Return from either an interrupt or an exception
    4614
    +#
    4615
    +# On entry:
    4616
    +#    SP = pointer to (HAL_SavedRegisters struct)
    4617
    +#
    4618
    +restore_state:
    4619
    +
    4620
    +        # Restore General Purpose Registers (GPRs).
    4621
    +        # R0 is not restored because it is always zero-valued.
    4622
    +        # R1, R3, and R4 are used as temps, so they are restored a little later
    4623
    +        l.lwz   r5,   5 * OR1K_GPRSIZE(sp)
    4624
    +        l.lwz   r6,   6 * OR1K_GPRSIZE(sp)
    4625
    +        l.lwz   r7,   7 * OR1K_GPRSIZE(sp)
    4626
    +        l.lwz   r8,   8 * OR1K_GPRSIZE(sp)
    4627
    +        l.lwz   r9,   9 * OR1K_GPRSIZE(sp)
    4628
    +        l.lwz   r11, 11 * OR1K_GPRSIZE(sp)
    4629
    +        l.lwz   r13, 13 * OR1K_GPRSIZE(sp)
    4630
    +        l.lwz   r15, 15 * OR1K_GPRSIZE(sp)
    4631
    +        l.lwz   r17, 17 * OR1K_GPRSIZE(sp)
    4632
    +        l.lwz   r19, 19 * OR1K_GPRSIZE(sp)
    4633
    +        l.lwz   r21, 21 * OR1K_GPRSIZE(sp)
    4634
    +        l.lwz   r23, 23 * OR1K_GPRSIZE(sp)
    4635
    +        l.lwz   r25, 25 * OR1K_GPRSIZE(sp)
    4636
    +        l.lwz   r27, 27 * OR1K_GPRSIZE(sp)
    4637
    +        l.lwz   r29, 29 * OR1K_GPRSIZE(sp)
    4638
    +        l.lwz   r31, 31 * OR1K_GPRSIZE(sp)
    4639
    +
    4640
    +#ifndef CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
    4641
    +        # Callee-saved regs don't need to be preserved across a call into
    4642
    +        # an ISR, but we can do so to make debugging easier.
    4643
    +
    4644
    +        l.lwz   r2,   2 * OR1K_GPRSIZE(sp)
    4645
    +        l.lwz   r10, 10 * OR1K_GPRSIZE(sp)
    4646
    +        l.lwz   r12, 12 * OR1K_GPRSIZE(sp)
    4647
    +        l.lwz   r14, 14 * OR1K_GPRSIZE(sp)
    4648
    +        l.lwz   r16, 16 * OR1K_GPRSIZE(sp)
    4649
    +        l.lwz   r18, 18 * OR1K_GPRSIZE(sp)
    4650
    +        l.lwz   r20, 20 * OR1K_GPRSIZE(sp)
    4651
    +        l.lwz   r22, 22 * OR1K_GPRSIZE(sp)
    4652
    +        l.lwz   r24, 24 * OR1K_GPRSIZE(sp)
    4653
    +        l.lwz   r26, 26 * OR1K_GPRSIZE(sp)
    4654
    +        l.lwz   r28, 28 * OR1K_GPRSIZE(sp)
    4655
    +        l.lwz   r30, 30 * OR1K_GPRSIZE(sp)
    4656
    +
    4657
    +        # Restore MAC LO and HI regs
    4658
    +        l.lwz   r4, OR1KREG_MACLO(sp)
    4659
    +        l.mtspr r0,r4,SPR_MACLO
    4660
    +        l.lwz   r4, OR1KREG_MACHI(sp)
    4661
    +        l.mtspr r0,r4,SPR_MACHI
    4662
    +#endif
    4663
    +
    4664
    +        # Must disable interrupts, since they could clobber ESR and EPC regs
    4665
    +        l.mfspr r3, r0, SPR_SR
    4666
    +        load32i r4,~(SPR_SR_TEE|SPR_SR_IEE)
    4667
    +        l.and   r3, r4, r3
    4668
    +        l.mtspr r0, r3, SPR_SR
    4669
    +
    4670
    +        # At this point we've restored all the pre-interrupt GPRs except for the SP.
    4671
    +        # Restore pre-interrupt SR, SP, and PC
    4672
    +        l.lwz    r4,  OR1KREG_SR(sp)
    4673
    +        l.mtspr  r0, r4, SPR_ESR_BASE
    4674
    +
    4675
    +        l.lwz    r4,  OR1KREG_PC(sp)
    4676
    +        l.mtspr  r0, r4, SPR_EPCR_BASE
    4677
    +
    4678
    +        l.lwz   r4,   4 * OR1K_GPRSIZE(sp)
    4679
    +        l.lwz   r3,   3 * OR1K_GPRSIZE(sp)
    4680
    +        l.lwz    sp,  1 * OR1K_GPRSIZE(sp)
    4681
    +
    4682
    +        # All done, restore CPU state and continue
    4683
    +        l.rfe
    4684
    +        l.nop           # Delay slot
    4685
    +
    4686
    +
    4687
    +##-----------------------------------------------------------------------------
    4688
    +## Execute pending DSRs on the interrupt stack with interrupts enabled.
    4689
    +## Note: this can only be called from code running on a thread stack
    4690
    +
    4691
    +#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
    4692
    +        .extern _cyg_interrupt_call_pending_DSRs
    4693
    +
    4694
    +       .text
    4695
    +FUNC_START(hal_interrupt_stack_call_pending_DSRs)
    4696
    +        # Switch to interrupt stack
    4697
    +        l.or    r3, sp, sp      # Stash entry SP
    4698
    +        load32i sp, __interrupt_stack
    4699
    +        l.addi  sp, sp, -16
    4700
    +        l.sw    0(sp), r3       # Save entry SP
    4701
    +        l.mfspr r4,r0,SPR_SR
    4702
    +        l.sw    4(sp), r4       # Save interrupt state
    4703
    +        l.ori   r4, r4, SPR_SR_IEE|SPR_SR_TEE
    4704
    +        l.sw    8(sp),lr
    4705
    +
    4706
    +        l.jal   _cyg_interrupt_call_pending_DSRs
    4707
    +       # Enable interrupts before calling DSRs
    4708
    +       l.mtspr r0, r4, SPR_SR  # Delay slot
    4709
    +
    4710
    +        l.lwz   r4, 4(sp)
    4711
    +        l.lwz   lr, 8(sp)
    4712
    +        l.lwz   sp, 0(sp)
    4713
    +
    4714
    +        # Merge original interrupt state with (possibly altered) SR reg
    4715
    +        l.andi  r4, r4, SPR_SR_IEE|SPR_SR_TEE
    4716
    +        l.mfspr r5, r0, SPR_SR
    4717
    +        load32i r6, ~(SPR_SR_IEE|SPR_SR_TEE)
    4718
    +        l.and   r5, r5, r6
    4719
    +        l.or    r4, r4, r5
    4720
    +
    4721
    +        l.jr    r9
    4722
    +        l.mtspr r0, r4, SPR_SR  # Delay slot
    4723
    +
    4724
    +FUNC_END(hal_interrupt_stack_call_pending_DSRs)
    4725
    +#endif
    4726
    +
    4727
    +##-----------------------------------------------------------------------------
    4728
    +## Switch to a new stack.
    4729
    +## This is used in RedBoot to allow code to execute in a different
    4730
    +## stack context.
    4731
    +
    4732
    +FUNC_START(hal_program_new_stack)
    4733
    +        # Arguments are:
    4734
    +        # r3 = function to call
    4735
    +        # r4 = stack pointer to use
    4736
    +
    4737
    +        # Dummy prologue, so that debugger is fooled into thinking there
    4738
    +        # is a stack frame.  The debugger will use the offsets in the prologue
    4739
    +        # below to read the saved register values out of the *new* stack.
    4740
    +        l.addi  sp,sp,-8
    4741
    +        l.sw    0(sp),fp
    4742
    +        l.addi  fp,sp,8
    4743
    +        l.sw    4(sp),lr
    4744
    +
    4745
    +        l.or    r5,sp,sp        # Remember original SP
    4746
    +        l.addi  r6,fp,-8        # Remember original FP
    4747
    +        l.or    sp,r4,r4        # Switch to new stack
    4748
    +
    4749
    +        # "Real prologue" - Offsets here must match dummy prologue above
    4750
    +        l.addi  sp,sp,-16
    4751
    +        l.sw    0(sp),r6        # So debugger can know caller's FP
    4752
    +        l.sw    4(sp),lr        # So debugger can know caller's PC
    4753
    +        l.sw    8(sp),r5        # Save old SP on stack
    4754
    +
    4755
    +        # Call function
    4756
    +        l.jalr  r3
    4757
    +        l.nop
    4758
    +
    4759
    +        l.lwz   sp, 8(sp)       # Restore original SP
    4760
    +        l.lwz   lr, 4(sp)
    4761
    +        l.jr    lr              # Return to caller
    4762
    +        l.addi  sp,sp, 8        # Delay slot
    4763
    +
    4764
    +FUNC_END(hal_program_new_stack)
    4765
    +
    4766
    +#---------------------------------------------------------------------------
    4767
    +## Temporary interrupt stack
    4768
    +
    4769
    +        .section ".bss"
    4770
    +
    4771
    +        .balign 16
    4772
    +        .global _cyg_interrupt_stack_base
    4773
    +_cyg_interrupt_stack_base:
    4774
    +__interrupt_stack_base:
    4775
    +        .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
    4776
    +        .byte 0
    4777
    +        .endr
    4778
    +        .balign 16
    4779
    +        .global _cyg_interrupt_stack
    4780
    +_cyg_interrupt_stack:
    4781
    +__interrupt_stack:
    4782
    +
    4783
    +        .long   0,0,0,0,0,0,0,0
    4784
    +
    4785
    +#--------------------------------------
    4786
    +        .data
    4787
    +        .extern _hal_default_isr
    4788
    +
    4789
    +        .globl  _hal_interrupt_handlers
    4790
    +_hal_interrupt_handlers:
    4791
    +        .rept   CYGNUM_HAL_ISR_COUNT
    4792
    +        .long   _hal_default_isr
    4793
    +        .endr
    4794
    +
    4795
    +        .globl  _hal_interrupt_data
    4796
    +_hal_interrupt_data:
    4797
    +        .rept   CYGNUM_HAL_ISR_COUNT
    4798
    +        .long   0
    4799
    +        .endr
    4800
    +
    4801
    +        .globl  _hal_interrupt_objects
    4802
    +_hal_interrupt_objects:
    4803
    +        .rept   CYGNUM_HAL_ISR_COUNT
    4804
    +        .long   0
    4805
    +        .endr
    4806
    +
    4807
    +#---------------------------------------------------------------------------
    4808
    +# end of vectors.S
    4809
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/ChangeLog ./ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/ChangeLog
    4810
    --- /opt/ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/ChangeLog       1969-12-31 16:00:00.000000000 -0800
    4811
    +++ ./ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/ChangeLog  2010-02-05 17:03:32.661243000 -0800
    4812
    @@ -0,0 +1,38 @@
    4813
    +
    4814
    +        Initial port of eCos to OpenRISC or1200 Platform (OR1200)
    4815
    +
    4816
    +//===========================================================================
    4817
    +//####ECOSGPLCOPYRIGHTBEGIN####
    4818
    +// -------------------------------------------
    4819
    +// This file is part of eCos, the Embedded Configurable Operating System.
    4820
    +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
    4821
    +// Copyright (C) 2002 Gary Thomas
    4822
    +//
    4823
    +// eCos is free software; you can redistribute it and/or modify it under
    4824
    +// the terms of the GNU General Public License as published by the Free
    4825
    +// Software Foundation; either version 2 or (at your option) any later version.
    4826
    +//
    4827
    +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
    4828
    +// WARRANTY; without even the implied warranty of MERCHANTABILITY or
    4829
    +// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    4830
    +// for more details.
    4831
    +//
    4832
    +// You should have received a copy of the GNU General Public License along
    4833
    +// with eCos; if not, write to the Free Software Foundation, Inc.,
    4834
    +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
    4835
    +//
    4836
    +// As a special exception, if other files instantiate templates or use macros
    4837
    +// or inline functions from this file, or you compile this file and link it
    4838
    +// with other works to produce a work based on this file, this file does not
    4839
    +// by itself cause the resulting work to be covered by the GNU General Public
    4840
    +// License. However the source code for this file must still be made available
    4841
    +// in accordance with section (3) of the GNU General Public License.
    4842
    +//
    4843
    +// This exception does not invalidate any other reasons why a work based on
    4844
    +// this file might be covered by the GNU General Public License.
    4845
    +//
    4846
    +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
    4847
    +// at http://sources.redhat.com/ecos/ecos-license/
    4848
    +// -------------------------------------------
    4849
    +//####ECOSGPLCOPYRIGHTEND####
    4850
    +//===========================================================================
    4851
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/cdl/hal_openrisc_or1200_soc.cdl ./ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/cdl/hal_openrisc_or1200_soc.cdl
    4852
    --- /opt/ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/cdl/hal_openrisc_or1200_soc.cdl 1969-12-31 16:00:00.000000000 -0800
    4853
    +++ ./ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/cdl/hal_openrisc_or1200_soc.cdl    2010-02-17 11:06:26.624690600 -0800
    4854
    @@ -0,0 +1,335 @@
    4855
    +# ====================================================================
    4856
    +#
    4857
    +#      hal_openrisc_or1200_soc.cdl
    4858
    +#
    4859
    +#      OpenRISC or1200 Platform (OR1200) HAL package configuration data
    4860
    +#
    4861
    +# ====================================================================
    4862
    +#####ECOSGPLCOPYRIGHTBEGIN####
    4863
    +## -------------------------------------------
    4864
    +## This file is part of eCos, the Embedded Configurable Operating System.
    4865
    +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
    4866
    +##
    4867
    +## eCos is free software; you can redistribute it and/or modify it under
    4868
    +## the terms of the GNU General Public License as published by the Free
    4869
    +## Software Foundation; either version 2 or (at your option) any later version.
    4870
    +##
    4871
    +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
    4872
    +## WARRANTY; without even the implied warranty of MERCHANTABILITY or
    4873
    +## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    4874
    +## for more details.
    4875
    +##
    4876
    +## You should have received a copy of the GNU General Public License along
    4877
    +## with eCos; if not, write to the Free Software Foundation, Inc.,
    4878
    +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
    4879
    +##
    4880
    +## As a special exception, if other files instantiate templates or use macros
    4881
    +## or inline functions from this file, or you compile this file and link it
    4882
    +## with other works to produce a work based on this file, this file does not
    4883
    +## by itself cause the resulting work to be covered by the GNU General Public
    4884
    +## License. However the source code for this file must still be made available
    4885
    +## in accordance with section (3) of the GNU General Public License.
    4886
    +##
    4887
    +## This exception does not invalidate any other reasons why a work based on
    4888
    +## this file might be covered by the GNU General Public License.
    4889
    +##
    4890
    +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
    4891
    +## at http://sources.redhat.com/ecos/ecos-license/
    4892
    +## -------------------------------------------
    4893
    +#####ECOSGPLCOPYRIGHTEND####
    4894
    +# ====================================================================
    4895
    +######DESCRIPTIONBEGIN####
    4896
    +#
    4897
    +# Author(s):      sfurman
    4898
    +# Contributors:   qaztronic
    4899
    +# Date:           02-06-2010
    4900
    +#
    4901
    +#####DESCRIPTIONEND####
    4902
    +#
    4903
    +# ====================================================================
    4904
    +
    4905
    +cdl_package CYGPKG_HAL_OPENRISC_OR1200_SOC {
    4906
    +    display  "OpenRISC Reference Platform"
    4907
    +    parent        CYGPKG_HAL_OPENRISC
    4908
    +    include_dir   cyg/hal
    4909
    +    hardware
    4910
    +    description   "
    4911
    +           The or1200_soc HAL package should be used when targetting the
    4912
    +           OpenRISC or1200_soc Platform."
    4913
    +
    4914
    +    compile       hal_diag.c hal_aux.c
    4915
    +
    4916
    +    implements    CYGINT_HAL_DEBUG_GDB_STUBS
    4917
    +    implements    CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
    4918
    +    implements    CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
    4919
    +    implements    CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
    4920
    +
    4921
    +    define_proc {
    4922
    +        puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   "
    4923
    +        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H "
    4924
    +    }
    4925
    +
    4926
    +    cdl_component CYG_HAL_STARTUP {
    4927
    +        display       "Startup type"
    4928
    +        flavor        data
    4929
    +        legal_values  {"RAM" "ROM"}
    4930
    +        default_value {"ROM"}
    4931
    +        no_define
    4932
    +        define -file system.h CYG_HAL_STARTUP
    4933
    +        description   "
    4934
    +            Selects whether code initially runs from ROM or RAM.  In the case of ROM startup,
    4935
    +            it's possible for the code to be copied into RAM and executed there."
    4936
    +    }
    4937
    +
    4938
    +    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
    4939
    +        display       "Diagnostic serial port baud rate"
    4940
    +        flavor        data
    4941
    +        legal_values  9600 19200 38400 57600 115200 230400 460800 921600
    4942
    +        default_value 115200
    4943
    +        description   "
    4944
    +            This option selects the baud rate used for the diagnostic console.
    4945
    +            Note: this should match the value chosen for the GDB port if the
    4946
    +            diagnostic and GDB port are the same.
    4947
    +            Note: very high baud rates are useful during simulation."
    4948
    +    }
    4949
    +
    4950
    +    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
    4951
    +        display       "GDB serial port baud rate"
    4952
    +        flavor        data
    4953
    +        legal_values  9600 19200 38400 57600 115200 230400 460800 921600
    4954
    +        default_value 115200
    4955
    +        description   "
    4956
    +            This option controls the baud rate used for the GDB connection.
    4957
    +            Note: very high baud rates are useful during simulation."
    4958
    +    }
    4959
    +
    4960
    +    # Real-time clock/counter specifics
    4961
    +    cdl_component CYGNUM_HAL_RTC_CONSTANTS {
    4962
    +        display       "Real-time clock constants."
    4963
    +        flavor        none
    4964
    +
    4965
    +        cdl_option CYGNUM_HAL_RTC_NUMERATOR {
    4966
    +            display       "Real-time clock numerator"
    4967
    +            flavor        data
    4968
    +            calculated    1000000000
    4969
    +        }
    4970
    +        cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
    4971
    +            display       "Real-time clock denominator"
    4972
    +            flavor        data
    4973
    +            calculated    100
    4974
    +        }
    4975
    +        cdl_option CYGNUM_HAL_RTC_PERIOD {
    4976
    +            display       "Real-time clock period"
    4977
    +            flavor        data
    4978
    +# sfurman: Probably ought be "calculated" - not "default_value"
    4979
    +# However, it is handy to override this value during simulator-based testing
    4980
    +            default_value {CYGHWR_HAL_OPENRISC_CPU_FREQ * 1000000 / CYGNUM_HAL_RTC_DENOMINATOR}
    4981
    +            description   "
    4982
    +                The tick timer facility is used
    4983
    +                to drive the eCos kernel RTC. The count register
    4984
    +                increments at the CPU clock speed.  By default, 100 Hz"
    4985
    +        }
    4986
    +    }
    4987
    +
    4988
    +    cdl_option CYGBLD_BUILD_GDB_STUBS {
    4989
    +        display "Build GDB stub ROM image"
    4990
    +        default_value 0
    4991
    +        parent CYGBLD_GLOBAL_OPTIONS
    4992
    +        requires { CYG_HAL_STARTUP == "ROM" }
    4993
    +        requires CYGSEM_HAL_ROM_MONITOR
    4994
    +        requires CYGBLD_BUILD_COMMON_GDB_STUBS
    4995
    +        requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
    4996
    +        requires ! CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
    4997
    +        requires ! CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
    4998
    +        requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
    4999
    +        requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
    5000
    +        no_define
    5001
    +        description "
    5002
    +                This option enables the building of the GDB stubs for the
    5003
    +                board. The common HAL controls takes care of most of the
    5004
    +                build process, but the final conversion from ELF image to
    5005
    +                binary data is handled by the platform CDL, allowing
    5006
    +                relocation of the data if necessary."
    5007
    +
    5008
    +        make -priority 320 {
    5009
    +            /bin/gdb_module.bin : /bin/gdb_module.img
    5010
    +            $(OBJCOPY) -O binary $< $@
    5011
    +        }
    5012
    +    }
    5013
    +
    5014
    +
    5015
    +    cdl_option CYGNUM_HAL_BREAKPOINT_LIST_SIZE {
    5016
    +        display       "Number of breakpoints supported by the HAL."
    5017
    +        flavor        data
    5018
    +        default_value 25
    5019
    +        description   "
    5020
    +            This option determines the number of breakpoints supported by the HAL."
    5021
    +    }
    5022
    +
    5023
    +    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
    5024
    +        display      "Number of communication channels on the board"
    5025
    +        flavor       data
    5026
    +        default_value  1
    5027
    +    }
    5028
    +
    5029
    +    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
    5030
    +        display          "Debug serial port"
    5031
    +        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
    5032
    +        flavor data
    5033
    +        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
    5034
    +        default_value    0
    5035
    +        description      "
    5036
    +           The or1200_soc platform has at least one serial port, but it can potentially have several.
    5037
    +           This option chooses which port will be used to connect to a host
    5038
    +           running GDB."
    5039
    +    }
    5040
    +
    5041
    +     cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
    5042
    +        display          "Diagnostic serial port"
    5043
    +        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
    5044
    +        flavor data
    5045
    +        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
    5046
    +        default_value    0
    5047
    +        description      "
    5048
    +           The or1200_soc platform has at least one serial port, but it can potentially have several.
    5049
    +           This option chooses which port will be used for diagnostic output."
    5050
    +     }
    5051
    +
    5052
    +    cdl_component CYGBLD_GLOBAL_OPTIONS {
    5053
    +        display "Global build options"
    5054
    +        flavor  none
    5055
    +        description   "
    5056
    +            Global build options including control over
    5057
    +            compiler flags, linker flags and choice of toolchain."
    5058
    +
    5059
    +
    5060
    +        parent  CYGPKG_NONE
    5061
    +
    5062
    +        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
    5063
    +            display "Global command prefix"
    5064
    +            flavor  data
    5065
    +            no_define
    5066
    +            default_value { "or32-elf" }
    5067
    +            description "
    5068
    +                This option specifies the command prefix used when
    5069
    +                invoking the build tools."
    5070
    +        }
    5071
    +
    5072
    +        cdl_option CYGBLD_GLOBAL_CFLAGS {
    5073
    +            display "Global compiler flags"
    5074
    +            flavor  data
    5075
    +            no_define
    5076
    +            default_value { "-msoft-float -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -fno-omit-frame-pointer -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
    5077
    +            description   "
    5078
    +                This option controls the global compiler flags which
    5079
    +                are used to compile all packages by
    5080
    +                default. Individual packages may define
    5081
    +                options which override these global flags."
    5082
    +        }
    5083
    +
    5084
    +        cdl_option CYGBLD_GLOBAL_LDFLAGS {
    5085
    +            display "Global linker flags"
    5086
    +            flavor  data
    5087
    +            no_define
    5088
    +            default_value { "-msoft-float -g -nostdlib -Wl,--gc-sections -Wl,-static" }
    5089
    +            description   "
    5090
    +                This option controls the global linker flags. Individual
    5091
    +                packages may define options which override these global flags."
    5092
    +        }
    5093
    +    }
    5094
    +
    5095
    +    cdl_component CYGHWR_MEMORY_LAYOUT {
    5096
    +        display "Memory layout"
    5097
    +        flavor data
    5098
    +        no_define
    5099
    +        calculated { CYG_HAL_STARTUP == "RAM" ? "openrisc_or1200_soc_ram" : \
    5100
    +                                                "openrisc_or1200_soc_rom" }
    5101
    +
    5102
    +        cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
    5103
    +            display "Memory layout linker script fragment"
    5104
    +            flavor data
    5105
    +            no_define
    5106
    +            define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
    5107
    +            calculated { CYG_HAL_STARTUP == "RAM" ? "" : \
    5108
    +                                                    "" }
    5109
    +        }
    5110
    +
    5111
    +        cdl_option CYGHWR_MEMORY_LAYOUT_H {
    5112
    +            display "Memory layout header file"
    5113
    +            flavor data
    5114
    +            no_define
    5115
    +            define -file system.h CYGHWR_MEMORY_LAYOUT_H
    5116
    +            calculated { CYG_HAL_STARTUP == "RAM" ? "" : \
    5117
    +                                                    "" }
    5118
    +        }
    5119
    +    }
    5120
    +
    5121
    +    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
    5122
    +        display       "Work with a ROM monitor"
    5123
    +        flavor        booldata
    5124
    +        legal_values  { "Generic" "CygMon" "GDB_stubs" }
    5125
    +        default_value { CYG_HAL_STARTUP == "RAM" ? "CygMon" : 0 }
    5126
    +        parent        CYGPKG_HAL_ROM_MONITOR
    5127
    +        requires      { CYG_HAL_STARTUP == "RAM" }
    5128
    +        description   "
    5129
    +            Support can be enabled for three different varieties of ROM monitor.
    5130
    +            This support changes various eCos semantics such as the encoding
    5131
    +            of diagnostic output, or the overriding of hardware interrupt
    5132
    +            vectors.
    5133
    +            Firstly there is \"Generic\" support which prevents the HAL
    5134
    +            from overriding the hardware vectors that it does not use, to
    5135
    +            instead allow an installed ROM monitor to handle them. This is
    5136
    +            the most basic support which is likely to be common to most
    5137
    +            implementations of ROM monitor.
    5138
    +            \"CygMon\" provides support for the Cygnus ROM Monitor.
    5139
    +            And finally, \"GDB_stubs\" provides support when GDB stubs are
    5140
    +            included in the ROM monitor or boot ROM."
    5141
    +    }
    5142
    +
    5143
    +    cdl_option CYGSEM_HAL_ROM_MONITOR {
    5144
    +        display       "Behave as a ROM monitor"
    5145
    +        flavor        bool
    5146
    +        default_value 1
    5147
    +        parent        CYGPKG_HAL_ROM_MONITOR
    5148
    +        requires      { CYG_HAL_STARTUP == "ROM" }
    5149
    +        description   "
    5150
    +            Enable this option if this program is to be used as a ROM monitor,
    5151
    +            i.e. applications will be loaded into RAM on the board, and this
    5152
    +            ROM monitor may process exceptions or interrupts generated from the
    5153
    +            application. This enables features such as utilizing a separate
    5154
    +            interrupt stack when exceptions are generated."
    5155
    +    }
    5156
    +
    5157
    +    cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
    5158
    +        display       "Redboot HAL options"
    5159
    +        flavor        none
    5160
    +        no_define
    5161
    +        parent        CYGPKG_REDBOOT
    5162
    +        active_if     CYGPKG_REDBOOT
    5163
    +        description   "
    5164
    +            This option lists the target's requirements for a valid Redboot
    5165
    +            configuration."
    5166
    +
    5167
    +        cdl_option CYGBLD_BUILD_REDBOOT_BIN {
    5168
    +            display       "Build Redboot ROM binary image"
    5169
    +            active_if     CYGBLD_BUILD_REDBOOT
    5170
    +            default_value 1
    5171
    +            no_define
    5172
    +            description "This option enables the conversion of the Redboot ELF
    5173
    +                         image to a binary image suitable for ROM programming."
    5174
    +
    5175
    +            compile -library=libextras.a redboot_cmds.c
    5176
    +
    5177
    +            make -priority 325 {
    5178
    +                /bin/redboot.srec : /bin/redboot.elf
    5179
    +                $(OBJCOPY) --strip-all $< $(@:.srec=.img)
    5180
    +                $(OBJCOPY) -O srec $< $@
    5181
    +            }
    5182
    +        }
    5183
    +    }
    5184
    +
    5185
    +    define_proc {
    5186
    +        puts $cdl_header "#define CYGHWR_HAL_VSR_TABLE    0"
    5187
    +        puts $cdl_header "#define CYGHWR_HAL_VIRTUAL_VECTOR_TABLE 0x30000000"
    5188
    +    }
    5189
    +}
    5190
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/doc/README.html ./ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/doc/README.html
    5191
    --- /opt/ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/doc/README.html 1969-12-31 16:00:00.000000000 -0800
    5192
    +++ ./ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/doc/README.html    2009-09-16 14:06:24.000000000 -0700
    5193
    @@ -0,0 +1,13 @@
    5194
    +
    5195
    +
    5196
    +
    5197
    +
    5198
    +  
    5199
    + content="1;URL="../../../arch/current/doc/README.html">
    5200
    +  README - eCos OpenRISC Port
    5201
    +
    5202
    +
    5203
    +
    5204
    + Redirecting to OpenRISC eCos README...
    5205
    +
    5206
    +
    5207
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/include/hal_diag.h ./ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/include/hal_diag.h
    5208
    --- /opt/ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/include/hal_diag.h      1969-12-31 16:00:00.000000000 -0800
    5209
    +++ ./ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/include/hal_diag.h 2009-09-16 14:06:24.000000000 -0700
    5210
    @@ -0,0 +1,69 @@
    5211
    +#ifndef CYGONCE_HAL_HAL_DIAG_H
    5212
    +#define CYGONCE_HAL_HAL_DIAG_H
    5213
    +
    5214
    +//=============================================================================
    5215
    +//
    5216
    +//      hal_diag.h
    5217
    +//
    5218
    +//      HAL Support for Kernel Diagnostic Routines
    5219
    +//
    5220
    +//=============================================================================
    5221
    +//####ECOSGPLCOPYRIGHTBEGIN####
    5222
    +// -------------------------------------------
    5223
    +// This file is part of eCos, the Embedded Configurable Operating System.
    5224
    +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
    5225
    +// Copyright (C) 2002 Gary Thomas
    5226
    +//
    5227
    +// eCos is free software; you can redistribute it and/or modify it under
    5228
    +// the terms of the GNU General Public License as published by the Free
    5229
    +// Software Foundation; either version 2 or (at your option) any later version.
    5230
    +//
    5231
    +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
    5232
    +// WARRANTY; without even the implied warranty of MERCHANTABILITY or
    5233
    +// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    5234
    +// for more details.
    5235
    +//
    5236
    +// You should have received a copy of the GNU General Public License along
    5237
    +// with eCos; if not, write to the Free Software Foundation, Inc.,
    5238
    +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
    5239
    +//
    5240
    +// As a special exception, if other files instantiate templates or use macros
    5241
    +// or inline functions from this file, or you compile this file and link it
    5242
    +// with other works to produce a work based on this file, this file does not
    5243
    +// by itself cause the resulting work to be covered by the GNU General Public
    5244
    +// License. However the source code for this file must still be made available
    5245
    +// in accordance with section (3) of the GNU General Public License.
    5246
    +//
    5247
    +// This exception does not invalidate any other reasons why a work based on
    5248
    +// this file might be covered by the GNU General Public License.
    5249
    +//
    5250
    +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
    5251
    +// at http://sources.redhat.com/ecos/ecos-license/
    5252
    +// -------------------------------------------
    5253
    +//####ECOSGPLCOPYRIGHTEND####
    5254
    +//=============================================================================
    5255
    +//#####DESCRIPTIONBEGIN####
    5256
    +//
    5257
    +// Author(s):   nickg
    5258
    +// Contributors:nickg
    5259
    +// Date:        2003-02-28
    5260
    +// Purpose:     HAL Support for Kernel Diagnostic Routines
    5261
    +// Description: Diagnostic routines for use during kernel development.
    5262
    +// Usage:       #include 
    5263
    +//
    5264
    +//####DESCRIPTIONEND####
    5265
    +//
    5266
    +//=============================================================================
    5267
    +
    5268
    +#include 
    5269
    +
    5270
    +#include 
    5271
    +#include 
    5272
    +
    5273
    +#define HAL_DIAG_INIT() hal_if_diag_init()
    5274
    +#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
    5275
    +#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_)
    5276
    +
    5277
    +//-----------------------------------------------------------------------------
    5278
    +// end of hal_diag.h
    5279
    +#endif // CYGONCE_HAL_HAL_DIAG_H
    5280
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/include/mc.h ./ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/include/mc.h
    5281
    --- /opt/ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/include/mc.h    1969-12-31 16:00:00.000000000 -0800
    5282
    +++ ./ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/include/mc.h       2009-09-16 14:06:24.000000000 -0700
    5283
    @@ -0,0 +1,143 @@
    5284
    +//==========================================================================
    5285
    +//
    5286
    +//      mc.h
    5287
    +//
    5288
    +//      OpenCores.org memory controller definitions
    5289
    +//
    5290
    +//==========================================================================
    5291
    +//####ECOSGPLCOPYRIGHTBEGIN####
    5292
    +// -------------------------------------------
    5293
    +// This file is part of eCos, the Embedded Configurable Operating System.
    5294
    +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
    5295
    +//
    5296
    +// eCos is free software; you can redistribute it and/or modify it under
    5297
    +// the terms of the GNU General Public License as published by the Free
    5298
    +// Software Foundation; either version 2 or (at your option) any later version.
    5299
    +//
    5300
    +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
    5301
    +// WARRANTY; without even the implied warranty of MERCHANTABILITY or
    5302
    +// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    5303
    +// for more details.
    5304
    +//
    5305
    +// You should have received a copy of the GNU General Public License along
    5306
    +// with eCos; if not, write to the Free Software Foundation, Inc.,
    5307
    +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
    5308
    +//
    5309
    +// As a special exception, if other files instantiate templates or use macros
    5310
    +// or inline functions from this file, or you compile this file and link it
    5311
    +// with other works to produce a work based on this file, this file does not
    5312
    +// by itself cause the resulting work to be covered by the GNU General Public
    5313
    +// License. However the source code for this file must still be made available
    5314
    +// in accordance with section (3) of the GNU General Public License.
    5315
    +//
    5316
    +// This exception does not invalidate any other reasons why a work based on
    5317
    +// this file might be covered by the GNU General Public License.
    5318
    +//
    5319
    +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
    5320
    +// at http://sources.redhat.com/ecos/ecos-license/
    5321
    +// -------------------------------------------
    5322
    +//####ECOSGPLCOPYRIGHTEND####
    5323
    +//==========================================================================
    5324
    +//#####DESCRIPTIONBEGIN####
    5325
    +//
    5326
    +// Author(s):    sfurman
    5327
    +// Contributors: Marko Mlinar
    5328
    +// Date:         2003-01-17
    5329
    +// Purpose:      Define OpenRISC architecture special-purpose registers
    5330
    +// Usage:        #include 
    5331
    +//
    5332
    +//####DESCRIPTIONEND####
    5333
    +//
    5334
    +//==========================================================================
    5335
    +
    5336
    +/* Prototypes */
    5337
    +#ifndef __MC_H
    5338
    +#define __MC_H
    5339
    +
    5340
    +#define N_CE        (8)
    5341
    +
    5342
    +#define MC_CSR      (0x00)
    5343
    +#define MC_POC      (0x04)
    5344
    +#define MC_BA_MASK  (0x08)
    5345
    +#define MC_CSC(i)   (0x10 + (i) * 8)
    5346
    +#define MC_TMS(i)   (0x14 + (i) * 8)
    5347
    +
    5348
    +#define MC_ADDR_SPACE (MC_CSC(N_CE))
    5349
    +
    5350
    +/* POC register field definition */
    5351
    +#define MC_POC_EN_BW_OFFSET     0
    5352
    +#define MC_POC_EN_BW_WIDTH      2
    5353
    +#define MC_POC_EN_MEMTYPE_OFFSET        2
    5354
    +#define MC_POC_EN_MEMTYPE_WIDTH 2
    5355
    +
    5356
    +/* CSC register field definition */
    5357
    +#define MC_CSC_EN_OFFSET        0
    5358
    +#define MC_CSC_MEMTYPE_OFFSET   1
    5359
    +#define MC_CSC_MEMTYPE_WIDTH    2
    5360
    +#define MC_CSC_BW_OFFSET        4
    5361
    +#define MC_CSC_BW_WIDTH         2
    5362
    +#define MC_CSC_MS_OFFSET        6
    5363
    +#define MC_CSC_MS_WIDTH         2
    5364
    +#define MC_CSC_WP_OFFSET        8
    5365
    +#define MC_CSC_BAS_OFFSET       9
    5366
    +#define MC_CSC_KRO_OFFSET       10
    5367
    +#define MC_CSC_PEN_OFFSET       11
    5368
    +#define MC_CSC_SEL_OFFSET       16
    5369
    +#define MC_CSC_SEL_WIDTH        8
    5370
    +
    5371
    +#define MC_CSC_MEMTYPE_SDRAM  0
    5372
    +#define MC_CSC_MEMTYPE_SSRAM  1
    5373
    +#define MC_CSC_MEMTYPE_ASYNC  2
    5374
    +#define MC_CSC_MEMTYPE_SYNC   3
    5375
    +
    5376
    +#define MC_CSR_VALID            0xFF000703LU
    5377
    +#define MC_POC_VALID            0x0000000FLU
    5378
    +#define MC_BA_MASK_VALID        0x000000FFLU
    5379
    +#define MC_CSC_VALID            0x00FF0FFFLU
    5380
    +#define MC_TMS_SDRAM_VALID      0x0FFF83FFLU
    5381
    +#define MC_TMS_SSRAM_VALID      0x00000000LU
    5382
    +#define MC_TMS_ASYNC_VALID      0x03FFFFFFLU
    5383
    +#define MC_TMS_SYNC_VALID       0x01FFFFFFLU
    5384
    +#define MC_TMS_VALID            0xFFFFFFFFLU /* reg test compat. */
    5385
    +
    5386
    +/* TMS register field definition SDRAM */
    5387
    +#define MC_TMS_SDRAM_TRFC_OFFSET        24
    5388
    +#define MC_TMS_SDRAM_TRFC_WIDTH         4
    5389
    +#define MC_TMS_SDRAM_TRP_OFFSET         20
    5390
    +#define MC_TMS_SDRAM_TRP_WIDTH          4
    5391
    +#define MC_TMS_SDRAM_TRCD_OFFSET        17
    5392
    +#define MC_TMS_SDRAM_TRCD_WIDTH         4
    5393
    +#define MC_TMS_SDRAM_TWR_OFFSET         15
    5394
    +#define MC_TMS_SDRAM_TWR_WIDTH          2
    5395
    +#define MC_TMS_SDRAM_WBL_OFFSET         9
    5396
    +#define MC_TMS_SDRAM_OM_OFFSET          7
    5397
    +#define MC_TMS_SDRAM_OM_WIDTH           2
    5398
    +#define MC_TMS_SDRAM_CL_OFFSET          4
    5399
    +#define MC_TMS_SDRAM_CL_WIDTH           3
    5400
    +#define MC_TMS_SDRAM_BT_OFFSET          3
    5401
    +#define MC_TMS_SDRAM_BL_OFFSET          0
    5402
    +#define MC_TMS_SDRAM_BL_WIDTH           3
    5403
    +
    5404
    +/* TMS register field definition ASYNC */
    5405
    +#define MC_TMS_ASYNC_TWWD_OFFSET        20
    5406
    +#define MC_TMS_ASYNC_TWWD_WIDTH         6
    5407
    +#define MC_TMS_ASYNC_TWD_OFFSET         16
    5408
    +#define MC_TMS_ASYNC_TWD_WIDTH          4
    5409
    +#define MC_TMS_ASYNC_TWPW_OFFSET        12
    5410
    +#define MC_TMS_ASYNC_TWPW_WIDTH         4
    5411
    +#define MC_TMS_ASYNC_TRDZ_OFFSET        8
    5412
    +#define MC_TMS_ASYNC_TRDZ_WIDTH         4
    5413
    +#define MC_TMS_ASYNC_TRDV_OFFSET        0
    5414
    +#define MC_TMS_ASYNC_TRDV_WIDTH         8
    5415
    +
    5416
    +/* TMS register field definition SYNC  */
    5417
    +#define MC_TMS_SYNC_TTO_OFFSET          16
    5418
    +#define MC_TMS_SYNC_TTO_WIDTH           9
    5419
    +#define MC_TMS_SYNC_TWR_OFFSET          12
    5420
    +#define MC_TMS_SYNC_TWR_WIDTH           4
    5421
    +#define MC_TMS_SYNC_TRDZ_OFFSET         8
    5422
    +#define MC_TMS_SYNC_TRDZ_WIDTH          4
    5423
    +#define MC_TMS_SYNC_TRDV_OFFSET         0
    5424
    +#define MC_TMS_SYNC_TRDV_WIDTH          8
    5425
    +
    5426
    +#endif
    5427
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/include/pkgconf/mlt_openrisc_or1200_soc_ram.h ./ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/include/pkgconf/mlt_openrisc_or1200_soc_ram.h
    5428
    --- /opt/ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/include/pkgconf/mlt_openrisc_or1200_soc_ram.h   1969-12-31 16:00:00.000000000 -0800
    5429
    +++ ./ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/include/pkgconf/mlt_openrisc_or1200_soc_ram.h      2010-02-09 10:06:21.870364800 -0800
    5430
    @@ -0,0 +1,37 @@
    5431
    +// eCos memory layout
    5432
    +
    5433
    +#ifndef __ASSEMBLER__
    5434
    +#include 
    5435
    +#include 
    5436
    +
    5437
    +#endif
    5438
    +#define CYGMEM_REGION_ram (0)
    5439
    +#define CYGMEM_REGION_ram_SIZE (0x00080000)
    5440
    +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
    5441
    +#define CYGMEM_REGION_rom (0x20000000)
    5442
    +#define CYGMEM_REGION_rom_SIZE (0x00400000)
    5443
    +#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
    5444
    +
    5445
    +#if 0
    5446
    +#ifndef __ASSEMBLER__
    5447
    +extern char CYG_LABEL_NAME (__reserved_vectors) [];
    5448
    +#endif
    5449
    +#define CYGMEM_SECTION_reserved_vectors (CYG_LABEL_NAME (__reserved_vectors))
    5450
    +#define CYGMEM_SECTION_reserved_vectors_SIZE (0x3000)
    5451
    +#ifndef __ASSEMBLER__
    5452
    +extern char CYG_LABEL_NAME (__reserved_vsr_table) [];
    5453
    +#endif
    5454
    +#define CYGMEM_SECTION_reserved_vsr_table (CYG_LABEL_NAME (__reserved_vsr_table))
    5455
    +#define CYGMEM_SECTION_reserved_vsr_table_SIZE (0x200)
    5456
    +#ifndef __ASSEMBLER__
    5457
    +extern char CYG_LABEL_NAME (__reserved_virtual_table) [];
    5458
    +#endif
    5459
    +#define CYGMEM_SECTION_reserved_virtual_table (CYG_LABEL_NAME (__reserved_virtual_table))
    5460
    +#define CYGMEM_SECTION_reserved_virtual_table_SIZE (0x100)
    5461
    +#endif
    5462
    +
    5463
    +#ifndef __ASSEMBLER__
    5464
    +extern char CYG_LABEL_NAME (__heap1) [];
    5465
    +#endif
    5466
    +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
    5467
    +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
    5468
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/include/pkgconf/mlt_openrisc_or1200_soc_ram.ldi ./ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/include/pkgconf/mlt_openrisc_or1200_soc_ram.ldi
    5469
    --- /opt/ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/include/pkgconf/mlt_openrisc_or1200_soc_ram.ldi 1969-12-31 16:00:00.000000000 -0800
    5470
    +++ ./ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/include/pkgconf/mlt_openrisc_or1200_soc_ram.ldi    2010-02-09 10:06:53.713503400 -0800
    5471
    @@ -0,0 +1,25 @@
    5472
    +// eCos memory layout
    5473
    +
    5474
    +#include 
    5475
    +
    5476
    +MEMORY
    5477
    +{
    5478
    +    ram : ORIGIN = 0x00000000, LENGTH = 0x00080000
    5479
    +    rom : ORIGIN = 0x20000000, LENGTH = 0x00400000
    5480
    +}
    5481
    +
    5482
    +SECTIONS
    5483
    +{
    5484
    +    SECTIONS_BEGIN
    5485
    +    SECTION_vectors (ram, 0x00000100, LMA_EQ_VMA)
    5486
    +    SECTION_text (ram, 0x00008000, LMA_EQ_VMA)
    5487
    +    SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA)
    5488
    +    SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
    5489
    +    SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA)
    5490
    +    SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA)
    5491
    +    SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA)
    5492
    +    SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
    5493
    +    SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA)
    5494
    +    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
    5495
    +    SECTIONS_END
    5496
    +}
    5497
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/include/pkgconf/mlt_openrisc_or1200_soc_rom.h ./ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/include/pkgconf/mlt_openrisc_or1200_soc_rom.h
    5498
    --- /opt/ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/include/pkgconf/mlt_openrisc_or1200_soc_rom.h   1969-12-31 16:00:00.000000000 -0800
    5499
    +++ ./ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/include/pkgconf/mlt_openrisc_or1200_soc_rom.h      2010-02-15 12:04:01.734170600 -0800
    5500
    @@ -0,0 +1,37 @@
    5501
    +// eCos memory layout
    5502
    +
    5503
    +#ifndef __ASSEMBLER__
    5504
    +#include 
    5505
    +#include 
    5506
    +
    5507
    +#endif
    5508
    +#define CYGMEM_REGION_ram (0x30000000)
    5509
    +#define CYGMEM_REGION_ram_SIZE (0x00080000)
    5510
    +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
    5511
    +#define CYGMEM_REGION_rom (0x20000000)
    5512
    +#define CYGMEM_REGION_rom_SIZE (0x00400000)
    5513
    +#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
    5514
    +
    5515
    +#if 0
    5516
    +#ifndef __ASSEMBLER__
    5517
    +extern char CYG_LABEL_NAME (__reserved_vectors) [];
    5518
    +#endif
    5519
    +#define CYGMEM_SECTION_reserved_vectors (CYG_LABEL_NAME (__reserved_vectors))
    5520
    +#define CYGMEM_SECTION_reserved_vectors_SIZE (0x3000)
    5521
    +#ifndef __ASSEMBLER__
    5522
    +extern char CYG_LABEL_NAME (__reserved_vsr_table) [];
    5523
    +#endif
    5524
    +#define CYGMEM_SECTION_reserved_vsr_table (CYG_LABEL_NAME (__reserved_vsr_table))
    5525
    +#define CYGMEM_SECTION_reserved_vsr_table_SIZE (0x200)
    5526
    +#ifndef __ASSEMBLER__
    5527
    +extern char CYG_LABEL_NAME (__reserved_virtual_table) [];
    5528
    +#endif
    5529
    +#define CYGMEM_SECTION_reserved_virtual_table (CYG_LABEL_NAME (__reserved_virtual_table))
    5530
    +#define CYGMEM_SECTION_reserved_virtual_table_SIZE (0x100)
    5531
    +#endif
    5532
    +
    5533
    +#ifndef __ASSEMBLER__
    5534
    +extern char CYG_LABEL_NAME (__heap1) [];
    5535
    +#endif
    5536
    +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
    5537
    +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram_SIZE - ((size_t) CYG_LABEL_NAME (__heap1) - CYGMEM_REGION_ram) )
    5538
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/include/pkgconf/mlt_openrisc_or1200_soc_rom.ldi ./ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/include/pkgconf/mlt_openrisc_or1200_soc_rom.ldi
    5539
    --- /opt/ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/include/pkgconf/mlt_openrisc_or1200_soc_rom.ldi 1969-12-31 16:00:00.000000000 -0800
    5540
    +++ ./ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/include/pkgconf/mlt_openrisc_or1200_soc_rom.ldi    2010-02-17 12:34:51.525537000 -0800
    5541
    @@ -0,0 +1,26 @@
    5542
    +// eCos memory layout
    5543
    +
    5544
    +#include 
    5545
    +
    5546
    +MEMORY
    5547
    +{
    5548
    +    ram         : ORIGIN = 0x00000000, LENGTH = 0x00080000
    5549
    +    rom         : ORIGIN = 0x20000000, LENGTH = 0x00400000
    5550
    +    mem_bank_3  : ORIGIN = 0x30000000, LENGTH = 0x00080000
    5551
    +}
    5552
    +
    5553
    +SECTIONS
    5554
    +{
    5555
    +    SECTIONS_BEGIN
    5556
    +    SECTION_vectors (rom, 0x20000000, LMA_EQ_VMA)
    5557
    +    SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA)
    5558
    +    SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
    5559
    +    SECTION_rodata1 (rom, ALIGN (0x8), LMA_EQ_VMA)
    5560
    +    SECTION_rodata (rom, ALIGN (0x8), LMA_EQ_VMA)
    5561
    +    SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
    5562
    +    SECTION_gcc_except_table (rom, ALIGN (0x1), LMA_EQ_VMA)
    5563
    +    SECTION_data (mem_bank_3, 0x30001000, FOLLOWING (.gcc_except_table))
    5564
    +    SECTION_bss (mem_bank_3, ALIGN (0x10), LMA_EQ_VMA)
    5565
    +    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
    5566
    +    SECTIONS_END
    5567
    +}
    5568
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/include/platform.inc ./ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/include/platform.inc
    5569
    --- /opt/ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/include/platform.inc    1969-12-31 16:00:00.000000000 -0800
    5570
    +++ ./ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/include/platform.inc       2010-02-09 17:21:33.758015400 -0800
    5571
    @@ -0,0 +1,124 @@
    5572
    +##==========================================================================
    5573
    +##
    5574
    +##      platform.inc
    5575
    +##
    5576
    +##      OpenRISC Reference Platform (ORP) board-specific defines
    5577
    +##
    5578
    +##==========================================================================
    5579
    +#####ECOSGPLCOPYRIGHTBEGIN####
    5580
    +## -------------------------------------------
    5581
    +## This file is part of eCos, the Embedded Configurable Operating System.
    5582
    +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
    5583
    +##
    5584
    +## eCos is free software; you can redistribute it and/or modify it under
    5585
    +## the terms of the GNU General Public License as published by the Free
    5586
    +## Software Foundation; either version 2 or (at your option) any later version.
    5587
    +##
    5588
    +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
    5589
    +## WARRANTY; without even the implied warranty of MERCHANTABILITY or
    5590
    +## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    5591
    +## for more details.
    5592
    +##
    5593
    +## You should have received a copy of the GNU General Public License along
    5594
    +## with eCos; if not, write to the Free Software Foundation, Inc.,
    5595
    +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
    5596
    +##
    5597
    +## As a special exception, if other files instantiate templates or use macros
    5598
    +## or inline functions from this file, or you compile this file and link it
    5599
    +## with other works to produce a work based on this file, this file does not
    5600
    +## by itself cause the resulting work to be covered by the GNU General Public
    5601
    +## License. However the source code for this file must still be made available
    5602
    +## in accordance with section (3) of the GNU General Public License.
    5603
    +##
    5604
    +## This exception does not invalidate any other reasons why a work based on
    5605
    +## this file might be covered by the GNU General Public License.
    5606
    +##
    5607
    +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
    5608
    +## at http://sources.redhat.com/ecos/ecos-license/
    5609
    +## -------------------------------------------
    5610
    +#####ECOSGPLCOPYRIGHTEND####
    5611
    +##==========================================================================
    5612
    +#######DESCRIPTIONBEGIN####
    5613
    +##
    5614
    +## Author(s):    sfurman
    5615
    +## Contributors: qaztronic
    5616
    +## Date:         2003-01-20
    5617
    +## Purpose:      ORP platform-specific init
    5618
    +## Description:  This file handles the post-reset hardware initialization
    5619
    +##               that is specific to the ORP platform (but not specific to
    5620
    +##               the OpenRISC processor itself).  So far, it only
    5621
    +##               initializes the memory controller so as to map Flash and
    5622
    +##               SDRAM into the memory space.
    5623
    +##
    5624
    +######DESCRIPTIONEND####
    5625
    +##
    5626
    +##==========================================================================
    5627
    +
    5628
    +#ifndef _PLATFORM_INC_
    5629
    +#define _PLATFORM_INC_
    5630
    +
    5631
    +#include 
    5632
    +#include CYGHWR_MEMORY_LAYOUT_H
    5633
    +
    5634
    +/* Memory organization */
    5635
    +#define SDRAM_BASE_ADD  CYGMEM_REGION_ram
    5636
    +#define FLASH_BASE_ADD  CYGMEM_REGION_rom
    5637
    +
    5638
    +/* Memory Controller's base address */
    5639
    +#define MC_BASE_ADD     0x93000000
    5640
    +
    5641
    +/* Memory controller initialize magic values */
    5642
    +#define MC_CSR_VAL      0x0B000300
    5643
    +#define MC_MASK_VAL     0x000003f0
    5644
    +#define FLASH_TMS_VAL   0x00000103
    5645
    +#define SDRAM_TMS_VAL   0x19220057
    5646
    +#define FLASH_CSC_VAL   (((FLASH_BASE_ADD>>6) & 0x07ff0000) | 0x0025)
    5647
    +#define SDRAM_CSC_VAL   (((SDRAM_BASE_ADD>>6) & 0x07ff0000) | 0x0411)
    5648
    +
    5649
    +
    5650
    +        # Platform-specific, post-reset hardware initialization
    5651
    +        .macro  hal_hardware_init
    5652
    +
    5653
    +init_func:
    5654
    +        # pause sim
    5655
    +        load32i r3,0x5ffffffc
    5656
    +        load32i r5,0xcea5e0ff
    5657
    +        l.sw    (0)(r3),r5
    5658
    +
    5659
    +# init_mc:
    5660
    +#         load32i r3,MC_BASE_ADD
    5661
    +
    5662
    +#         # Program Flash chip-select
    5663
    +#         load32i r5,FLASH_CSC_VAL
    5664
    +#         l.sw    MC_CSC(0)(r3),r5
    5665
    +
    5666
    +#         # Init flash timing
    5667
    +#         load32i r5,FLASH_TMS_VAL
    5668
    +#         l.sw    MC_TMS(0)(r3),r5
    5669
    +
    5670
    +#         # Start decoding memory addresses to generate chip-selects
    5671
    +#         l.addi  r5,r0,MC_MASK_VAL
    5672
    +#         l.sw    MC_BA_MASK(r3),r5
    5673
    +
    5674
    +#         load32i r5, MC_CSR_VAL
    5675
    +#         l.sw    MC_CSR(r3),r5
    5676
    +
    5677
    +#         # Init DRAM timing
    5678
    +#         load32i r5, SDRAM_TMS_VAL
    5679
    +#         l.sw    MC_TMS(1)(r3),r5
    5680
    +
    5681
    +#         # Program DRAM chip-select
    5682
    +#         load32i r5, SDRAM_CSC_VAL
    5683
    +#         l.sw    MC_CSC(1)(r3),r5
    5684
    +
    5685
    +#         # Wait for SDRAM
    5686
    +#         l.addi  r3,r0,0x1000
    5687
    +# 1:      l.sfeqi r3,0
    5688
    +#         l.bnf   1b
    5689
    +#         l.addi  r3,r3,-1
    5690
    +
    5691
    +        .endm
    5692
    +
    5693
    +#endif /* ifndef _PLATFORM_INC_ */
    5694
    +
    5695
    +#undef CYGIMP_FORCE_INTERRUPT_HANDLING_CODE_IN_RAM
    5696
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/include/plf_intr.h ./ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/include/plf_intr.h
    5697
    --- /opt/ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/include/plf_intr.h      1969-12-31 16:00:00.000000000 -0800
    5698
    +++ ./ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/include/plf_intr.h 2009-09-16 14:06:24.000000000 -0700
    5699
    @@ -0,0 +1,80 @@
    5700
    +#ifndef CYGONCE_HAL_PLF_INTR_H
    5701
    +#define CYGONCE_HAL_PLF_INTR_H
    5702
    +
    5703
    +//==========================================================================
    5704
    +//
    5705
    +//      plf_intr.h
    5706
    +//
    5707
    +//      OpenRISC ORP platform-specific interrupt definitions
    5708
    +//
    5709
    +//==========================================================================
    5710
    +//####ECOSGPLCOPYRIGHTBEGIN####
    5711
    +// -------------------------------------------
    5712
    +// This file is part of eCos, the Embedded Configurable Operating System.
    5713
    +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
    5714
    +// Copyright (C) 2002 Gary Thomas
    5715
    +//
    5716
    +// eCos is free software; you can redistribute it and/or modify it under
    5717
    +// the terms of the GNU General Public License as published by the Free
    5718
    +// Software Foundation; either version 2 or (at your option) any later version.
    5719
    +//
    5720
    +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
    5721
    +// WARRANTY; without even the implied warranty of MERCHANTABILITY or
    5722
    +// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    5723
    +// for more details.
    5724
    +//
    5725
    +// You should have received a copy of the GNU General Public License along
    5726
    +// with eCos; if not, write to the Free Software Foundation, Inc.,
    5727
    +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
    5728
    +//
    5729
    +// As a special exception, if other files instantiate templates or use macros
    5730
    +// or inline functions from this file, or you compile this file and link it
    5731
    +// with other works to produce a work based on this file, this file does not
    5732
    +// by itself cause the resulting work to be covered by the GNU General Public
    5733
    +// License. However the source code for this file must still be made available
    5734
    +// in accordance with section (3) of the GNU General Public License.
    5735
    +//
    5736
    +// This exception does not invalidate any other reasons why a work based on
    5737
    +// this file might be covered by the GNU General Public License.
    5738
    +//
    5739
    +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
    5740
    +// at http://sources.redhat.com/ecos/ecos-license/
    5741
    +// -------------------------------------------
    5742
    +//####ECOSGPLCOPYRIGHTEND####
    5743
    +//==========================================================================
    5744
    +//#####DESCRIPTIONBEGIN####
    5745
    +//
    5746
    +// Author(s):    sfurman
    5747
    +// Contributors:
    5748
    +// Date:         2002-02-28
    5749
    +// Purpose:      Define platform specific interrupt support
    5750
    +//
    5751
    +// Usage:
    5752
    +//              #include 
    5753
    +//              ...
    5754
    +//
    5755
    +//
    5756
    +//####DESCRIPTIONEND####
    5757
    +//
    5758
    +//==========================================================================
    5759
    +
    5760
    +
    5761
    +//----------------------------------------------------------------------------
    5762
    +// Reset.
    5763
    +
    5764
    +// This function should perform a hardware reset
    5765
    +// For now, it does nothing.
    5766
    +#define HAL_PLATFORM_RESET() CYG_EMPTY_STATEMENT
    5767
    +
    5768
    +// If no HW reset exists, jump to this location instead.
    5769
    +// The current value is the ROM reset entry point.
    5770
    +#define HAL_PLATFORM_RESET_ENTRY 0xF0001000
    5771
    +
    5772
    +// Define PIC interrupt numbers for peripherals
    5773
    +#define CYGNUM_HAL_INTERRUPT_SERIAL_CONSOLE    CYGNUM_HAL_INTERRUPT_2
    5774
    +#define CYGNUM_HAL_INTERRUPT_SERIAL_DEBUGGER   CYGNUM_HAL_INTERRUPT_3
    5775
    +
    5776
    +
    5777
    +//--------------------------------------------------------------------------
    5778
    +#endif // ifndef CYGONCE_HAL_PLF_INTR_H
    5779
    +// End of plf_intr.h
    5780
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/include/plf_stub.h ./ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/include/plf_stub.h
    5781
    --- /opt/ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/include/plf_stub.h      1969-12-31 16:00:00.000000000 -0800
    5782
    +++ ./ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/include/plf_stub.h 2010-02-05 17:08:20.269461800 -0800
    5783
    @@ -0,0 +1,69 @@
    5784
    +//=============================================================================
    5785
    +//
    5786
    +//      plf_stub.h
    5787
    +//
    5788
    +//      Platform header for GDB stub support.
    5789
    +//
    5790
    +//=============================================================================
    5791
    +//####ECOSGPLCOPYRIGHTBEGIN####
    5792
    +// -------------------------------------------
    5793
    +// This file is part of eCos, the Embedded Configurable Operating System.
    5794
    +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
    5795
    +//
    5796
    +// eCos is free software; you can redistribute it and/or modify it under
    5797
    +// the terms of the GNU General Public License as published by the Free
    5798
    +// Software Foundation; either version 2 or (at your option) any later version.
    5799
    +//
    5800
    +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
    5801
    +// WARRANTY; without even the implied warranty of MERCHANTABILITY or
    5802
    +// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    5803
    +// for more details.
    5804
    +//
    5805
    +// You should have received a copy of the GNU General Public License along
    5806
    +// with eCos; if not, write to the Free Software Foundation, Inc.,
    5807
    +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
    5808
    +//
    5809
    +// As a special exception, if other files instantiate templates or use macros
    5810
    +// or inline functions from this file, or you compile this file and link it
    5811
    +// with other works to produce a work based on this file, this file does not
    5812
    +// by itself cause the resulting work to be covered by the GNU General Public
    5813
    +// License. However the source code for this file must still be made available
    5814
    +// in accordance with section (3) of the GNU General Public License.
    5815
    +//
    5816
    +// This exception does not invalidate any other reasons why a work based on
    5817
    +// this file might be covered by the GNU General Public License.
    5818
    +//
    5819
    +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
    5820
    +// at http://sources.redhat.com/ecos/ecos-license/
    5821
    +// -------------------------------------------
    5822
    +//####ECOSGPLCOPYRIGHTEND####
    5823
    +//=============================================================================
    5824
    +//#####DESCRIPTIONBEGIN####
    5825
    +//
    5826
    +// Author(s):   sfurman
    5827
    +// Contributors:jskov
    5828
    +// Date:        2003-02-28
    5829
    +// Purpose:     Platform HAL stub support for PowerPC/VIPER board.
    5830
    +// Usage:       #include 
    5831
    +//
    5832
    +//####DESCRIPTIONEND####
    5833
    +//
    5834
    +//=============================================================================
    5835
    +
    5836
    +#ifndef CYGONCE_HAL_PLF_STUB_H
    5837
    +#define CYGONCE_HAL_PLF_STUB_H
    5838
    +
    5839
    +#include 
    5840
    +
    5841
    +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
    5842
    +
    5843
    +#include          // CYG_UNUSED_PARAM
    5844
    +#include 
    5845
    +
    5846
    +//----------------------------------------------------------------------------
    5847
    +// Stub initializer.
    5848
    +
    5849
    +#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
    5850
    +//-----------------------------------------------------------------------------
    5851
    +#endif // CYGONCE_HAL_PLF_STUB_H
    5852
    +// End of plf_stub.h
    5853
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/src/hal_aux.c ./ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/src/hal_aux.c
    5854
    --- /opt/ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/src/hal_aux.c   1969-12-31 16:00:00.000000000 -0800
    5855
    +++ ./ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/src/hal_aux.c      2010-02-09 17:15:23.343252500 -0800
    5856
    @@ -0,0 +1,72 @@
    5857
    +//=============================================================================
    5858
    +//
    5859
    +//      hal_aux.c
    5860
    +//
    5861
    +//      HAL auxiliary objects and code; per platform
    5862
    +//
    5863
    +//=============================================================================
    5864
    +//####ECOSGPLCOPYRIGHTBEGIN####
    5865
    +// -------------------------------------------
    5866
    +// This file is part of eCos, the Embedded Configurable Operating System.
    5867
    +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
    5868
    +// Copyright (C) 2002 Gary Thomas
    5869
    +//
    5870
    +// eCos is free software; you can redistribute it and/or modify it under
    5871
    +// the terms of the GNU General Public License as published by the Free
    5872
    +// Software Foundation; either version 2 or (at your option) any later version.
    5873
    +//
    5874
    +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
    5875
    +// WARRANTY; without even the implied warranty of MERCHANTABILITY or
    5876
    +// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    5877
    +// for more details.
    5878
    +//
    5879
    +// You should have received a copy of the GNU General Public License along
    5880
    +// with eCos; if not, write to the Free Software Foundation, Inc.,
    5881
    +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
    5882
    +//
    5883
    +// As a special exception, if other files instantiate templates or use macros
    5884
    +// or inline functions from this file, or you compile this file and link it
    5885
    +// with other works to produce a work based on this file, this file does not
    5886
    +// by itself cause the resulting work to be covered by the GNU General Public
    5887
    +// License. However the source code for this file must still be made available
    5888
    +// in accordance with section (3) of the GNU General Public License.
    5889
    +//
    5890
    +// This exception does not invalidate any other reasons why a work based on
    5891
    +// this file might be covered by the GNU General Public License.
    5892
    +//
    5893
    +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
    5894
    +// at http://sources.redhat.com/ecos/ecos-license/
    5895
    +// -------------------------------------------
    5896
    +//####ECOSGPLCOPYRIGHTEND####
    5897
    +//=============================================================================
    5898
    +//#####DESCRIPTIONBEGIN####
    5899
    +//
    5900
    +// Author(s):   hmt
    5901
    +// Contributors:hmt
    5902
    +// Date:        2003-02-28
    5903
    +// Purpose:     HAL aux objects: startup tables.
    5904
    +// Description: Tables for per-platform initialization
    5905
    +//
    5906
    +//####DESCRIPTIONEND####
    5907
    +//
    5908
    +//=============================================================================
    5909
    +
    5910
    +#include 
    5911
    +
    5912
    +//--------------------------------------------------------------------------
    5913
    +// Platform init code.
    5914
    +void
    5915
    +hal_platform_init(void)
    5916
    +{
    5917
    +    // Basic hardware initialization has already taken place
    5918
    +
    5919
    +       *((volatile unsigned int *)(0x5ffffffc)) = 0xcea5e0ff;
    5920
    +
    5921
    +    hal_if_init();   // Initialize logical I/O layer (virtual vector support)
    5922
    +
    5923
    +       *((volatile unsigned int *)(0x5ffffffc)) = 0xcea5e0ff;
    5924
    +
    5925
    +}
    5926
    +
    5927
    +// EOF hal_aux.c
    5928
    +
    5929
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/src/hal_diag.c ./ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/src/hal_diag.c
    5930
    --- /opt/ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/src/hal_diag.c  1969-12-31 16:00:00.000000000 -0800
    5931
    +++ ./ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/src/hal_diag.c     2010-02-09 16:59:00.002758000 -0800
    5932
    @@ -0,0 +1,589 @@
    5933
    +//=============================================================================
    5934
    +//
    5935
    +//      hal_diag.c
    5936
    +//
    5937
    +//      Simple polling driver for the 16c550c serial controller(s) in the ORP,
    5938
    +//      to be used for diagnostic I/O and gdb remote debugging.
    5939
    +//
    5940
    +//=============================================================================
    5941
    +//####ECOSGPLCOPYRIGHTBEGIN####
    5942
    +// -------------------------------------------
    5943
    +// This file is part of eCos, the Embedded Configurable Operating System.
    5944
    +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
    5945
    +//
    5946
    +// eCos is free software; you can redistribute it and/or modify it under
    5947
    +// the terms of the GNU General Public License as published by the Free
    5948
    +// Software Foundation; either version 2 or (at your option) any later version.
    5949
    +//
    5950
    +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
    5951
    +// WARRANTY; without even the implied warranty of MERCHANTABILITY or
    5952
    +// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    5953
    +// for more details.
    5954
    +//
    5955
    +// You should have received a copy of the GNU General Public License along
    5956
    +// with eCos; if not, write to the Free Software Foundation, Inc.,
    5957
    +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
    5958
    +//
    5959
    +// As a special exception, if other files instantiate templates or use macros
    5960
    +// or inline functions from this file, or you compile this file and link it
    5961
    +// with other works to produce a work based on this file, this file does not
    5962
    +// by itself cause the resulting work to be covered by the GNU General Public
    5963
    +// License. However the source code for this file must still be made available
    5964
    +// in accordance with section (3) of the GNU General Public License.
    5965
    +//
    5966
    +// This exception does not invalidate any other reasons why a work based on
    5967
    +// this file might be covered by the GNU General Public License.
    5968
    +//
    5969
    +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
    5970
    +// at http://sources.redhat.com/ecos/ecos-license/
    5971
    +// -------------------------------------------
    5972
    +//####ECOSGPLCOPYRIGHTEND####
    5973
    +//=============================================================================
    5974
    +//#####DESCRIPTIONBEGIN####
    5975
    +//
    5976
    +// Author(s):   sfurman
    5977
    +// Contributors:dmoseley
    5978
    +// Date:        2003-02-28
    5979
    +// Description: Simple polling driver for the 16c550c serial controller(s) in the ORP,
    5980
    +//              to be used for diagnostic I/O and gdb remote debugging.
    5981
    +//
    5982
    +//
    5983
    +//####DESCRIPTIONEND####
    5984
    +//
    5985
    +//=============================================================================
    5986
    +
    5987
    +#include 
    5988
    +#include 
    5989
    +#include CYGBLD_HAL_PLATFORM_H
    5990
    +
    5991
    +#include            // SAVE/RESTORE GP macros
    5992
    +#include              // IO macros
    5993
    +#include              // interface API
    5994
    +#include            // HAL_ENABLE/MASK/UNMASK_INTERRUPTS
    5995
    +#include            // Helper functions
    5996
    +#include             // CYG_ISR_HANDLED
    5997
    +#include           // assertion macros
    5998
    +
    5999
    +//-----------------------------------------------------------------------------
    6000
    +// Base addresses for each 16550 UART in the system
    6001
    +#define SERIAL_16550_CONSOLE_BASE_ADDR    0x50000000
    6002
    +
    6003
    +//-----------------------------------------------------------------------------
    6004
    +// Define the 16550C serial registers.
    6005
    +#define SER_16550_RBR 0x00   // receiver buffer register, read, dlab = 0
    6006
    +#define SER_16550_THR 0x00   // transmitter holding register, write, dlab = 0
    6007
    +#define SER_16550_DLL 0x00   // divisor latch (LS), read/write, dlab = 1
    6008
    +#define SER_16550_IER 0x01   // interrupt enable register, read/write, dlab = 0
    6009
    +#define SER_16550_DLM 0x01   // divisor latch (MS), read/write, dlab = 1
    6010
    +#define SER_16550_IIR 0x02   // interrupt identification reg, read, dlab = 0
    6011
    +#define SER_16550_FCR 0x02   // fifo control register, write, dlab = 0
    6012
    +#define SER_16550_AFR 0x02   // alternate function reg, read/write, dlab = 1
    6013
    +#define SER_16550_LCR 0x03   // line control register, read/write
    6014
    +#define SER_16550_MCR 0x04   // modem control register, read/write
    6015
    +#define SER_16550_LSR 0x05   // line status register, read
    6016
    +#define SER_16550_MSR 0x06   // modem status register, read
    6017
    +#define SER_16550_SCR 0x07   // scratch pad register
    6018
    +
    6019
    +// The interrupt enable register bits.
    6020
    +#define SIO_IER_ERDAI   0x01            // enable received data available irq
    6021
    +#define SIO_IER_ETHREI  0x02            // enable THR empty interrupt
    6022
    +#define SIO_IER_ELSI    0x04            // enable receiver line status irq
    6023
    +#define SIO_IER_EMSI    0x08            // enable modem status interrupt
    6024
    +
    6025
    +// The interrupt identification register bits.
    6026
    +#define SIO_IIR_IP      0x01            // 0 if interrupt pending
    6027
    +#define SIO_IIR_ID_MASK 0x0e            // mask for interrupt ID bits
    6028
    +
    6029
    +// The line status register bits.
    6030
    +#define SIO_LSR_DR      0x01            // data ready
    6031
    +#define SIO_LSR_OE      0x02            // overrun error
    6032
    +#define SIO_LSR_PE      0x04            // parity error
    6033
    +#define SIO_LSR_FE      0x08            // framing error
    6034
    +#define SIO_LSR_BI      0x10            // break interrupt
    6035
    +#define SIO_LSR_THRE    0x20            // transmitter holding register empty
    6036
    +#define SIO_LSR_TEMT    0x40            // transmitter register empty
    6037
    +#define SIO_LSR_ERR     0x80            // any error condition
    6038
    +
    6039
    +// The modem status register bits.
    6040
    +#define SIO_MSR_DCTS  0x01              // delta clear to send
    6041
    +#define SIO_MSR_DDSR  0x02              // delta data set ready
    6042
    +#define SIO_MSR_TERI  0x04              // trailing edge ring indicator
    6043
    +#define SIO_MSR_DDCD  0x08              // delta data carrier detect
    6044
    +#define SIO_MSR_CTS   0x10              // clear to send
    6045
    +#define SIO_MSR_DSR   0x20              // data set ready
    6046
    +#define SIO_MSR_RI    0x40              // ring indicator
    6047
    +#define SIO_MSR_DCD   0x80              // data carrier detect
    6048
    +
    6049
    +// The line control register bits.
    6050
    +#define SIO_LCR_WLS0   0x01             // word length select bit 0
    6051
    +#define SIO_LCR_WLS1   0x02             // word length select bit 1
    6052
    +#define SIO_LCR_STB    0x04             // number of stop bits
    6053
    +#define SIO_LCR_PEN    0x08             // parity enable
    6054
    +#define SIO_LCR_EPS    0x10             // even parity select
    6055
    +#define SIO_LCR_SP     0x20             // stick parity
    6056
    +#define SIO_LCR_SB     0x40             // set break
    6057
    +#define SIO_LCR_DLAB   0x80             // divisor latch access bit
    6058
    +
    6059
    +// The FIFO control register
    6060
    +#define SIO_FCR_FCR0   0x01             // enable xmit and rcvr fifos
    6061
    +#define SIO_FCR_FCR1   0x02             // clear RCVR FIFO
    6062
    +#define SIO_FCR_FCR2   0x04             // clear XMIT FIFO
    6063
    +
    6064
    +/////////////////////////////////////////
    6065
    +// Interrupt Enable Register
    6066
    +#define IER_RCV 0x01
    6067
    +#define IER_XMT 0x02
    6068
    +#define IER_LS  0x04
    6069
    +#define IER_MS  0x08
    6070
    +
    6071
    +// Line Control Register
    6072
    +#define LCR_WL5 0x00    // Word length
    6073
    +#define LCR_WL6 0x01
    6074
    +#define LCR_WL7 0x02
    6075
    +#define LCR_WL8 0x03
    6076
    +#define LCR_SB1 0x00    // Number of stop bits
    6077
    +#define LCR_SB1_5 0x04  // 1.5 -> only valid with 5 bit words
    6078
    +#define LCR_SB2 0x04
    6079
    +#define LCR_PN  0x00    // Parity mode - none
    6080
    +#define LCR_PE  0x0C    // Parity mode - even
    6081
    +#define LCR_PO  0x08    // Parity mode - odd
    6082
    +#define LCR_PM  0x28    // Forced "mark" parity
    6083
    +#define LCR_PS  0x38    // Forced "space" parity
    6084
    +#define LCR_DL  0x80    // Enable baud rate latch
    6085
    +
    6086
    +// Line Status Register
    6087
    +#define LSR_RSR 0x01
    6088
    +#define LSR_THE 0x20
    6089
    +
    6090
    +// Modem Control Register
    6091
    +#define MCR_DTR 0x01
    6092
    +#define MCR_RTS 0x02
    6093
    +#define MCR_INT 0x08   // Enable interrupts
    6094
    +
    6095
    +// Interrupt status register
    6096
    +#define ISR_None             0x01
    6097
    +#define ISR_Rx_Line_Status   0x06
    6098
    +#define ISR_Rx_Avail         0x04
    6099
    +#define ISR_Rx_Char_Timeout  0x0C
    6100
    +#define ISR_Tx_Empty         0x02
    6101
    +#define ISR_Modem_Status     0x00
    6102
    +
    6103
    +// FIFO control register
    6104
    +#define FCR_ENABLE     0x01
    6105
    +#define FCR_CLEAR_RCVR 0x02
    6106
    +#define FCR_CLEAR_XMIT 0x04
    6107
    +
    6108
    +// Assume the UART is driven 1/16 CPU frequency
    6109
    +#define UART_CLOCK    ((CYGHWR_HAL_OPENRISC_CPU_FREQ)*1.0e6/16.0)
    6110
    +
    6111
    +#define DIVISOR(baud) ((int)((UART_CLOCK)/baud))
    6112
    +
    6113
    +#ifdef CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD
    6114
    +#define CYG_DEV_SERIAL_BAUD_DIVISOR   \
    6115
    +    DIVISOR(CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD)
    6116
    +#else
    6117
    +#error Missing/incorrect serial baud rate defined - CDL error?
    6118
    +#endif
    6119
    +
    6120
    +
    6121
    +//-----------------------------------------------------------------------------
    6122
    +typedef struct {
    6123
    +    cyg_uint8* base;
    6124
    +    cyg_int32 msec_timeout;
    6125
    +    int isr_vector;
    6126
    +} channel_data_t;
    6127
    +
    6128
    +static channel_data_t channels[] = {
    6129
    +    { (cyg_uint8*)SERIAL_16550_CONSOLE_BASE_ADDR,
    6130
    +      1000,
    6131
    +      CYGNUM_HAL_INTERRUPT_SERIAL_CONSOLE
    6132
    +    }
    6133
    +};
    6134
    +
    6135
    +//-----------------------------------------------------------------------------
    6136
    +// Set the baud rate
    6137
    +
    6138
    +static void
    6139
    +cyg_hal_plf_serial_set_baud(cyg_uint8* port, cyg_uint16 baud_divisor)
    6140
    +{
    6141
    +    cyg_uint8 _lcr;
    6142
    +
    6143
    +    HAL_READ_UINT8(port+SER_16550_LCR, _lcr);
    6144
    +    _lcr |= LCR_DL;
    6145
    +    HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr);
    6146
    +
    6147
    +    HAL_WRITE_UINT8(port+SER_16550_DLM, baud_divisor >> 8);
    6148
    +    HAL_WRITE_UINT8(port+SER_16550_DLL, baud_divisor & 0xff);
    6149
    +
    6150
    +    _lcr &= ~LCR_DL;
    6151
    +    HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr);
    6152
    +}
    6153
    +
    6154
    +//-----------------------------------------------------------------------------
    6155
    +// The minimal init, get and put functions. All by polling.
    6156
    +
    6157
    +void
    6158
    +cyg_hal_plf_serial_init_channel(void* __ch_data)
    6159
    +{
    6160
    +    cyg_uint8* port;
    6161
    +    cyg_uint8 _lcr;
    6162
    +
    6163
    +    // Some of the diagnostic print code calls through here with no idea what the ch_data is.
    6164
    +    // Go ahead and assume it is channels[0].
    6165
    +    if (__ch_data == 0)
    6166
    +      __ch_data = (void*)&channels[0];
    6167
    +
    6168
    +    port = ((channel_data_t*)__ch_data)->base;
    6169
    +
    6170
    +    // Disable port interrupts while changing hardware
    6171
    +    HAL_WRITE_UINT8(port+SER_16550_IER, 0);
    6172
    +
    6173
    +    // Set databits, stopbits and parity.
    6174
    +    _lcr = LCR_WL8 | LCR_SB1 | LCR_PN;
    6175
    +    HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr);
    6176
    +
    6177
    +    // Set baud rate.
    6178
    +    cyg_hal_plf_serial_set_baud(port, CYG_DEV_SERIAL_BAUD_DIVISOR);
    6179
    +
    6180
    +    // Enable and clear FIFO
    6181
    +    HAL_WRITE_UINT8(port+SER_16550_FCR, (FCR_ENABLE | FCR_CLEAR_RCVR | FCR_CLEAR_XMIT));
    6182
    +
    6183
    +    // enable RTS to keep host side happy
    6184
    +    HAL_WRITE_UINT8( port+SER_16550_MCR, MCR_RTS );
    6185
    +
    6186
    +    // Don't allow interrupts.
    6187
    +    HAL_WRITE_UINT8(port+SER_16550_IER, 0);
    6188
    +}
    6189
    +
    6190
    +void
    6191
    +cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 __ch)
    6192
    +{
    6193
    +    cyg_uint8* port;
    6194
    +    cyg_uint8 _lsr;
    6195
    +
    6196
    +    // Some of the diagnostic print code calls through here with no idea what the ch_data is.
    6197
    +    // Go ahead and assume it is channels[0].
    6198
    +    if (__ch_data == 0)
    6199
    +      __ch_data = (void*)&channels[0];
    6200
    +
    6201
    +    port = ((channel_data_t*)__ch_data)->base;
    6202
    +
    6203
    +    CYGARC_HAL_SAVE_GP();
    6204
    +
    6205
    +    do {
    6206
    +        HAL_READ_UINT8(port+SER_16550_LSR, _lsr);
    6207
    +    } while ((_lsr & SIO_LSR_THRE) == 0);
    6208
    +
    6209
    +    // Now, the transmit buffer is empty
    6210
    +    HAL_WRITE_UINT8(port+SER_16550_THR, __ch);
    6211
    +
    6212
    +    // Hang around until the character has been safely sent.
    6213
    +    do {
    6214
    +        HAL_READ_UINT8(port+SER_16550_LSR, _lsr);
    6215
    +    } while ((_lsr & SIO_LSR_THRE) == 0);
    6216
    +
    6217
    +    CYGARC_HAL_RESTORE_GP();
    6218
    +}
    6219
    +
    6220
    +static int lsr_global;
    6221
    +
    6222
    +static cyg_bool
    6223
    +cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
    6224
    +{
    6225
    +    cyg_uint8* port;
    6226
    +    cyg_uint8 _lsr;
    6227
    +
    6228
    +    // Some of the diagnostic print code calls through here with no idea what the ch_data is.
    6229
    +    // Go ahead and assume it is channels[0].
    6230
    +    if (__ch_data == 0)
    6231
    +      __ch_data = (void*)&channels[0];
    6232
    +
    6233
    +    port = ((channel_data_t*)__ch_data)->base;
    6234
    +
    6235
    +    HAL_READ_UINT8(port+SER_16550_LSR, _lsr);
    6236
    +    if ((_lsr & SIO_LSR_DR) == 0)
    6237
    +        return false;
    6238
    +    lsr_global = _lsr;
    6239
    +    CYG_ASSERT((_lsr & SIO_LSR_OE) == 0 , "UART receiver overrun error");
    6240
    +    HAL_READ_UINT8(port+SER_16550_RBR, *ch);
    6241
    +
    6242
    +    return true;
    6243
    +}
    6244
    +
    6245
    +cyg_uint8
    6246
    +cyg_hal_plf_serial_getc(void* __ch_data)
    6247
    +{
    6248
    +    cyg_uint8 ch;
    6249
    +    CYGARC_HAL_SAVE_GP();
    6250
    +
    6251
    +    // Some of the diagnostic print code calls through here with no idea what the ch_data is.
    6252
    +    // Go ahead and assume it is channels[0].
    6253
    +    if (__ch_data == 0)
    6254
    +      __ch_data = (void*)&channels[0];
    6255
    +
    6256
    +    while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
    6257
    +
    6258
    +    CYGARC_HAL_RESTORE_GP();
    6259
    +    return ch;
    6260
    +}
    6261
    +
    6262
    +static void
    6263
    +cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
    6264
    +                         cyg_uint32 __len)
    6265
    +{
    6266
    +    CYGARC_HAL_SAVE_GP();
    6267
    +
    6268
    +    // Some of the diagnostic print code calls through here with no idea what the ch_data is.
    6269
    +    // Go ahead and assume it is channels[0].
    6270
    +    if (__ch_data == 0)
    6271
    +      __ch_data = (void*)&channels[0];
    6272
    +
    6273
    +    while(__len-- > 0)
    6274
    +        cyg_hal_plf_serial_putc(__ch_data, *__buf++);
    6275
    +
    6276
    +    CYGARC_HAL_RESTORE_GP();
    6277
    +}
    6278
    +
    6279
    +static void
    6280
    +cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
    6281
    +{
    6282
    +    CYGARC_HAL_SAVE_GP();
    6283
    +
    6284
    +    // Some of the diagnostic print code calls through here with no idea what the ch_data is.
    6285
    +    // Go ahead and assume it is channels[0].
    6286
    +    if (__ch_data == 0)
    6287
    +      __ch_data = (void*)&channels[0];
    6288
    +
    6289
    +    while(__len-- > 0)
    6290
    +        *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
    6291
    +
    6292
    +    CYGARC_HAL_RESTORE_GP();
    6293
    +}
    6294
    +
    6295
    +
    6296
    +cyg_bool
    6297
    +cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
    6298
    +{
    6299
    +    int delay_count;
    6300
    +    channel_data_t* chan;
    6301
    +    cyg_bool res;
    6302
    +    CYGARC_HAL_SAVE_GP();
    6303
    +
    6304
    +    // Some of the diagnostic print code calls through here with no idea what the ch_data is.
    6305
    +    // Go ahead and assume it is channels[0].
    6306
    +    if (__ch_data == 0)
    6307
    +      __ch_data = (void*)&channels[0];
    6308
    +
    6309
    +    chan = (channel_data_t*)__ch_data;
    6310
    +
    6311
    +    delay_count = chan->msec_timeout; // delay in 1000 us steps
    6312
    +
    6313
    +    for(;;) {
    6314
    +        res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
    6315
    +        if (res || 0 == delay_count--)
    6316
    +            break;
    6317
    +        CYGACC_CALL_IF_DELAY_US(1000);
    6318
    +    }
    6319
    +
    6320
    +    CYGARC_HAL_RESTORE_GP();
    6321
    +    return res;
    6322
    +}
    6323
    +
    6324
    +static int
    6325
    +cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
    6326
    +{
    6327
    +    static int irq_state = 0;
    6328
    +    channel_data_t* chan;
    6329
    +    cyg_uint8 ier;
    6330
    +    int ret = 0;
    6331
    +    CYGARC_HAL_SAVE_GP();
    6332
    +
    6333
    +    // Some of the diagnostic print code calls through here with no idea what the ch_data is.
    6334
    +    // Go ahead and assume it is channels[0].
    6335
    +    if (__ch_data == 0)
    6336
    +      __ch_data = (void*)&channels[0];
    6337
    +
    6338
    +    chan = (channel_data_t*)__ch_data;
    6339
    +
    6340
    +    switch (__func) {
    6341
    +    case __COMMCTL_IRQ_ENABLE:
    6342
    +        irq_state = 1;
    6343
    +
    6344
    +        HAL_READ_UINT8(chan->base + SER_16550_IER, ier);
    6345
    +        ier |= SIO_IER_ERDAI;
    6346
    +        HAL_WRITE_UINT8(chan->base + SER_16550_IER, ier);
    6347
    +
    6348
    +        HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1);
    6349
    +        HAL_INTERRUPT_UNMASK(chan->isr_vector);
    6350
    +        break;
    6351
    +    case __COMMCTL_IRQ_DISABLE:
    6352
    +        ret = irq_state;
    6353
    +        irq_state = 0;
    6354
    +
    6355
    +        HAL_READ_UINT8(chan->base + SER_16550_IER, ier);
    6356
    +        ier &= ~SIO_IER_ERDAI;
    6357
    +        HAL_WRITE_UINT8(chan->base + SER_16550_IER, ier);
    6358
    +
    6359
    +        HAL_INTERRUPT_MASK(chan->isr_vector);
    6360
    +        break;
    6361
    +    case __COMMCTL_DBG_ISR_VECTOR:
    6362
    +        ret = chan->isr_vector;
    6363
    +        break;
    6364
    +    case __COMMCTL_SET_TIMEOUT:
    6365
    +    {
    6366
    +        va_list ap;
    6367
    +
    6368
    +        va_start(ap, __func);
    6369
    +
    6370
    +        ret = chan->msec_timeout;
    6371
    +        chan->msec_timeout = va_arg(ap, cyg_uint32);
    6372
    +
    6373
    +        va_end(ap);
    6374
    +    }
    6375
    +    break;
    6376
    +    case __COMMCTL_SETBAUD:
    6377
    +    {
    6378
    +        cyg_uint32 baud_rate;
    6379
    +        cyg_uint16 baud_divisor;
    6380
    +        cyg_uint8* port = chan->base;
    6381
    +        va_list ap;
    6382
    +
    6383
    +        va_start(ap, __func);
    6384
    +        baud_rate = va_arg(ap, cyg_uint32);
    6385
    +        va_end(ap);
    6386
    +
    6387
    +        switch (baud_rate)
    6388
    +        {
    6389
    +        case 110:    baud_divisor = DIVISOR(110);    break;
    6390
    +        case 150:    baud_divisor = DIVISOR(150);    break;
    6391
    +        case 300:    baud_divisor = DIVISOR(300);    break;
    6392
    +        case 600:    baud_divisor = DIVISOR(600);    break;
    6393
    +        case 1200:   baud_divisor = DIVISOR(1200);   break;
    6394
    +        case 2400:   baud_divisor = DIVISOR(2400);   break;
    6395
    +        case 4800:   baud_divisor = DIVISOR(4800);   break;
    6396
    +        case 7200:   baud_divisor = DIVISOR(7200);   break;
    6397
    +        case 9600:   baud_divisor = DIVISOR(9600);   break;
    6398
    +        case 14400:  baud_divisor = DIVISOR(14400);  break;
    6399
    +        case 19200:  baud_divisor = DIVISOR(19200);  break;
    6400
    +        case 38400:  baud_divisor = DIVISOR(38400);  break;
    6401
    +        case 57600:  baud_divisor = DIVISOR(57600);  break;
    6402
    +        case 115200: baud_divisor = DIVISOR(115200); break;
    6403
    +        case 230400: baud_divisor = DIVISOR(230400); break;
    6404
    +        default:     return -1;                      break; // Invalid baud rate selected
    6405
    +        }
    6406
    +
    6407
    +        // Disable port interrupts while changing hardware
    6408
    +        HAL_READ_UINT8(port+SER_16550_IER, ier);
    6409
    +        HAL_WRITE_UINT8(port+SER_16550_IER, 0);
    6410
    +
    6411
    +        // Set baud rate.
    6412
    +        cyg_hal_plf_serial_set_baud(port, baud_divisor);
    6413
    +
    6414
    +        // Reenable interrupts if necessary
    6415
    +        HAL_WRITE_UINT8(port+SER_16550_IER, ier);
    6416
    +    }
    6417
    +    break;
    6418
    +
    6419
    +    case __COMMCTL_GETBAUD:
    6420
    +        break;
    6421
    +    default:
    6422
    +        break;
    6423
    +    }
    6424
    +    CYGARC_HAL_RESTORE_GP();
    6425
    +    return ret;
    6426
    +}
    6427
    +
    6428
    +static int
    6429
    +cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
    6430
    +                       CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
    6431
    +{
    6432
    +    int res = 0;
    6433
    +    cyg_uint8 _iir, c;
    6434
    +    channel_data_t* chan;
    6435
    +    CYGARC_HAL_SAVE_GP();
    6436
    +
    6437
    +    // Some of the diagnostic print code calls through here with no idea what the ch_data is.
    6438
    +    // Go ahead and assume it is channels[0].
    6439
    +    if (__ch_data == 0)
    6440
    +      __ch_data = (void*)&channels[0];
    6441
    +
    6442
    +    chan = (channel_data_t*)__ch_data;
    6443
    +
    6444
    +    HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
    6445
    +
    6446
    +    HAL_READ_UINT8(chan->base + SER_16550_IIR, _iir);
    6447
    +    _iir &= SIO_IIR_ID_MASK;
    6448
    +
    6449
    +    *__ctrlc = 0;
    6450
    +    if ((_iir == ISR_Rx_Avail) || (_iir == ISR_Rx_Char_Timeout)) {
    6451
    +
    6452
    +        HAL_READ_UINT8(chan->base + SER_16550_RBR, c);
    6453
    +
    6454
    +        if( cyg_hal_is_break( &c , 1 ) )
    6455
    +            *__ctrlc = 1;
    6456
    +
    6457
    +        res = CYG_ISR_HANDLED;
    6458
    +    }
    6459
    +
    6460
    +    /* sfurman - Hmmm.  Under or1ksim, we sometimes receive interrupts
    6461
    +       when no characters are in the FIFO.  I think this is a SW bug
    6462
    +       and not a problem w/ or1ksim, but until the problem is solved,
    6463
    +       we always consume the interrupt */
    6464
    +    res = CYG_ISR_HANDLED;
    6465
    +
    6466
    +    CYGARC_HAL_RESTORE_GP();
    6467
    +    return res;
    6468
    +}
    6469
    +
    6470
    +static void
    6471
    +cyg_hal_plf_serial_init(void)
    6472
    +{
    6473
    +    int i;
    6474
    +    hal_virtual_comm_table_t* comm;
    6475
    +    int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
    6476
    +
    6477
    +    //#define NUM_CHANNELS (sizeof(channels)/sizeof(channels[0]))
    6478
    +#define NUM_CHANNELS CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS
    6479
    +    for (i = 0; i < NUM_CHANNELS; i++) {
    6480
    +
    6481
    +    // Disable interrupts.
    6482
    +    HAL_INTERRUPT_MASK(channels[i].isr_vector);
    6483
    +
    6484
    +    // Init channels
    6485
    +    cyg_hal_plf_serial_init_channel((void*)&channels[i]);
    6486
    +
    6487
    +    // Setup procs in the vector table
    6488
    +
    6489
    +    // Set COMM callbacks for channel
    6490
    +    CYGACC_CALL_IF_SET_CONSOLE_COMM(i);
    6491
    +    comm = CYGACC_CALL_IF_CONSOLE_PROCS();
    6492
    +    CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]);
    6493
    +    CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
    6494
    +    CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
    6495
    +    CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
    6496
    +    CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
    6497
    +    CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
    6498
    +    CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
    6499
    +    CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
    6500
    +    }
    6501
    +
    6502
    +    // Restore original console
    6503
    +    CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
    6504
    +}
    6505
    +
    6506
    +void
    6507
    +cyg_hal_plf_comms_init(void)
    6508
    +{
    6509
    +    static int initialized = 0;
    6510
    +
    6511
    +    if (initialized)
    6512
    +        return;
    6513
    +
    6514
    +    initialized = 1;
    6515
    +
    6516
    +    cyg_hal_plf_serial_init();
    6517
    +}
    6518
    +
    6519
    +//-----------------------------------------------------------------------------
    6520
    +// end of ser16c550c.c
    6521
    +
    6522
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/src/redboot_cmds.c ./ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/src/redboot_cmds.c
    6523
    --- /opt/ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/src/redboot_cmds.c      1969-12-31 16:00:00.000000000 -0800
    6524
    +++ ./ecos-3.0/packages/hal/openrisc/or1200_soc/v3_0/src/redboot_cmds.c 2010-02-17 11:05:35.234723400 -0800
    6525
    @@ -0,0 +1,73 @@
    6526
    +//==========================================================================
    6527
    +//
    6528
    +//      redboot_cmds.c
    6529
    +//
    6530
    +//      custom redboot commands
    6531
    +//
    6532
    +//==========================================================================
    6533
    +// ####ECOSGPLCOPYRIGHTBEGIN####
    6534
    +// -------------------------------------------
    6535
    +// This file is part of eCos, the Embedded Configurable Operating System.
    6536
    +// Copyright (C) 2004 Free Software Foundation, Inc.
    6537
    +//
    6538
    +// eCos is free software; you can redistribute it and/or modify it under
    6539
    +// the terms of the GNU General Public License as published by the Free
    6540
    +// Software Foundation; either version 2 or (at your option) any later
    6541
    +// version.
    6542
    +//
    6543
    +// eCos is distributed in the hope that it will be useful, but WITHOUT
    6544
    +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
    6545
    +// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    6546
    +// for more details.
    6547
    +//
    6548
    +// You should have received a copy of the GNU General Public License
    6549
    +// along with eCos; if not, write to the Free Software Foundation, Inc.,
    6550
    +// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
    6551
    +//
    6552
    +// As a special exception, if other files instantiate templates or use
    6553
    +// macros or inline functions from this file, or you compile this file
    6554
    +// and link it with other works to produce a work based on this file,
    6555
    +// this file does not by itself cause the resulting work to be covered by
    6556
    +// the GNU General Public License. However the source code for this file
    6557
    +// must still be made available in accordance with section (3) of the GNU
    6558
    +// General Public License v2.
    6559
    +//
    6560
    +// This exception does not invalidate any other reasons why a work based
    6561
    +// on this file might be covered by the GNU General Public License.
    6562
    +// -------------------------------------------
    6563
    +// ####ECOSGPLCOPYRIGHTEND####
    6564
    +//==========================================================================
    6565
    +//#####DESCRIPTIONBEGIN####
    6566
    +//
    6567
    +// Author(s):
    6568
    +// Contributors:
    6569
    +// Date:
    6570
    +// Purpose:
    6571
    +// Description:
    6572
    +//
    6573
    +// This code is part of RedBoot (tm).
    6574
    +//
    6575
    +//####DESCRIPTIONEND####
    6576
    +//
    6577
    +//==========================================================================
    6578
    +
    6579
    +
    6580
    +#include 
    6581
    +#include 
    6582
    +
    6583
    +// CLI functions
    6584
    +static void do_test_led(int argc, char *argv[]);
    6585
    +RedBoot_cmd ( "test_led",
    6586
    +              "Test the leds.",
    6587
    +              " ",
    6588
    +              do_test_led
    6589
    +             );
    6590
    +
    6591
    +static void
    6592
    +do_test_led(int argc, char *argv[])
    6593
    +{
    6594
    +
    6595
    +       *((volatile unsigned int *)(0x60000014)) = 0xffffffff;
    6596
    +       *((volatile unsigned int *)(0x60000008)) = 0xffffffff;
    6597
    +
    6598
    +}
    6599
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/orp/v3_0/ChangeLog ./ecos-3.0/packages/hal/openrisc/orp/v3_0/ChangeLog
    6600
    --- /opt/ecos-3.0/packages/hal/openrisc/orp/v3_0/ChangeLog      1969-12-31 16:00:00.000000000 -0800
    6601
    +++ ./ecos-3.0/packages/hal/openrisc/orp/v3_0/ChangeLog 2009-09-16 14:06:24.000000000 -0700
    6602
    @@ -0,0 +1,39 @@
    6603
    +2003-03-06  Scott Furman 
    6604
    +
    6605
    +        Initial port of eCos to OpenRISC Reference Platform (ORP)
    6606
    +
    6607
    +//===========================================================================
    6608
    +//####ECOSGPLCOPYRIGHTBEGIN####
    6609
    +// -------------------------------------------
    6610
    +// This file is part of eCos, the Embedded Configurable Operating System.
    6611
    +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
    6612
    +// Copyright (C) 2002 Gary Thomas
    6613
    +//
    6614
    +// eCos is free software; you can redistribute it and/or modify it under
    6615
    +// the terms of the GNU General Public License as published by the Free
    6616
    +// Software Foundation; either version 2 or (at your option) any later version.
    6617
    +//
    6618
    +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
    6619
    +// WARRANTY; without even the implied warranty of MERCHANTABILITY or
    6620
    +// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    6621
    +// for more details.
    6622
    +//
    6623
    +// You should have received a copy of the GNU General Public License along
    6624
    +// with eCos; if not, write to the Free Software Foundation, Inc.,
    6625
    +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
    6626
    +//
    6627
    +// As a special exception, if other files instantiate templates or use macros
    6628
    +// or inline functions from this file, or you compile this file and link it
    6629
    +// with other works to produce a work based on this file, this file does not
    6630
    +// by itself cause the resulting work to be covered by the GNU General Public
    6631
    +// License. However the source code for this file must still be made available
    6632
    +// in accordance with section (3) of the GNU General Public License.
    6633
    +//
    6634
    +// This exception does not invalidate any other reasons why a work based on
    6635
    +// this file might be covered by the GNU General Public License.
    6636
    +//
    6637
    +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
    6638
    +// at http://sources.redhat.com/ecos/ecos-license/
    6639
    +// -------------------------------------------
    6640
    +//####ECOSGPLCOPYRIGHTEND####
    6641
    +//===========================================================================
    6642
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/orp/v3_0/cdl/hal_openrisc_orp.cdl ./ecos-3.0/packages/hal/openrisc/orp/v3_0/cdl/hal_openrisc_orp.cdl
    6643
    --- /opt/ecos-3.0/packages/hal/openrisc/orp/v3_0/cdl/hal_openrisc_orp.cdl       1969-12-31 16:00:00.000000000 -0800
    6644
    +++ ./ecos-3.0/packages/hal/openrisc/orp/v3_0/cdl/hal_openrisc_orp.cdl  2009-09-16 14:06:24.000000000 -0700
    6645
    @@ -0,0 +1,335 @@
    6646
    +# ====================================================================
    6647
    +#
    6648
    +#      hal_openrisc_orp.cdl
    6649
    +#
    6650
    +#      OpenRISC Reference Platform (ORP) HAL package configuration data
    6651
    +#
    6652
    +# ====================================================================
    6653
    +#####ECOSGPLCOPYRIGHTBEGIN####
    6654
    +## -------------------------------------------
    6655
    +## This file is part of eCos, the Embedded Configurable Operating System.
    6656
    +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
    6657
    +##
    6658
    +## eCos is free software; you can redistribute it and/or modify it under
    6659
    +## the terms of the GNU General Public License as published by the Free
    6660
    +## Software Foundation; either version 2 or (at your option) any later version.
    6661
    +##
    6662
    +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
    6663
    +## WARRANTY; without even the implied warranty of MERCHANTABILITY or
    6664
    +## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    6665
    +## for more details.
    6666
    +##
    6667
    +## You should have received a copy of the GNU General Public License along
    6668
    +## with eCos; if not, write to the Free Software Foundation, Inc.,
    6669
    +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
    6670
    +##
    6671
    +## As a special exception, if other files instantiate templates or use macros
    6672
    +## or inline functions from this file, or you compile this file and link it
    6673
    +## with other works to produce a work based on this file, this file does not
    6674
    +## by itself cause the resulting work to be covered by the GNU General Public
    6675
    +## License. However the source code for this file must still be made available
    6676
    +## in accordance with section (3) of the GNU General Public License.
    6677
    +##
    6678
    +## This exception does not invalidate any other reasons why a work based on
    6679
    +## this file might be covered by the GNU General Public License.
    6680
    +##
    6681
    +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
    6682
    +## at http://sources.redhat.com/ecos/ecos-license/
    6683
    +## -------------------------------------------
    6684
    +#####ECOSGPLCOPYRIGHTEND####
    6685
    +# ====================================================================
    6686
    +######DESCRIPTIONBEGIN####
    6687
    +#
    6688
    +# Author(s):      sfurman
    6689
    +# Contributors:
    6690
    +# Date:           2003-01-20
    6691
    +#
    6692
    +#####DESCRIPTIONEND####
    6693
    +#
    6694
    +# ====================================================================
    6695
    +
    6696
    +cdl_package CYGPKG_HAL_OPENRISC_ORP {
    6697
    +    display  "OpenRISC Reference Platform"
    6698
    +    parent        CYGPKG_HAL_OPENRISC
    6699
    +    include_dir   cyg/hal
    6700
    +    hardware
    6701
    +    description   "
    6702
    +           The ORP HAL package should be used when targetting the
    6703
    +           OpenRISC Reference Platform."
    6704
    +
    6705
    +    compile       hal_diag.c hal_aux.c
    6706
    +
    6707
    +    implements    CYGINT_HAL_DEBUG_GDB_STUBS
    6708
    +    implements    CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
    6709
    +    implements    CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
    6710
    +    implements    CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
    6711
    +
    6712
    +    define_proc {
    6713
    +        puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   "
    6714
    +        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H "
    6715
    +    }
    6716
    +
    6717
    +    cdl_component CYG_HAL_STARTUP {
    6718
    +        display       "Startup type"
    6719
    +        flavor        data
    6720
    +        legal_values  {"RAM" "ROM"}
    6721
    +        default_value {"ROM"}
    6722
    +        no_define
    6723
    +        define -file system.h CYG_HAL_STARTUP
    6724
    +        description   "
    6725
    +            Selects whether code initially runs from ROM or RAM.  In the case of ROM startup,
    6726
    +            it's possible for the code to be copied into RAM and executed there."
    6727
    +    }
    6728
    +
    6729
    +    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
    6730
    +        display       "Diagnostic serial port baud rate"
    6731
    +        flavor        data
    6732
    +        legal_values  9600 19200 38400 57600 115200 230400 460800 921600
    6733
    +        default_value 115200
    6734
    +        description   "
    6735
    +            This option selects the baud rate used for the diagnostic console.
    6736
    +            Note: this should match the value chosen for the GDB port if the
    6737
    +            diagnostic and GDB port are the same.
    6738
    +            Note: very high baud rates are useful during simulation."
    6739
    +    }
    6740
    +
    6741
    +    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
    6742
    +        display       "GDB serial port baud rate"
    6743
    +        flavor        data
    6744
    +        legal_values  9600 19200 38400 57600 115200 230400 460800 921600
    6745
    +        default_value 115200
    6746
    +        description   "
    6747
    +            This option controls the baud rate used for the GDB connection.
    6748
    +            Note: very high baud rates are useful during simulation."
    6749
    +    }
    6750
    +
    6751
    +    # Real-time clock/counter specifics
    6752
    +    cdl_component CYGNUM_HAL_RTC_CONSTANTS {
    6753
    +        display       "Real-time clock constants."
    6754
    +        flavor        none
    6755
    +
    6756
    +        cdl_option CYGNUM_HAL_RTC_NUMERATOR {
    6757
    +            display       "Real-time clock numerator"
    6758
    +            flavor        data
    6759
    +            calculated    1000000000
    6760
    +        }
    6761
    +        cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
    6762
    +            display       "Real-time clock denominator"
    6763
    +            flavor        data
    6764
    +            calculated    100
    6765
    +        }
    6766
    +        cdl_option CYGNUM_HAL_RTC_PERIOD {
    6767
    +            display       "Real-time clock period"
    6768
    +            flavor        data
    6769
    +# sfurman: Probably ought be "calculated" - not "default_value"
    6770
    +# However, it is handy to override this value during simulator-based testing
    6771
    +            default_value {CYGHWR_HAL_OPENRISC_CPU_FREQ * 1000000 / CYGNUM_HAL_RTC_DENOMINATOR}
    6772
    +            description   "
    6773
    +                The tick timer facility is used
    6774
    +                to drive the eCos kernel RTC. The count register
    6775
    +                increments at the CPU clock speed.  By default, 100 Hz"
    6776
    +        }
    6777
    +    }
    6778
    +
    6779
    +    cdl_option CYGBLD_BUILD_GDB_STUBS {
    6780
    +        display "Build GDB stub ROM image"
    6781
    +        default_value 0
    6782
    +        parent CYGBLD_GLOBAL_OPTIONS
    6783
    +        requires { CYG_HAL_STARTUP == "ROM" }
    6784
    +        requires CYGSEM_HAL_ROM_MONITOR
    6785
    +        requires CYGBLD_BUILD_COMMON_GDB_STUBS
    6786
    +        requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
    6787
    +        requires ! CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
    6788
    +        requires ! CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
    6789
    +        requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
    6790
    +        requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
    6791
    +        no_define
    6792
    +        description "
    6793
    +                This option enables the building of the GDB stubs for the
    6794
    +                board. The common HAL controls takes care of most of the
    6795
    +                build process, but the final conversion from ELF image to
    6796
    +                binary data is handled by the platform CDL, allowing
    6797
    +                relocation of the data if necessary."
    6798
    +
    6799
    +        make -priority 320 {
    6800
    +            /bin/gdb_module.bin : /bin/gdb_module.img
    6801
    +            $(OBJCOPY) -O binary $< $@
    6802
    +        }
    6803
    +    }
    6804
    +
    6805
    +
    6806
    +    cdl_option CYGNUM_HAL_BREAKPOINT_LIST_SIZE {
    6807
    +        display       "Number of breakpoints supported by the HAL."
    6808
    +        flavor        data
    6809
    +        default_value 25
    6810
    +        description   "
    6811
    +            This option determines the number of breakpoints supported by the HAL."
    6812
    +    }
    6813
    +
    6814
    +    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
    6815
    +        display      "Number of communication channels on the board"
    6816
    +        flavor       data
    6817
    +        default_value  1
    6818
    +    }
    6819
    +
    6820
    +    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
    6821
    +        display          "Debug serial port"
    6822
    +        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
    6823
    +        flavor data
    6824
    +        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
    6825
    +        default_value    0
    6826
    +        description      "
    6827
    +           The ORP platform has at least one serial port, but it can potentially have several.
    6828
    +           This option chooses which port will be used to connect to a host
    6829
    +           running GDB."
    6830
    +    }
    6831
    +
    6832
    +     cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
    6833
    +        display          "Diagnostic serial port"
    6834
    +        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
    6835
    +        flavor data
    6836
    +        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
    6837
    +        default_value    0
    6838
    +        description      "
    6839
    +           The ORP platform has at least one serial port, but it can potentially have several.
    6840
    +           This option chooses which port will be used for diagnostic output."
    6841
    +     }
    6842
    +
    6843
    +    cdl_component CYGBLD_GLOBAL_OPTIONS {
    6844
    +        display "Global build options"
    6845
    +        flavor  none
    6846
    +        description   "
    6847
    +            Global build options including control over
    6848
    +            compiler flags, linker flags and choice of toolchain."
    6849
    +
    6850
    +
    6851
    +        parent  CYGPKG_NONE
    6852
    +
    6853
    +        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
    6854
    +            display "Global command prefix"
    6855
    +            flavor  data
    6856
    +            no_define
    6857
    +            default_value { "or32-elf" }
    6858
    +            description "
    6859
    +                This option specifies the command prefix used when
    6860
    +                invoking the build tools."
    6861
    +        }
    6862
    +
    6863
    +        cdl_option CYGBLD_GLOBAL_CFLAGS {
    6864
    +            display "Global compiler flags"
    6865
    +            flavor  data
    6866
    +            no_define
    6867
    +            default_value { "-msoft-float -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -fno-omit-frame-pointer -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
    6868
    +            description   "
    6869
    +                This option controls the global compiler flags which
    6870
    +                are used to compile all packages by
    6871
    +                default. Individual packages may define
    6872
    +                options which override these global flags."
    6873
    +        }
    6874
    +
    6875
    +        cdl_option CYGBLD_GLOBAL_LDFLAGS {
    6876
    +            display "Global linker flags"
    6877
    +            flavor  data
    6878
    +            no_define
    6879
    +            default_value { "-msoft-float -g -nostdlib -Wl,--gc-sections -Wl,-static" }
    6880
    +            description   "
    6881
    +                This option controls the global linker flags. Individual
    6882
    +                packages may define options which override these global flags."
    6883
    +        }
    6884
    +    }
    6885
    +
    6886
    +    cdl_component CYGHWR_MEMORY_LAYOUT {
    6887
    +        display "Memory layout"
    6888
    +        flavor data
    6889
    +        no_define
    6890
    +        calculated { CYG_HAL_STARTUP == "RAM" ? "openrisc_orp_ram" : \
    6891
    +                                                "openrisc_orp_rom" }
    6892
    +
    6893
    +        cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
    6894
    +            display "Memory layout linker script fragment"
    6895
    +            flavor data
    6896
    +            no_define
    6897
    +            define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
    6898
    +            calculated { CYG_HAL_STARTUP == "RAM" ? "" : \
    6899
    +                                                    "" }
    6900
    +        }
    6901
    +
    6902
    +        cdl_option CYGHWR_MEMORY_LAYOUT_H {
    6903
    +            display "Memory layout header file"
    6904
    +            flavor data
    6905
    +            no_define
    6906
    +            define -file system.h CYGHWR_MEMORY_LAYOUT_H
    6907
    +            calculated { CYG_HAL_STARTUP == "RAM" ? "" : \
    6908
    +                                                    "" }
    6909
    +        }
    6910
    +    }
    6911
    +
    6912
    +    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
    6913
    +        display       "Work with a ROM monitor"
    6914
    +        flavor        booldata
    6915
    +        legal_values  { "Generic" "CygMon" "GDB_stubs" }
    6916
    +        default_value { CYG_HAL_STARTUP == "RAM" ? "CygMon" : 0 }
    6917
    +        parent        CYGPKG_HAL_ROM_MONITOR
    6918
    +        requires      { CYG_HAL_STARTUP == "RAM" }
    6919
    +        description   "
    6920
    +            Support can be enabled for three different varieties of ROM monitor.
    6921
    +            This support changes various eCos semantics such as the encoding
    6922
    +            of diagnostic output, or the overriding of hardware interrupt
    6923
    +            vectors.
    6924
    +            Firstly there is \"Generic\" support which prevents the HAL
    6925
    +            from overriding the hardware vectors that it does not use, to
    6926
    +            instead allow an installed ROM monitor to handle them. This is
    6927
    +            the most basic support which is likely to be common to most
    6928
    +            implementations of ROM monitor.
    6929
    +            \"CygMon\" provides support for the Cygnus ROM Monitor.
    6930
    +            And finally, \"GDB_stubs\" provides support when GDB stubs are
    6931
    +            included in the ROM monitor or boot ROM."
    6932
    +    }
    6933
    +
    6934
    +    cdl_option CYGSEM_HAL_ROM_MONITOR {
    6935
    +        display       "Behave as a ROM monitor"
    6936
    +        flavor        bool
    6937
    +        default_value 1
    6938
    +        parent        CYGPKG_HAL_ROM_MONITOR
    6939
    +        requires      { CYG_HAL_STARTUP == "ROM" }
    6940
    +        description   "
    6941
    +            Enable this option if this program is to be used as a ROM monitor,
    6942
    +            i.e. applications will be loaded into RAM on the board, and this
    6943
    +            ROM monitor may process exceptions or interrupts generated from the
    6944
    +            application. This enables features such as utilizing a separate
    6945
    +            interrupt stack when exceptions are generated."
    6946
    +    }
    6947
    +
    6948
    +    cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
    6949
    +        display       "Redboot HAL options"
    6950
    +        flavor        none
    6951
    +        no_define
    6952
    +        parent        CYGPKG_REDBOOT
    6953
    +        active_if     CYGPKG_REDBOOT
    6954
    +        description   "
    6955
    +            This option lists the target's requirements for a valid Redboot
    6956
    +            configuration."
    6957
    +
    6958
    +        cdl_option CYGBLD_BUILD_REDBOOT_BIN {
    6959
    +            display       "Build Redboot ROM binary image"
    6960
    +            active_if     CYGBLD_BUILD_REDBOOT
    6961
    +            default_value 1
    6962
    +            no_define
    6963
    +            description "This option enables the conversion of the Redboot ELF
    6964
    +                         image to a binary image suitable for ROM programming."
    6965
    +
    6966
    +            compile -library=libextras.a
    6967
    +
    6968
    +            make -priority 325 {
    6969
    +                /bin/redboot.srec : /bin/redboot.elf
    6970
    +                $(OBJCOPY) --strip-all $< $(@:.srec=.img)
    6971
    +                $(OBJCOPY) -O srec $< $@
    6972
    +            }
    6973
    +        }
    6974
    +    }
    6975
    +
    6976
    +    define_proc {
    6977
    +        puts $cdl_header "#define CYGHWR_HAL_VSR_TABLE    0"
    6978
    +        puts $cdl_header "#define CYGHWR_HAL_VIRTUAL_VECTOR_TABLE 0xF00"
    6979
    +    }
    6980
    +}
    6981
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/orp/v3_0/doc/README.html ./ecos-3.0/packages/hal/openrisc/orp/v3_0/doc/README.html
    6982
    --- /opt/ecos-3.0/packages/hal/openrisc/orp/v3_0/doc/README.html        1969-12-31 16:00:00.000000000 -0800
    6983
    +++ ./ecos-3.0/packages/hal/openrisc/orp/v3_0/doc/README.html   2009-09-16 14:06:24.000000000 -0700
    6984
    @@ -0,0 +1,13 @@
    6985
    +
    6986
    +
    6987
    +
    6988
    +
    6989
    +  
    6990
    + content="1;URL="../../../arch/current/doc/README.html">
    6991
    +  README - eCos OpenRISC Port
    6992
    +
    6993
    +
    6994
    +
    6995
    + Redirecting to OpenRISC eCos README...
    6996
    +
    6997
    +
    6998
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/orp/v3_0/include/hal_diag.h ./ecos-3.0/packages/hal/openrisc/orp/v3_0/include/hal_diag.h
    6999
    --- /opt/ecos-3.0/packages/hal/openrisc/orp/v3_0/include/hal_diag.h     1969-12-31 16:00:00.000000000 -0800
    7000
    +++ ./ecos-3.0/packages/hal/openrisc/orp/v3_0/include/hal_diag.h        2009-09-16 14:06:24.000000000 -0700
    7001
    @@ -0,0 +1,69 @@
    7002
    +#ifndef CYGONCE_HAL_HAL_DIAG_H
    7003
    +#define CYGONCE_HAL_HAL_DIAG_H
    7004
    +
    7005
    +//=============================================================================
    7006
    +//
    7007
    +//      hal_diag.h
    7008
    +//
    7009
    +//      HAL Support for Kernel Diagnostic Routines
    7010
    +//
    7011
    +//=============================================================================
    7012
    +//####ECOSGPLCOPYRIGHTBEGIN####
    7013
    +// -------------------------------------------
    7014
    +// This file is part of eCos, the Embedded Configurable Operating System.
    7015
    +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
    7016
    +// Copyright (C) 2002 Gary Thomas
    7017
    +//
    7018
    +// eCos is free software; you can redistribute it and/or modify it under
    7019
    +// the terms of the GNU General Public License as published by the Free
    7020
    +// Software Foundation; either version 2 or (at your option) any later version.
    7021
    +//
    7022
    +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
    7023
    +// WARRANTY; without even the implied warranty of MERCHANTABILITY or
    7024
    +// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    7025
    +// for more details.
    7026
    +//
    7027
    +// You should have received a copy of the GNU General Public License along
    7028
    +// with eCos; if not, write to the Free Software Foundation, Inc.,
    7029
    +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
    7030
    +//
    7031
    +// As a special exception, if other files instantiate templates or use macros
    7032
    +// or inline functions from this file, or you compile this file and link it
    7033
    +// with other works to produce a work based on this file, this file does not
    7034
    +// by itself cause the resulting work to be covered by the GNU General Public
    7035
    +// License. However the source code for this file must still be made available
    7036
    +// in accordance with section (3) of the GNU General Public License.
    7037
    +//
    7038
    +// This exception does not invalidate any other reasons why a work based on
    7039
    +// this file might be covered by the GNU General Public License.
    7040
    +//
    7041
    +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
    7042
    +// at http://sources.redhat.com/ecos/ecos-license/
    7043
    +// -------------------------------------------
    7044
    +//####ECOSGPLCOPYRIGHTEND####
    7045
    +//=============================================================================
    7046
    +//#####DESCRIPTIONBEGIN####
    7047
    +//
    7048
    +// Author(s):   nickg
    7049
    +// Contributors:nickg
    7050
    +// Date:        2003-02-28
    7051
    +// Purpose:     HAL Support for Kernel Diagnostic Routines
    7052
    +// Description: Diagnostic routines for use during kernel development.
    7053
    +// Usage:       #include 
    7054
    +//
    7055
    +//####DESCRIPTIONEND####
    7056
    +//
    7057
    +//=============================================================================
    7058
    +
    7059
    +#include 
    7060
    +
    7061
    +#include 
    7062
    +#include 
    7063
    +
    7064
    +#define HAL_DIAG_INIT() hal_if_diag_init()
    7065
    +#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
    7066
    +#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_)
    7067
    +
    7068
    +//-----------------------------------------------------------------------------
    7069
    +// end of hal_diag.h
    7070
    +#endif // CYGONCE_HAL_HAL_DIAG_H
    7071
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/orp/v3_0/include/mc.h ./ecos-3.0/packages/hal/openrisc/orp/v3_0/include/mc.h
    7072
    --- /opt/ecos-3.0/packages/hal/openrisc/orp/v3_0/include/mc.h   1969-12-31 16:00:00.000000000 -0800
    7073
    +++ ./ecos-3.0/packages/hal/openrisc/orp/v3_0/include/mc.h      2009-09-16 14:06:24.000000000 -0700
    7074
    @@ -0,0 +1,143 @@
    7075
    +//==========================================================================
    7076
    +//
    7077
    +//      mc.h
    7078
    +//
    7079
    +//      OpenCores.org memory controller definitions
    7080
    +//
    7081
    +//==========================================================================
    7082
    +//####ECOSGPLCOPYRIGHTBEGIN####
    7083
    +// -------------------------------------------
    7084
    +// This file is part of eCos, the Embedded Configurable Operating System.
    7085
    +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
    7086
    +//
    7087
    +// eCos is free software; you can redistribute it and/or modify it under
    7088
    +// the terms of the GNU General Public License as published by the Free
    7089
    +// Software Foundation; either version 2 or (at your option) any later version.
    7090
    +//
    7091
    +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
    7092
    +// WARRANTY; without even the implied warranty of MERCHANTABILITY or
    7093
    +// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    7094
    +// for more details.
    7095
    +//
    7096
    +// You should have received a copy of the GNU General Public License along
    7097
    +// with eCos; if not, write to the Free Software Foundation, Inc.,
    7098
    +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
    7099
    +//
    7100
    +// As a special exception, if other files instantiate templates or use macros
    7101
    +// or inline functions from this file, or you compile this file and link it
    7102
    +// with other works to produce a work based on this file, this file does not
    7103
    +// by itself cause the resulting work to be covered by the GNU General Public
    7104
    +// License. However the source code for this file must still be made available
    7105
    +// in accordance with section (3) of the GNU General Public License.
    7106
    +//
    7107
    +// This exception does not invalidate any other reasons why a work based on
    7108
    +// this file might be covered by the GNU General Public License.
    7109
    +//
    7110
    +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
    7111
    +// at http://sources.redhat.com/ecos/ecos-license/
    7112
    +// -------------------------------------------
    7113
    +//####ECOSGPLCOPYRIGHTEND####
    7114
    +//==========================================================================
    7115
    +//#####DESCRIPTIONBEGIN####
    7116
    +//
    7117
    +// Author(s):    sfurman
    7118
    +// Contributors: Marko Mlinar
    7119
    +// Date:         2003-01-17
    7120
    +// Purpose:      Define OpenRISC architecture special-purpose registers
    7121
    +// Usage:        #include 
    7122
    +//
    7123
    +//####DESCRIPTIONEND####
    7124
    +//
    7125
    +//==========================================================================
    7126
    +
    7127
    +/* Prototypes */
    7128
    +#ifndef __MC_H
    7129
    +#define __MC_H
    7130
    +
    7131
    +#define N_CE        (8)
    7132
    +
    7133
    +#define MC_CSR      (0x00)
    7134
    +#define MC_POC      (0x04)
    7135
    +#define MC_BA_MASK  (0x08)
    7136
    +#define MC_CSC(i)   (0x10 + (i) * 8)
    7137
    +#define MC_TMS(i)   (0x14 + (i) * 8)
    7138
    +
    7139
    +#define MC_ADDR_SPACE (MC_CSC(N_CE))
    7140
    +
    7141
    +/* POC register field definition */
    7142
    +#define MC_POC_EN_BW_OFFSET     0
    7143
    +#define MC_POC_EN_BW_WIDTH      2
    7144
    +#define MC_POC_EN_MEMTYPE_OFFSET        2
    7145
    +#define MC_POC_EN_MEMTYPE_WIDTH 2
    7146
    +
    7147
    +/* CSC register field definition */
    7148
    +#define MC_CSC_EN_OFFSET        0
    7149
    +#define MC_CSC_MEMTYPE_OFFSET   1
    7150
    +#define MC_CSC_MEMTYPE_WIDTH    2
    7151
    +#define MC_CSC_BW_OFFSET        4
    7152
    +#define MC_CSC_BW_WIDTH         2
    7153
    +#define MC_CSC_MS_OFFSET        6
    7154
    +#define MC_CSC_MS_WIDTH         2
    7155
    +#define MC_CSC_WP_OFFSET        8
    7156
    +#define MC_CSC_BAS_OFFSET       9
    7157
    +#define MC_CSC_KRO_OFFSET       10
    7158
    +#define MC_CSC_PEN_OFFSET       11
    7159
    +#define MC_CSC_SEL_OFFSET       16
    7160
    +#define MC_CSC_SEL_WIDTH        8
    7161
    +
    7162
    +#define MC_CSC_MEMTYPE_SDRAM  0
    7163
    +#define MC_CSC_MEMTYPE_SSRAM  1
    7164
    +#define MC_CSC_MEMTYPE_ASYNC  2
    7165
    +#define MC_CSC_MEMTYPE_SYNC   3
    7166
    +
    7167
    +#define MC_CSR_VALID            0xFF000703LU
    7168
    +#define MC_POC_VALID            0x0000000FLU
    7169
    +#define MC_BA_MASK_VALID        0x000000FFLU
    7170
    +#define MC_CSC_VALID            0x00FF0FFFLU
    7171
    +#define MC_TMS_SDRAM_VALID      0x0FFF83FFLU
    7172
    +#define MC_TMS_SSRAM_VALID      0x00000000LU
    7173
    +#define MC_TMS_ASYNC_VALID      0x03FFFFFFLU
    7174
    +#define MC_TMS_SYNC_VALID       0x01FFFFFFLU
    7175
    +#define MC_TMS_VALID            0xFFFFFFFFLU /* reg test compat. */
    7176
    +
    7177
    +/* TMS register field definition SDRAM */
    7178
    +#define MC_TMS_SDRAM_TRFC_OFFSET        24
    7179
    +#define MC_TMS_SDRAM_TRFC_WIDTH         4
    7180
    +#define MC_TMS_SDRAM_TRP_OFFSET         20
    7181
    +#define MC_TMS_SDRAM_TRP_WIDTH          4
    7182
    +#define MC_TMS_SDRAM_TRCD_OFFSET        17
    7183
    +#define MC_TMS_SDRAM_TRCD_WIDTH         4
    7184
    +#define MC_TMS_SDRAM_TWR_OFFSET         15
    7185
    +#define MC_TMS_SDRAM_TWR_WIDTH          2
    7186
    +#define MC_TMS_SDRAM_WBL_OFFSET         9
    7187
    +#define MC_TMS_SDRAM_OM_OFFSET          7
    7188
    +#define MC_TMS_SDRAM_OM_WIDTH           2
    7189
    +#define MC_TMS_SDRAM_CL_OFFSET          4
    7190
    +#define MC_TMS_SDRAM_CL_WIDTH           3
    7191
    +#define MC_TMS_SDRAM_BT_OFFSET          3
    7192
    +#define MC_TMS_SDRAM_BL_OFFSET          0
    7193
    +#define MC_TMS_SDRAM_BL_WIDTH           3
    7194
    +
    7195
    +/* TMS register field definition ASYNC */
    7196
    +#define MC_TMS_ASYNC_TWWD_OFFSET        20
    7197
    +#define MC_TMS_ASYNC_TWWD_WIDTH         6
    7198
    +#define MC_TMS_ASYNC_TWD_OFFSET         16
    7199
    +#define MC_TMS_ASYNC_TWD_WIDTH          4
    7200
    +#define MC_TMS_ASYNC_TWPW_OFFSET        12
    7201
    +#define MC_TMS_ASYNC_TWPW_WIDTH         4
    7202
    +#define MC_TMS_ASYNC_TRDZ_OFFSET        8
    7203
    +#define MC_TMS_ASYNC_TRDZ_WIDTH         4
    7204
    +#define MC_TMS_ASYNC_TRDV_OFFSET        0
    7205
    +#define MC_TMS_ASYNC_TRDV_WIDTH         8
    7206
    +
    7207
    +/* TMS register field definition SYNC  */
    7208
    +#define MC_TMS_SYNC_TTO_OFFSET          16
    7209
    +#define MC_TMS_SYNC_TTO_WIDTH           9
    7210
    +#define MC_TMS_SYNC_TWR_OFFSET          12
    7211
    +#define MC_TMS_SYNC_TWR_WIDTH           4
    7212
    +#define MC_TMS_SYNC_TRDZ_OFFSET         8
    7213
    +#define MC_TMS_SYNC_TRDZ_WIDTH          4
    7214
    +#define MC_TMS_SYNC_TRDV_OFFSET         0
    7215
    +#define MC_TMS_SYNC_TRDV_WIDTH          8
    7216
    +
    7217
    +#endif
    7218
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/orp/v3_0/include/pkgconf/mlt_openrisc_orp_ram.h ./ecos-3.0/packages/hal/openrisc/orp/v3_0/include/pkgconf/mlt_openrisc_orp_ram.h
    7219
    --- /opt/ecos-3.0/packages/hal/openrisc/orp/v3_0/include/pkgconf/mlt_openrisc_orp_ram.h 1969-12-31 16:00:00.000000000 -0800
    7220
    +++ ./ecos-3.0/packages/hal/openrisc/orp/v3_0/include/pkgconf/mlt_openrisc_orp_ram.h    2009-09-16 14:06:24.000000000 -0700
    7221
    @@ -0,0 +1,37 @@
    7222
    +// eCos memory layout
    7223
    +
    7224
    +#ifndef __ASSEMBLER__
    7225
    +#include 
    7226
    +#include 
    7227
    +
    7228
    +#endif
    7229
    +#define CYGMEM_REGION_ram (0)
    7230
    +#define CYGMEM_REGION_ram_SIZE (0x00400000)
    7231
    +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
    7232
    +#define CYGMEM_REGION_rom (0xf0000000)
    7233
    +#define CYGMEM_REGION_rom_SIZE (0x10000000)
    7234
    +#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
    7235
    +
    7236
    +#if 0
    7237
    +#ifndef __ASSEMBLER__
    7238
    +extern char CYG_LABEL_NAME (__reserved_vectors) [];
    7239
    +#endif
    7240
    +#define CYGMEM_SECTION_reserved_vectors (CYG_LABEL_NAME (__reserved_vectors))
    7241
    +#define CYGMEM_SECTION_reserved_vectors_SIZE (0x3000)
    7242
    +#ifndef __ASSEMBLER__
    7243
    +extern char CYG_LABEL_NAME (__reserved_vsr_table) [];
    7244
    +#endif
    7245
    +#define CYGMEM_SECTION_reserved_vsr_table (CYG_LABEL_NAME (__reserved_vsr_table))
    7246
    +#define CYGMEM_SECTION_reserved_vsr_table_SIZE (0x200)
    7247
    +#ifndef __ASSEMBLER__
    7248
    +extern char CYG_LABEL_NAME (__reserved_virtual_table) [];
    7249
    +#endif
    7250
    +#define CYGMEM_SECTION_reserved_virtual_table (CYG_LABEL_NAME (__reserved_virtual_table))
    7251
    +#define CYGMEM_SECTION_reserved_virtual_table_SIZE (0x100)
    7252
    +#endif
    7253
    +
    7254
    +#ifndef __ASSEMBLER__
    7255
    +extern char CYG_LABEL_NAME (__heap1) [];
    7256
    +#endif
    7257
    +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
    7258
    +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
    7259
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/orp/v3_0/include/pkgconf/mlt_openrisc_orp_ram.ldi ./ecos-3.0/packages/hal/openrisc/orp/v3_0/include/pkgconf/mlt_openrisc_orp_ram.ldi
    7260
    --- /opt/ecos-3.0/packages/hal/openrisc/orp/v3_0/include/pkgconf/mlt_openrisc_orp_ram.ldi       1969-12-31 16:00:00.000000000 -0800
    7261
    +++ ./ecos-3.0/packages/hal/openrisc/orp/v3_0/include/pkgconf/mlt_openrisc_orp_ram.ldi  2009-09-16 14:06:24.000000000 -0700
    7262
    @@ -0,0 +1,25 @@
    7263
    +// eCos memory layout
    7264
    +
    7265
    +#include 
    7266
    +
    7267
    +MEMORY
    7268
    +{
    7269
    +    ram : ORIGIN = 0x00000000, LENGTH = 0x00400000
    7270
    +    rom : ORIGIN = 0xF0000000, LENGTH = 0x10000000
    7271
    +}
    7272
    +
    7273
    +SECTIONS
    7274
    +{
    7275
    +    SECTIONS_BEGIN
    7276
    +    SECTION_vectors (ram, 0x00000100, LMA_EQ_VMA)
    7277
    +    SECTION_text (ram, 0x00008000, LMA_EQ_VMA)
    7278
    +    SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA)
    7279
    +    SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
    7280
    +    SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA)
    7281
    +    SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA)
    7282
    +    SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA)
    7283
    +    SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
    7284
    +    SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA)
    7285
    +    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
    7286
    +    SECTIONS_END
    7287
    +}
    7288
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/orp/v3_0/include/pkgconf/mlt_openrisc_orp_rom.h ./ecos-3.0/packages/hal/openrisc/orp/v3_0/include/pkgconf/mlt_openrisc_orp_rom.h
    7289
    --- /opt/ecos-3.0/packages/hal/openrisc/orp/v3_0/include/pkgconf/mlt_openrisc_orp_rom.h 1969-12-31 16:00:00.000000000 -0800
    7290
    +++ ./ecos-3.0/packages/hal/openrisc/orp/v3_0/include/pkgconf/mlt_openrisc_orp_rom.h    2009-09-16 14:06:24.000000000 -0700
    7291
    @@ -0,0 +1,37 @@
    7292
    +// eCos memory layout
    7293
    +
    7294
    +#ifndef __ASSEMBLER__
    7295
    +#include 
    7296
    +#include 
    7297
    +
    7298
    +#endif
    7299
    +#define CYGMEM_REGION_ram (0)
    7300
    +#define CYGMEM_REGION_ram_SIZE (0x00400000)
    7301
    +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
    7302
    +#define CYGMEM_REGION_rom (0xf0000000)
    7303
    +#define CYGMEM_REGION_rom_SIZE (0x10000000)
    7304
    +#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
    7305
    +
    7306
    +#if 0
    7307
    +#ifndef __ASSEMBLER__
    7308
    +extern char CYG_LABEL_NAME (__reserved_vectors) [];
    7309
    +#endif
    7310
    +#define CYGMEM_SECTION_reserved_vectors (CYG_LABEL_NAME (__reserved_vectors))
    7311
    +#define CYGMEM_SECTION_reserved_vectors_SIZE (0x3000)
    7312
    +#ifndef __ASSEMBLER__
    7313
    +extern char CYG_LABEL_NAME (__reserved_vsr_table) [];
    7314
    +#endif
    7315
    +#define CYGMEM_SECTION_reserved_vsr_table (CYG_LABEL_NAME (__reserved_vsr_table))
    7316
    +#define CYGMEM_SECTION_reserved_vsr_table_SIZE (0x200)
    7317
    +#ifndef __ASSEMBLER__
    7318
    +extern char CYG_LABEL_NAME (__reserved_virtual_table) [];
    7319
    +#endif
    7320
    +#define CYGMEM_SECTION_reserved_virtual_table (CYG_LABEL_NAME (__reserved_virtual_table))
    7321
    +#define CYGMEM_SECTION_reserved_virtual_table_SIZE (0x100)
    7322
    +#endif
    7323
    +
    7324
    +#ifndef __ASSEMBLER__
    7325
    +extern char CYG_LABEL_NAME (__heap1) [];
    7326
    +#endif
    7327
    +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
    7328
    +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
    7329
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/orp/v3_0/include/pkgconf/mlt_openrisc_orp_rom.ldi ./ecos-3.0/packages/hal/openrisc/orp/v3_0/include/pkgconf/mlt_openrisc_orp_rom.ldi
    7330
    --- /opt/ecos-3.0/packages/hal/openrisc/orp/v3_0/include/pkgconf/mlt_openrisc_orp_rom.ldi       1969-12-31 16:00:00.000000000 -0800
    7331
    +++ ./ecos-3.0/packages/hal/openrisc/orp/v3_0/include/pkgconf/mlt_openrisc_orp_rom.ldi  2009-09-16 14:06:24.000000000 -0700
    7332
    @@ -0,0 +1,25 @@
    7333
    +// eCos memory layout
    7334
    +
    7335
    +#include 
    7336
    +
    7337
    +MEMORY
    7338
    +{
    7339
    +    ram : ORIGIN = 0x00000000, LENGTH = 0x00400000
    7340
    +    rom : ORIGIN = 0xF0000000, LENGTH = 0x10000000
    7341
    +}
    7342
    +
    7343
    +SECTIONS
    7344
    +{
    7345
    +    SECTIONS_BEGIN
    7346
    +    SECTION_vectors (rom, 0xF0000100, LMA_EQ_VMA)
    7347
    +    SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA)
    7348
    +    SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
    7349
    +    SECTION_rodata1 (rom, ALIGN (0x8), LMA_EQ_VMA)
    7350
    +    SECTION_rodata (rom, ALIGN (0x8), LMA_EQ_VMA)
    7351
    +    SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
    7352
    +    SECTION_gcc_except_table (rom, ALIGN (0x1), LMA_EQ_VMA)
    7353
    +    SECTION_data (ram, 0x1000, FOLLOWING (.gcc_except_table))
    7354
    +    SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA)
    7355
    +    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
    7356
    +    SECTIONS_END
    7357
    +}
    7358
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/orp/v3_0/include/platform.inc ./ecos-3.0/packages/hal/openrisc/orp/v3_0/include/platform.inc
    7359
    --- /opt/ecos-3.0/packages/hal/openrisc/orp/v3_0/include/platform.inc   1969-12-31 16:00:00.000000000 -0800
    7360
    +++ ./ecos-3.0/packages/hal/openrisc/orp/v3_0/include/platform.inc      2009-09-16 14:06:24.000000000 -0700
    7361
    @@ -0,0 +1,116 @@
    7362
    +##==========================================================================
    7363
    +##
    7364
    +##      platform.inc
    7365
    +##
    7366
    +##      OpenRISC Reference Platform (ORP) board-specific defines
    7367
    +##
    7368
    +##==========================================================================
    7369
    +#####ECOSGPLCOPYRIGHTBEGIN####
    7370
    +## -------------------------------------------
    7371
    +## This file is part of eCos, the Embedded Configurable Operating System.
    7372
    +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
    7373
    +##
    7374
    +## eCos is free software; you can redistribute it and/or modify it under
    7375
    +## the terms of the GNU General Public License as published by the Free
    7376
    +## Software Foundation; either version 2 or (at your option) any later version.
    7377
    +##
    7378
    +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
    7379
    +## WARRANTY; without even the implied warranty of MERCHANTABILITY or
    7380
    +## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    7381
    +## for more details.
    7382
    +##
    7383
    +## You should have received a copy of the GNU General Public License along
    7384
    +## with eCos; if not, write to the Free Software Foundation, Inc.,
    7385
    +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
    7386
    +##
    7387
    +## As a special exception, if other files instantiate templates or use macros
    7388
    +## or inline functions from this file, or you compile this file and link it
    7389
    +## with other works to produce a work based on this file, this file does not
    7390
    +## by itself cause the resulting work to be covered by the GNU General Public
    7391
    +## License. However the source code for this file must still be made available
    7392
    +## in accordance with section (3) of the GNU General Public License.
    7393
    +##
    7394
    +## This exception does not invalidate any other reasons why a work based on
    7395
    +## this file might be covered by the GNU General Public License.
    7396
    +##
    7397
    +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
    7398
    +## at http://sources.redhat.com/ecos/ecos-license/
    7399
    +## -------------------------------------------
    7400
    +#####ECOSGPLCOPYRIGHTEND####
    7401
    +##==========================================================================
    7402
    +#######DESCRIPTIONBEGIN####
    7403
    +##
    7404
    +## Author(s):    sfurman
    7405
    +## Contributors:
    7406
    +## Date:         2003-01-20
    7407
    +## Purpose:      ORP platform-specific init
    7408
    +## Description:  This file handles the post-reset hardware initialization
    7409
    +##               that is specific to the ORP platform (but not specific to
    7410
    +##               the OpenRISC processor itself).  So far, it only
    7411
    +##               initializes the memory controller so as to map Flash and
    7412
    +##               SDRAM into the memory space.
    7413
    +##
    7414
    +######DESCRIPTIONEND####
    7415
    +##
    7416
    +##==========================================================================
    7417
    +
    7418
    +#ifndef _PLATFORM_INC_
    7419
    +#define _PLATFORM_INC_
    7420
    +
    7421
    +#include 
    7422
    +#include CYGHWR_MEMORY_LAYOUT_H
    7423
    +
    7424
    +/* Memory organization */
    7425
    +#define SDRAM_BASE_ADD  CYGMEM_REGION_ram
    7426
    +#define FLASH_BASE_ADD  CYGMEM_REGION_rom
    7427
    +
    7428
    +/* Memory Controller's base address */
    7429
    +#define MC_BASE_ADD     0x93000000
    7430
    +
    7431
    +/* Memory controller initialize magic values */
    7432
    +#define MC_CSR_VAL      0x0B000300
    7433
    +#define MC_MASK_VAL     0x000003f0
    7434
    +#define FLASH_TMS_VAL   0x00000103
    7435
    +#define SDRAM_TMS_VAL   0x19220057
    7436
    +#define FLASH_CSC_VAL   (((FLASH_BASE_ADD>>6) & 0x07ff0000) | 0x0025)
    7437
    +#define SDRAM_CSC_VAL   (((SDRAM_BASE_ADD>>6) & 0x07ff0000) | 0x0411)
    7438
    +
    7439
    +
    7440
    +        # Platform-specific, post-reset hardware initialization
    7441
    +        .macro  hal_hardware_init
    7442
    +init_mc:
    7443
    +        load32i r3,MC_BASE_ADD
    7444
    +
    7445
    +        # Program Flash chip-select
    7446
    +        load32i r5,FLASH_CSC_VAL
    7447
    +        l.sw    MC_CSC(0)(r3),r5
    7448
    +
    7449
    +        # Init flash timing
    7450
    +        load32i r5,FLASH_TMS_VAL
    7451
    +        l.sw    MC_TMS(0)(r3),r5
    7452
    +
    7453
    +        # Start decoding memory addresses to generate chip-selects
    7454
    +        l.addi  r5,r0,MC_MASK_VAL
    7455
    +        l.sw    MC_BA_MASK(r3),r5
    7456
    +
    7457
    +        load32i r5, MC_CSR_VAL
    7458
    +        l.sw    MC_CSR(r3),r5
    7459
    +
    7460
    +        # Init DRAM timing
    7461
    +        load32i r5, SDRAM_TMS_VAL
    7462
    +        l.sw    MC_TMS(1)(r3),r5
    7463
    +
    7464
    +        # Program DRAM chip-select
    7465
    +        load32i r5, SDRAM_CSC_VAL
    7466
    +        l.sw    MC_CSC(1)(r3),r5
    7467
    +
    7468
    +        # Wait for SDRAM
    7469
    +        l.addi  r3,r0,0x1000
    7470
    +1:      l.sfeqi r3,0
    7471
    +        l.bnf   1b
    7472
    +        l.addi  r3,r3,-1
    7473
    +        .endm
    7474
    +
    7475
    +#endif /* ifndef _PLATFORM_INC_ */
    7476
    +
    7477
    +#undef CYGIMP_FORCE_INTERRUPT_HANDLING_CODE_IN_RAM
    7478
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/orp/v3_0/include/plf_intr.h ./ecos-3.0/packages/hal/openrisc/orp/v3_0/include/plf_intr.h
    7479
    --- /opt/ecos-3.0/packages/hal/openrisc/orp/v3_0/include/plf_intr.h     1969-12-31 16:00:00.000000000 -0800
    7480
    +++ ./ecos-3.0/packages/hal/openrisc/orp/v3_0/include/plf_intr.h        2009-09-16 14:06:24.000000000 -0700
    7481
    @@ -0,0 +1,80 @@
    7482
    +#ifndef CYGONCE_HAL_PLF_INTR_H
    7483
    +#define CYGONCE_HAL_PLF_INTR_H
    7484
    +
    7485
    +//==========================================================================
    7486
    +//
    7487
    +//      plf_intr.h
    7488
    +//
    7489
    +//      OpenRISC ORP platform-specific interrupt definitions
    7490
    +//
    7491
    +//==========================================================================
    7492
    +//####ECOSGPLCOPYRIGHTBEGIN####
    7493
    +// -------------------------------------------
    7494
    +// This file is part of eCos, the Embedded Configurable Operating System.
    7495
    +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
    7496
    +// Copyright (C) 2002 Gary Thomas
    7497
    +//
    7498
    +// eCos is free software; you can redistribute it and/or modify it under
    7499
    +// the terms of the GNU General Public License as published by the Free
    7500
    +// Software Foundation; either version 2 or (at your option) any later version.
    7501
    +//
    7502
    +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
    7503
    +// WARRANTY; without even the implied warranty of MERCHANTABILITY or
    7504
    +// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    7505
    +// for more details.
    7506
    +//
    7507
    +// You should have received a copy of the GNU General Public License along
    7508
    +// with eCos; if not, write to the Free Software Foundation, Inc.,
    7509
    +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
    7510
    +//
    7511
    +// As a special exception, if other files instantiate templates or use macros
    7512
    +// or inline functions from this file, or you compile this file and link it
    7513
    +// with other works to produce a work based on this file, this file does not
    7514
    +// by itself cause the resulting work to be covered by the GNU General Public
    7515
    +// License. However the source code for this file must still be made available
    7516
    +// in accordance with section (3) of the GNU General Public License.
    7517
    +//
    7518
    +// This exception does not invalidate any other reasons why a work based on
    7519
    +// this file might be covered by the GNU General Public License.
    7520
    +//
    7521
    +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
    7522
    +// at http://sources.redhat.com/ecos/ecos-license/
    7523
    +// -------------------------------------------
    7524
    +//####ECOSGPLCOPYRIGHTEND####
    7525
    +//==========================================================================
    7526
    +//#####DESCRIPTIONBEGIN####
    7527
    +//
    7528
    +// Author(s):    sfurman
    7529
    +// Contributors:
    7530
    +// Date:         2002-02-28
    7531
    +// Purpose:      Define platform specific interrupt support
    7532
    +//
    7533
    +// Usage:
    7534
    +//              #include 
    7535
    +//              ...
    7536
    +//
    7537
    +//
    7538
    +//####DESCRIPTIONEND####
    7539
    +//
    7540
    +//==========================================================================
    7541
    +
    7542
    +
    7543
    +//----------------------------------------------------------------------------
    7544
    +// Reset.
    7545
    +
    7546
    +// This function should perform a hardware reset
    7547
    +// For now, it does nothing.
    7548
    +#define HAL_PLATFORM_RESET() CYG_EMPTY_STATEMENT
    7549
    +
    7550
    +// If no HW reset exists, jump to this location instead.
    7551
    +// The current value is the ROM reset entry point.
    7552
    +#define HAL_PLATFORM_RESET_ENTRY 0xF0001000
    7553
    +
    7554
    +// Define PIC interrupt numbers for peripherals
    7555
    +#define CYGNUM_HAL_INTERRUPT_SERIAL_CONSOLE    CYGNUM_HAL_INTERRUPT_2
    7556
    +#define CYGNUM_HAL_INTERRUPT_SERIAL_DEBUGGER   CYGNUM_HAL_INTERRUPT_3
    7557
    +
    7558
    +
    7559
    +//--------------------------------------------------------------------------
    7560
    +#endif // ifndef CYGONCE_HAL_PLF_INTR_H
    7561
    +// End of plf_intr.h
    7562
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/orp/v3_0/include/plf_stub.h ./ecos-3.0/packages/hal/openrisc/orp/v3_0/include/plf_stub.h
    7563
    --- /opt/ecos-3.0/packages/hal/openrisc/orp/v3_0/include/plf_stub.h     1969-12-31 16:00:00.000000000 -0800
    7564
    +++ ./ecos-3.0/packages/hal/openrisc/orp/v3_0/include/plf_stub.h        2009-09-16 14:06:24.000000000 -0700
    7565
    @@ -0,0 +1,69 @@
    7566
    +//=============================================================================
    7567
    +//
    7568
    +//      plf_stub.h
    7569
    +//
    7570
    +//      Platform header for GDB stub support.
    7571
    +//
    7572
    +//=============================================================================
    7573
    +//####ECOSGPLCOPYRIGHTBEGIN####
    7574
    +// -------------------------------------------
    7575
    +// This file is part of eCos, the Embedded Configurable Operating System.
    7576
    +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
    7577
    +//
    7578
    +// eCos is free software; you can redistribute it and/or modify it under
    7579
    +// the terms of the GNU General Public License as published by the Free
    7580
    +// Software Foundation; either version 2 or (at your option) any later version.
    7581
    +//
    7582
    +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
    7583
    +// WARRANTY; without even the implied warranty of MERCHANTABILITY or
    7584
    +// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    7585
    +// for more details.
    7586
    +//
    7587
    +// You should have received a copy of the GNU General Public License along
    7588
    +// with eCos; if not, write to the Free Software Foundation, Inc.,
    7589
    +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
    7590
    +//
    7591
    +// As a special exception, if other files instantiate templates or use macros
    7592
    +// or inline functions from this file, or you compile this file and link it
    7593
    +// with other works to produce a work based on this file, this file does not
    7594
    +// by itself cause the resulting work to be covered by the GNU General Public
    7595
    +// License. However the source code for this file must still be made available
    7596
    +// in accordance with section (3) of the GNU General Public License.
    7597
    +//
    7598
    +// This exception does not invalidate any other reasons why a work based on
    7599
    +// this file might be covered by the GNU General Public License.
    7600
    +//
    7601
    +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
    7602
    +// at http://sources.redhat.com/ecos/ecos-license/
    7603
    +// -------------------------------------------
    7604
    +//####ECOSGPLCOPYRIGHTEND####
    7605
    +//=============================================================================
    7606
    +//#####DESCRIPTIONBEGIN####
    7607
    +//
    7608
    +// Author(s):   sfurman
    7609
    +// Contributors:jskov
    7610
    +// Date:        2003-02-28
    7611
    +// Purpose:     Platform HAL stub support for PowerPC/VIPER board.
    7612
    +// Usage:       #include 
    7613
    +//
    7614
    +//####DESCRIPTIONEND####
    7615
    +//
    7616
    +//=============================================================================
    7617
    +
    7618
    +#ifndef CYGONCE_HAL_PLF_STUB_H
    7619
    +#define CYGONCE_HAL_PLF_STUB_H
    7620
    +
    7621
    +#include 
    7622
    +
    7623
    +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
    7624
    +
    7625
    +#include          // CYG_UNUSED_PARAM
    7626
    +#include 
    7627
    +
    7628
    +//----------------------------------------------------------------------------
    7629
    +// Stub initializer.
    7630
    +
    7631
    +#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
    7632
    +//-----------------------------------------------------------------------------
    7633
    +#endif // CYGONCE_HAL_PLF_STUB_H
    7634
    +// End of plf_stub.h
    7635
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/orp/v3_0/src/hal_aux.c ./ecos-3.0/packages/hal/openrisc/orp/v3_0/src/hal_aux.c
    7636
    --- /opt/ecos-3.0/packages/hal/openrisc/orp/v3_0/src/hal_aux.c  1969-12-31 16:00:00.000000000 -0800
    7637
    +++ ./ecos-3.0/packages/hal/openrisc/orp/v3_0/src/hal_aux.c     2009-09-16 14:06:24.000000000 -0700
    7638
    @@ -0,0 +1,67 @@
    7639
    +//=============================================================================
    7640
    +//
    7641
    +//      hal_aux.c
    7642
    +//
    7643
    +//      HAL auxiliary objects and code; per platform
    7644
    +//
    7645
    +//=============================================================================
    7646
    +//####ECOSGPLCOPYRIGHTBEGIN####
    7647
    +// -------------------------------------------
    7648
    +// This file is part of eCos, the Embedded Configurable Operating System.
    7649
    +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
    7650
    +// Copyright (C) 2002 Gary Thomas
    7651
    +//
    7652
    +// eCos is free software; you can redistribute it and/or modify it under
    7653
    +// the terms of the GNU General Public License as published by the Free
    7654
    +// Software Foundation; either version 2 or (at your option) any later version.
    7655
    +//
    7656
    +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
    7657
    +// WARRANTY; without even the implied warranty of MERCHANTABILITY or
    7658
    +// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    7659
    +// for more details.
    7660
    +//
    7661
    +// You should have received a copy of the GNU General Public License along
    7662
    +// with eCos; if not, write to the Free Software Foundation, Inc.,
    7663
    +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
    7664
    +//
    7665
    +// As a special exception, if other files instantiate templates or use macros
    7666
    +// or inline functions from this file, or you compile this file and link it
    7667
    +// with other works to produce a work based on this file, this file does not
    7668
    +// by itself cause the resulting work to be covered by the GNU General Public
    7669
    +// License. However the source code for this file must still be made available
    7670
    +// in accordance with section (3) of the GNU General Public License.
    7671
    +//
    7672
    +// This exception does not invalidate any other reasons why a work based on
    7673
    +// this file might be covered by the GNU General Public License.
    7674
    +//
    7675
    +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
    7676
    +// at http://sources.redhat.com/ecos/ecos-license/
    7677
    +// -------------------------------------------
    7678
    +//####ECOSGPLCOPYRIGHTEND####
    7679
    +//=============================================================================
    7680
    +//#####DESCRIPTIONBEGIN####
    7681
    +//
    7682
    +// Author(s):   hmt
    7683
    +// Contributors:hmt
    7684
    +// Date:        2003-02-28
    7685
    +// Purpose:     HAL aux objects: startup tables.
    7686
    +// Description: Tables for per-platform initialization
    7687
    +//
    7688
    +//####DESCRIPTIONEND####
    7689
    +//
    7690
    +//=============================================================================
    7691
    +
    7692
    +#include 
    7693
    +
    7694
    +//--------------------------------------------------------------------------
    7695
    +// Platform init code.
    7696
    +void
    7697
    +hal_platform_init(void)
    7698
    +{
    7699
    +    // Basic hardware initialization has already taken place
    7700
    +
    7701
    +    hal_if_init();   // Initialize logical I/O layer (virtual vector support)
    7702
    +}
    7703
    +
    7704
    +// EOF hal_aux.c
    7705
    +
    7706
    diff -NaurbBw /opt/ecos-3.0/packages/hal/openrisc/orp/v3_0/src/hal_diag.c ./ecos-3.0/packages/hal/openrisc/orp/v3_0/src/hal_diag.c
    7707
    --- /opt/ecos-3.0/packages/hal/openrisc/orp/v3_0/src/hal_diag.c 1969-12-31 16:00:00.000000000 -0800
    7708
    +++ ./ecos-3.0/packages/hal/openrisc/orp/v3_0/src/hal_diag.c    2009-09-16 14:06:24.000000000 -0700
    7709
    @@ -0,0 +1,594 @@
    7710
    +//=============================================================================
    7711
    +//
    7712
    +//      hal_diag.c
    7713
    +//
    7714
    +//      Simple polling driver for the 16c550c serial controller(s) in the ORP,
    7715
    +//      to be used for diagnostic I/O and gdb remote debugging.
    7716
    +//
    7717
    +//=============================================================================
    7718
    +//####ECOSGPLCOPYRIGHTBEGIN####
    7719
    +// -------------------------------------------
    7720
    +// This file is part of eCos, the Embedded Configurable Operating System.
    7721
    +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
    7722
    +//
    7723
    +// eCos is free software; you can redistribute it and/or modify it under
    7724
    +// the terms of the GNU General Public License as published by the Free
    7725
    +// Software Foundation; either version 2 or (at your option) any later version.
    7726
    +//
    7727
    +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
    7728
    +// WARRANTY; without even the implied warranty of MERCHANTABILITY or
    7729
    +// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    7730
    +// for more details.
    7731
    +//
    7732
    +// You should have received a copy of the GNU General Public License along
    7733
    +// with eCos; if not, write to the Free Software Foundation, Inc.,
    7734
    +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
    7735
    +//
    7736
    +// As a special exception, if other files instantiate templates or use macros
    7737
    +// or inline functions from this file, or you compile this file and link it
    7738
    +// with other works to produce a work based on this file, this file does not
    7739
    +// by itself cause the resulting work to be covered by the GNU General Public
    7740
    +// License. However the source code for this file must still be made available
    7741
    +// in accordance with section (3) of the GNU General Public License.
    7742
    +//
    7743
    +// This exception does not invalidate any other reasons why a work based on
    7744
    +// this file might be covered by the GNU General Public License.
    7745
    +//
    7746
    +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
    7747
    +// at http://sources.redhat.com/ecos/ecos-license/
    7748
    +// -------------------------------------------
    7749
    +//####ECOSGPLCOPYRIGHTEND####
    7750
    +//=============================================================================
    7751
    +//#####DESCRIPTIONBEGIN####
    7752
    +//
    7753
    +// Author(s):   sfurman
    7754
    +// Contributors:dmoseley
    7755
    +// Date:        2003-02-28
    7756
    +// Description: Simple polling driver for the 16c550c serial controller(s) in the ORP,
    7757
    +//              to be used for diagnostic I/O and gdb remote debugging.
    7758
    +//
    7759
    +//
    7760
    +//####DESCRIPTIONEND####
    7761
    +//
    7762
    +//=============================================================================
    7763
    +
    7764
    +#include 
    7765
    +#include 
    7766
    +#include CYGBLD_HAL_PLATFORM_H
    7767
    +
    7768
    +#include            // SAVE/RESTORE GP macros
    7769
    +#include              // IO macros
    7770
    +#include              // interface API
    7771
    +#include            // HAL_ENABLE/MASK/UNMASK_INTERRUPTS
    7772
    +#include            // Helper functions
    7773
    +#include             // CYG_ISR_HANDLED
    7774
    +#include           // assertion macros
    7775
    +
    7776
    +//-----------------------------------------------------------------------------
    7777
    +// Base addresses for each 16550 UART in the system
    7778
    +#define SERIAL_16550_CONSOLE_BASE_ADDR    0x90000000
    7779
    +#define SERIAL_16550_DEBUGGER_BASE_ADDR   0x90000008
    7780
    +
    7781
    +//-----------------------------------------------------------------------------
    7782
    +// Define the 16550C serial registers.
    7783
    +#define SER_16550_RBR 0x00   // receiver buffer register, read, dlab = 0
    7784
    +#define SER_16550_THR 0x00   // transmitter holding register, write, dlab = 0
    7785
    +#define SER_16550_DLL 0x00   // divisor latch (LS), read/write, dlab = 1
    7786
    +#define SER_16550_IER 0x01   // interrupt enable register, read/write, dlab = 0
    7787
    +#define SER_16550_DLM 0x01   // divisor latch (MS), read/write, dlab = 1
    7788
    +#define SER_16550_IIR 0x02   // interrupt identification reg, read, dlab = 0
    7789
    +#define SER_16550_FCR 0x02   // fifo control register, write, dlab = 0
    7790
    +#define SER_16550_AFR 0x02   // alternate function reg, read/write, dlab = 1
    7791
    +#define SER_16550_LCR 0x03   // line control register, read/write
    7792
    +#define SER_16550_MCR 0x04   // modem control register, read/write
    7793
    +#define SER_16550_LSR 0x05   // line status register, read
    7794
    +#define SER_16550_MSR 0x06   // modem status register, read
    7795
    +#define SER_16550_SCR 0x07   // scratch pad register
    7796
    +
    7797
    +// The interrupt enable register bits.
    7798
    +#define SIO_IER_ERDAI   0x01            // enable received data available irq
    7799
    +#define SIO_IER_ETHREI  0x02            // enable THR empty interrupt
    7800
    +#define SIO_IER_ELSI    0x04            // enable receiver line status irq
    7801
    +#define SIO_IER_EMSI    0x08            // enable modem status interrupt
    7802
    +
    7803
    +// The interrupt identification register bits.
    7804
    +#define SIO_IIR_IP      0x01            // 0 if interrupt pending
    7805
    +#define SIO_IIR_ID_MASK 0x0e            // mask for interrupt ID bits
    7806
    +
    7807
    +// The line status register bits.
    7808
    +#define SIO_LSR_DR      0x01            // data ready
    7809
    +#define SIO_LSR_OE      0x02            // overrun error
    7810
    +#define SIO_LSR_PE      0x04            // parity error
    7811
    +#define SIO_LSR_FE      0x08            // framing error
    7812
    +#define SIO_LSR_BI      0x10            // break interrupt
    7813
    +#define SIO_LSR_THRE    0x20            // transmitter holding register empty
    7814
    +#define SIO_LSR_TEMT    0x40            // transmitter register empty
    7815
    +#define SIO_LSR_ERR     0x80            // any error condition
    7816
    +
    7817
    +// The modem status register bits.
    7818
    +#define SIO_MSR_DCTS  0x01              // delta clear to send
    7819
    +#define SIO_MSR_DDSR  0x02              // delta data set ready
    7820
    +#define SIO_MSR_TERI  0x04              // trailing edge ring indicator
    7821
    +#define SIO_MSR_DDCD  0x08              // delta data carrier detect
    7822
    +#define SIO_MSR_CTS   0x10              // clear to send
    7823
    +#define SIO_MSR_DSR   0x20              // data set ready
    7824
    +#define SIO_MSR_RI    0x40              // ring indicator
    7825
    +#define SIO_MSR_DCD   0x80              // data carrier detect
    7826
    +
    7827
    +// The line control register bits.
    7828
    +#define SIO_LCR_WLS0   0x01             // word length select bit 0
    7829
    +#define SIO_LCR_WLS1   0x02             // word length select bit 1
    7830
    +#define SIO_LCR_STB    0x04             // number of stop bits
    7831
    +#define SIO_LCR_PEN    0x08             // parity enable
    7832
    +#define SIO_LCR_EPS    0x10             // even parity select
    7833
    +#define SIO_LCR_SP     0x20             // stick parity
    7834
    +#define SIO_LCR_SB     0x40             // set break
    7835
    +#define SIO_LCR_DLAB   0x80             // divisor latch access bit
    7836
    +
    7837
    +// The FIFO control register
    7838
    +#define SIO_FCR_FCR0   0x01             // enable xmit and rcvr fifos
    7839
    +#define SIO_FCR_FCR1   0x02             // clear RCVR FIFO
    7840
    +#define SIO_FCR_FCR2   0x04             // clear XMIT FIFO
    7841
    +
    7842
    +/////////////////////////////////////////
    7843
    +// Interrupt Enable Register
    7844
    +#define IER_RCV 0x01
    7845
    +#define IER_XMT 0x02
    7846
    +#define IER_LS  0x04
    7847
    +#define IER_MS  0x08
    7848
    +
    7849
    +// Line Control Register
    7850
    +#define LCR_WL5 0x00    // Word length
    7851
    +#define LCR_WL6 0x01
    7852
    +#define LCR_WL7 0x02
    7853
    +#define LCR_WL8 0x03
    7854
    +#define LCR_SB1 0x00    // Number of stop bits
    7855
    +#define LCR_SB1_5 0x04  // 1.5 -> only valid with 5 bit words
    7856
    +#define LCR_SB2 0x04
    7857
    +#define LCR_PN  0x00    // Parity mode - none
    7858
    +#define LCR_PE  0x0C    // Parity mode - even
    7859
    +#define LCR_PO  0x08    // Parity mode - odd
    7860
    +#define LCR_PM  0x28    // Forced "mark" parity
    7861
    +#define LCR_PS  0x38    // Forced "space" parity
    7862
    +#define LCR_DL  0x80    // Enable baud rate latch
    7863
    +
    7864
    +// Line Status Register
    7865
    +#define LSR_RSR 0x01
    7866
    +#define LSR_THE 0x20
    7867
    +
    7868
    +// Modem Control Register
    7869
    +#define MCR_DTR 0x01
    7870
    +#define MCR_RTS 0x02
    7871
    +#define MCR_INT 0x08   // Enable interrupts
    7872
    +
    7873
    +// Interrupt status register
    7874
    +#define ISR_None             0x01
    7875
    +#define ISR_Rx_Line_Status   0x06
    7876
    +#define ISR_Rx_Avail         0x04
    7877
    +#define ISR_Rx_Char_Timeout  0x0C
    7878
    +#define ISR_Tx_Empty         0x02
    7879
    +#define ISR_Modem_Status     0x00
    7880
    +
    7881
    +// FIFO control register
    7882
    +#define FCR_ENABLE     0x01
    7883
    +#define FCR_CLEAR_RCVR 0x02
    7884
    +#define FCR_CLEAR_XMIT 0x04
    7885
    +
    7886
    +// Assume the UART is driven 1/16 CPU frequency
    7887
    +#define UART_CLOCK    ((CYGHWR_HAL_OPENRISC_CPU_FREQ)*1.0e6/16.0)
    7888
    +
    7889
    +#define DIVISOR(baud) ((int)((UART_CLOCK)/baud))
    7890
    +
    7891
    +#ifdef CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD
    7892
    +#define CYG_DEV_SERIAL_BAUD_DIVISOR   \
    7893
    +    DIVISOR(CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD)
    7894
    +#else
    7895
    +#error Missing/incorrect serial baud rate defined - CDL error?
    7896
    +#endif
    7897
    +
    7898
    +
    7899
    +//-----------------------------------------------------------------------------
    7900
    +typedef struct {
    7901
    +    cyg_uint8* base;
    7902
    +    cyg_int32 msec_timeout;
    7903
    +    int isr_vector;
    7904
    +} channel_data_t;
    7905
    +
    7906
    +static channel_data_t channels[] = {
    7907
    +    { (cyg_uint8*)SERIAL_16550_CONSOLE_BASE_ADDR,
    7908
    +      1000,
    7909
    +      CYGNUM_HAL_INTERRUPT_SERIAL_CONSOLE
    7910
    +    },
    7911
    +    { (cyg_uint8*)SERIAL_16550_DEBUGGER_BASE_ADDR,
    7912
    +      1000,
    7913
    +      CYGNUM_HAL_INTERRUPT_SERIAL_DEBUGGER
    7914
    +    }
    7915
    +};
    7916
    +
    7917
    +//-----------------------------------------------------------------------------
    7918
    +// Set the baud rate
    7919
    +
    7920
    +static void
    7921
    +cyg_hal_plf_serial_set_baud(cyg_uint8* port, cyg_uint16 baud_divisor)
    7922
    +{
    7923
    +    cyg_uint8 _lcr;
    7924
    +
    7925
    +    HAL_READ_UINT8(port+SER_16550_LCR, _lcr);
    7926
    +    _lcr |= LCR_DL;
    7927
    +    HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr);
    7928
    +
    7929
    +    HAL_WRITE_UINT8(port+SER_16550_DLM, baud_divisor >> 8);
    7930
    +    HAL_WRITE_UINT8(port+SER_16550_DLL, baud_divisor & 0xff);
    7931
    +
    7932
    +    _lcr &= ~LCR_DL;
    7933
    +    HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr);
    7934
    +}
    7935
    +
    7936
    +//-----------------------------------------------------------------------------
    7937
    +// The minimal init, get and put functions. All by polling.
    7938
    +
    7939
    +void
    7940
    +cyg_hal_plf_serial_init_channel(void* __ch_data)
    7941
    +{
    7942
    +    cyg_uint8* port;
    7943
    +    cyg_uint8 _lcr;
    7944
    +
    7945
    +    // Some of the diagnostic print code calls through here with no idea what the ch_data is.
    7946
    +    // Go ahead and assume it is channels[0].
    7947
    +    if (__ch_data == 0)
    7948
    +      __ch_data = (void*)&channels[0];
    7949
    +
    7950
    +    port = ((channel_data_t*)__ch_data)->base;
    7951
    +
    7952
    +    // Disable port interrupts while changing hardware
    7953
    +    HAL_WRITE_UINT8(port+SER_16550_IER, 0);
    7954
    +
    7955
    +    // Set databits, stopbits and parity.
    7956
    +    _lcr = LCR_WL8 | LCR_SB1 | LCR_PN;
    7957
    +    HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr);
    7958
    +
    7959
    +    // Set baud rate.
    7960
    +    cyg_hal_plf_serial_set_baud(port, CYG_DEV_SERIAL_BAUD_DIVISOR);
    7961
    +
    7962
    +    // Enable and clear FIFO
    7963
    +    HAL_WRITE_UINT8(port+SER_16550_FCR, (FCR_ENABLE | FCR_CLEAR_RCVR | FCR_CLEAR_XMIT));
    7964
    +
    7965
    +    // enable RTS to keep host side happy
    7966
    +    HAL_WRITE_UINT8( port+SER_16550_MCR, MCR_RTS );
    7967
    +
    7968
    +    // Don't allow interrupts.
    7969
    +    HAL_WRITE_UINT8(port+SER_16550_IER, 0);
    7970
    +}
    7971
    +
    7972
    +void
    7973
    +cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 __ch)
    7974
    +{
    7975
    +    cyg_uint8* port;
    7976
    +    cyg_uint8 _lsr;
    7977
    +
    7978
    +    // Some of the diagnostic print code calls through here with no idea what the ch_data is.
    7979
    +    // Go ahead and assume it is channels[0].
    7980
    +    if (__ch_data == 0)
    7981
    +      __ch_data = (void*)&channels[0];
    7982
    +
    7983
    +    port = ((channel_data_t*)__ch_data)->base;
    7984
    +
    7985
    +    CYGARC_HAL_SAVE_GP();
    7986
    +
    7987
    +    do {
    7988
    +        HAL_READ_UINT8(port+SER_16550_LSR, _lsr);
    7989
    +    } while ((_lsr & SIO_LSR_THRE) == 0);
    7990
    +
    7991
    +    // Now, the transmit buffer is empty
    7992
    +    HAL_WRITE_UINT8(port+SER_16550_THR, __ch);
    7993
    +
    7994
    +    // Hang around until the character has been safely sent.
    7995
    +    do {
    7996
    +        HAL_READ_UINT8(port+SER_16550_LSR, _lsr);
    7997
    +    } while ((_lsr & SIO_LSR_THRE) == 0);
    7998
    +
    7999
    +    CYGARC_HAL_RESTORE_GP();
    8000
    +}
    8001
    +
    8002
    +static int lsr_global;
    8003
    +
    8004
    +static cyg_bool
    8005
    +cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
    8006
    +{
    8007
    +    cyg_uint8* port;
    8008
    +    cyg_uint8 _lsr;
    8009
    +
    8010
    +    // Some of the diagnostic print code calls through here with no idea what the ch_data is.
    8011
    +    // Go ahead and assume it is channels[0].
    8012
    +    if (__ch_data == 0)
    8013
    +      __ch_data = (void*)&channels[0];
    8014
    +
    8015
    +    port = ((channel_data_t*)__ch_data)->base;
    8016
    +
    8017
    +    HAL_READ_UINT8(port+SER_16550_LSR, _lsr);
    8018
    +    if ((_lsr & SIO_LSR_DR) == 0)
    8019
    +        return false;
    8020
    +    lsr_global = _lsr;
    8021
    +    CYG_ASSERT((_lsr & SIO_LSR_OE) == 0 , "UART receiver overrun error");
    8022
    +    HAL_READ_UINT8(port+SER_16550_RBR, *ch);
    8023
    +
    8024
    +    return true;
    8025
    +}
    8026
    +
    8027
    +cyg_uint8
    8028
    +cyg_hal_plf_serial_getc(void* __ch_data)
    8029
    +{
    8030
    +    cyg_uint8 ch;
    8031
    +    CYGARC_HAL_SAVE_GP();
    8032
    +
    8033
    +    // Some of the diagnostic print code calls through here with no idea what the ch_data is.
    8034
    +    // Go ahead and assume it is channels[0].
    8035
    +    if (__ch_data == 0)
    8036
    +      __ch_data = (void*)&channels[0];
    8037
    +
    8038
    +    while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
    8039
    +
    8040
    +    CYGARC_HAL_RESTORE_GP();
    8041
    +    return ch;
    8042
    +}
    8043
    +
    8044
    +static void
    8045
    +cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
    8046
    +                         cyg_uint32 __len)
    8047
    +{
    8048
    +    CYGARC_HAL_SAVE_GP();
    8049
    +
    8050
    +    // Some of the diagnostic print code calls through here with no idea what the ch_data is.
    8051
    +    // Go ahead and assume it is channels[0].
    8052
    +    if (__ch_data == 0)
    8053
    +      __ch_data = (void*)&channels[0];
    8054
    +
    8055
    +    while(__len-- > 0)
    8056
    +        cyg_hal_plf_serial_putc(__ch_data, *__buf++);
    8057
    +
    8058
    +    CYGARC_HAL_RESTORE_GP();
    8059
    +}
    8060
    +
    8061
    +static void
    8062
    +cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
    8063
    +{
    8064
    +    CYGARC_HAL_SAVE_GP();
    8065
    +
    8066
    +    // Some of the diagnostic print code calls through here with no idea what the ch_data is.
    8067
    +    // Go ahead and assume it is channels[0].
    8068
    +    if (__ch_data == 0)
    8069
    +      __ch_data = (void*)&channels[0];
    8070
    +
    8071
    +    while(__len-- > 0)
    8072
    +        *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
    8073
    +
    8074
    +    CYGARC_HAL_RESTORE_GP();
    8075
    +}
    8076
    +
    8077
    +
    8078
    +cyg_bool
    8079
    +cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
    8080
    +{
    8081
    +    int delay_count;
    8082
    +    channel_data_t* chan;
    8083
    +    cyg_bool res;
    8084
    +    CYGARC_HAL_SAVE_GP();
    8085
    +
    8086
    +    // Some of the diagnostic print code calls through here with no idea what the ch_data is.
    8087
    +    // Go ahead and assume it is channels[0].
    8088
    +    if (__ch_data == 0)
    8089
    +      __ch_data = (void*)&channels[0];
    8090
    +
    8091
    +    chan = (channel_data_t*)__ch_data;
    8092
    +
    8093
    +    delay_count = chan->msec_timeout; // delay in 1000 us steps
    8094
    +
    8095
    +    for(;;) {
    8096
    +        res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
    8097
    +        if (res || 0 == delay_count--)
    8098
    +            break;
    8099
    +        CYGACC_CALL_IF_DELAY_US(1000);
    8100
    +    }
    8101
    +
    8102
    +    CYGARC_HAL_RESTORE_GP();
    8103
    +    return res;
    8104
    +}
    8105
    +
    8106
    +static int
    8107
    +cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
    8108
    +{
    8109
    +    static int irq_state = 0;
    8110
    +    channel_data_t* chan;
    8111
    +    cyg_uint8 ier;
    8112
    +    int ret = 0;
    8113
    +    CYGARC_HAL_SAVE_GP();
    8114
    +
    8115
    +    // Some of the diagnostic print code calls through here with no idea what the ch_data is.
    8116
    +    // Go ahead and assume it is channels[0].
    8117
    +    if (__ch_data == 0)
    8118
    +      __ch_data = (void*)&channels[0];
    8119
    +
    8120
    +    chan = (channel_data_t*)__ch_data;
    8121
    +
    8122
    +    switch (__func) {
    8123
    +    case __COMMCTL_IRQ_ENABLE:
    8124
    +        irq_state = 1;
    8125
    +
    8126
    +        HAL_READ_UINT8(chan->base + SER_16550_IER, ier);
    8127
    +        ier |= SIO_IER_ERDAI;
    8128
    +        HAL_WRITE_UINT8(chan->base + SER_16550_IER, ier);
    8129
    +
    8130
    +        HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1);
    8131
    +        HAL_INTERRUPT_UNMASK(chan->isr_vector);
    8132
    +        break;
    8133
    +    case __COMMCTL_IRQ_DISABLE:
    8134
    +        ret = irq_state;
    8135
    +        irq_state = 0;
    8136
    +
    8137
    +        HAL_READ_UINT8(chan->base + SER_16550_IER, ier);
    8138
    +        ier &= ~SIO_IER_ERDAI;
    8139
    +        HAL_WRITE_UINT8(chan->base + SER_16550_IER, ier);
    8140
    +
    8141
    +        HAL_INTERRUPT_MASK(chan->isr_vector);
    8142
    +        break;
    8143
    +    case __COMMCTL_DBG_ISR_VECTOR:
    8144
    +        ret = chan->isr_vector;
    8145
    +        break;
    8146
    +    case __COMMCTL_SET_TIMEOUT:
    8147
    +    {
    8148
    +        va_list ap;
    8149
    +
    8150
    +        va_start(ap, __func);
    8151
    +
    8152
    +        ret = chan->msec_timeout;
    8153
    +        chan->msec_timeout = va_arg(ap, cyg_uint32);
    8154
    +
    8155
    +        va_end(ap);
    8156
    +    }
    8157
    +    break;
    8158
    +    case __COMMCTL_SETBAUD:
    8159
    +    {
    8160
    +        cyg_uint32 baud_rate;
    8161
    +        cyg_uint16 baud_divisor;
    8162
    +        cyg_uint8* port = chan->base;
    8163
    +        va_list ap;
    8164
    +
    8165
    +        va_start(ap, __func);
    8166
    +        baud_rate = va_arg(ap, cyg_uint32);
    8167
    +        va_end(ap);
    8168
    +
    8169
    +        switch (baud_rate)
    8170
    +        {
    8171
    +        case 110:    baud_divisor = DIVISOR(110);    break;
    8172
    +        case 150:    baud_divisor = DIVISOR(150);    break;
    8173
    +        case 300:    baud_divisor = DIVISOR(300);    break;
    8174
    +        case 600:    baud_divisor = DIVISOR(600);    break;
    8175
    +        case 1200:   baud_divisor = DIVISOR(1200);   break;
    8176
    +        case 2400:   baud_divisor = DIVISOR(2400);   break;
    8177
    +        case 4800:   baud_divisor = DIVISOR(4800);   break;
    8178
    +        case 7200:   baud_divisor = DIVISOR(7200);   break;
    8179
    +        case 9600:   baud_divisor = DIVISOR(9600);   break;
    8180
    +        case 14400:  baud_divisor = DIVISOR(14400);  break;
    8181
    +        case 19200:  baud_divisor = DIVISOR(19200);  break;
    8182
    +        case 38400:  baud_divisor = DIVISOR(38400);  break;
    8183
    +        case 57600:  baud_divisor = DIVISOR(57600);  break;
    8184
    +        case 115200: baud_divisor = DIVISOR(115200); break;
    8185
    +        case 230400: baud_divisor = DIVISOR(230400); break;
    8186
    +        default:     return -1;                      break; // Invalid baud rate selected
    8187
    +        }
    8188
    +
    8189
    +        // Disable port interrupts while changing hardware
    8190
    +        HAL_READ_UINT8(port+SER_16550_IER, ier);
    8191
    +        HAL_WRITE_UINT8(port+SER_16550_IER, 0);
    8192
    +
    8193
    +        // Set baud rate.
    8194
    +        cyg_hal_plf_serial_set_baud(port, baud_divisor);
    8195
    +
    8196
    +        // Reenable interrupts if necessary
    8197
    +        HAL_WRITE_UINT8(port+SER_16550_IER, ier);
    8198
    +    }
    8199
    +    break;
    8200
    +
    8201
    +    case __COMMCTL_GETBAUD:
    8202
    +        break;
    8203
    +    default:
    8204
    +        break;
    8205
    +    }
    8206
    +    CYGARC_HAL_RESTORE_GP();
    8207
    +    return ret;
    8208
    +}
    8209
    +
    8210
    +static int
    8211
    +cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
    8212
    +                       CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
    8213
    +{
    8214
    +    int res = 0;
    8215
    +    cyg_uint8 _iir, c;
    8216
    +    channel_data_t* chan;
    8217
    +    CYGARC_HAL_SAVE_GP();
    8218
    +
    8219
    +    // Some of the diagnostic print code calls through here with no idea what the ch_data is.
    8220
    +    // Go ahead and assume it is channels[0].
    8221
    +    if (__ch_data == 0)
    8222
    +      __ch_data = (void*)&channels[0];
    8223
    +
    8224
    +    chan = (channel_data_t*)__ch_data;
    8225
    +
    8226
    +    HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
    8227
    +
    8228
    +    HAL_READ_UINT8(chan->base + SER_16550_IIR, _iir);
    8229
    +    _iir &= SIO_IIR_ID_MASK;
    8230
    +
    8231
    +    *__ctrlc = 0;
    8232
    +    if ((_iir == ISR_Rx_Avail) || (_iir == ISR_Rx_Char_Timeout)) {
    8233
    +
    8234
    +        HAL_READ_UINT8(chan->base + SER_16550_RBR, c);
    8235
    +
    8236
    +        if( cyg_hal_is_break( &c , 1 ) )
    8237
    +            *__ctrlc = 1;
    8238
    +
    8239
    +        res = CYG_ISR_HANDLED;
    8240
    +    }
    8241
    +
    8242
    +    /* sfurman - Hmmm.  Under or1ksim, we sometimes receive interrupts
    8243
    +       when no characters are in the FIFO.  I think this is a SW bug
    8244
    +       and not a problem w/ or1ksim, but until the problem is solved,
    8245
    +       we always consume the interrupt */
    8246
    +    res = CYG_ISR_HANDLED;
    8247
    +
    8248
    +    CYGARC_HAL_RESTORE_GP();
    8249
    +    return res;
    8250
    +}
    8251
    +
    8252
    +static void
    8253
    +cyg_hal_plf_serial_init(void)
    8254
    +{
    8255
    +    int i;
    8256
    +    hal_virtual_comm_table_t* comm;
    8257
    +    int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
    8258
    +
    8259
    +    //#define NUM_CHANNELS (sizeof(channels)/sizeof(channels[0]))
    8260
    +#define NUM_CHANNELS CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS
    8261
    +    for (i = 0; i < NUM_CHANNELS; i++) {
    8262
    +
    8263
    +       // Disable interrupts.
    8264
    +       HAL_INTERRUPT_MASK(channels[i].isr_vector);
    8265
    +
    8266
    +       // Init channels
    8267
    +       cyg_hal_plf_serial_init_channel((void*)&channels[i]);
    8268
    +
    8269
    +       // Setup procs in the vector table
    8270
    +
    8271
    +       // Set COMM callbacks for channel
    8272
    +       CYGACC_CALL_IF_SET_CONSOLE_COMM(i);
    8273
    +       comm = CYGACC_CALL_IF_CONSOLE_PROCS();
    8274
    +       CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]);
    8275
    +       CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
    8276
    +       CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
    8277
    +       CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
    8278
    +       CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
    8279
    +       CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
    8280
    +       CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
    8281
    +       CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
    8282
    +    }
    8283
    +
    8284
    +    // Restore original console
    8285
    +    CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
    8286
    +}
    8287
    +
    8288
    +void
    8289
    +cyg_hal_plf_comms_init(void)
    8290
    +{
    8291
    +    static int initialized = 0;
    8292
    +
    8293
    +    if (initialized)
    8294
    +        return;
    8295
    +
    8296
    +    initialized = 1;
    8297
    +
    8298
    +    cyg_hal_plf_serial_init();
    8299
    +}
    8300
    +
    8301
    +//-----------------------------------------------------------------------------
    8302
    +// end of ser16c550c.c
    8303
    +

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