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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's ALU                                                ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  ALU                                                         ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7  2002/09/03 22:28:21  lampret
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
//
// Revision 1.6  2002/03/29 16:40:10  lampret
// Added a directive to ignore signed division variables that are only used in simulation.
//
// Revision 1.5  2002/03/29 16:33:59  lampret
// Added again just recently removed full_case directive
//
// Revision 1.4  2002/03/29 15:16:53  lampret
// Some of the warnings fixed.
//
// Revision 1.3  2002/01/28 01:15:59  lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10  2001/11/12 01:45:40  lampret
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
//
// Revision 1.9  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8  2001/10/19 23:28:45  lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_alu(
        a, b, mult_mac_result, macrc_op,
        alu_op, shrot_op, comp_op,
        result, flagforw, flag_we,
        cyforw, cy_we, carry
);
 
parameter width = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
input   [width-1:0]              a;
input   [width-1:0]              b;
input   [width-1:0]              mult_mac_result;
input                           macrc_op;
input   [`OR1200_ALUOP_WIDTH-1:0]        alu_op;
input   [`OR1200_SHROTOP_WIDTH-1:0]      shrot_op;
input   [`OR1200_COMPOP_WIDTH-1:0]       comp_op;
output  [width-1:0]              result;
output                          flagforw;
output                          flag_we;
output                          cyforw;
output                          cy_we;
input                           carry;
 
//
// Internal wires and regs
//
reg     [width-1:0]              result;
reg     [width-1:0]              shifted_rotated;
reg                             flagforw;
reg                             flagcomp;
reg                             flag_we;
reg                             cy_we;
// synopsys translate_off
`ifdef OR1200_SIM_ALU_DIV
integer                         d1;
integer                         d2;
`endif
// synopsys translate_on
wire    [width-1:0]              comp_a;
wire    [width-1:0]              comp_b;
`ifdef OR1200_IMPL_ALU_COMP1
wire                            a_eq_b;
wire                            a_lt_b;
`endif
wire    [width-1:0]              result_sum;
`ifdef OR1200_IMPL_ADDC
wire    [width-1:0]              result_csum;
`endif
wire    [width-1:0]              result_and;
wire                            cyforw;
 
//
// Combinatorial logic
//
assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
`ifdef OR1200_IMPL_ALU_COMP1
assign a_eq_b = (comp_a == comp_b);
assign a_lt_b = (comp_a < comp_b);
`endif
assign {cyforw, result_sum} = a + b;
`ifdef OR1200_IMPL_ADDC
assign {cyforw, result_csum} = a + b + carry;
`endif
assign result_and = a & b;
 
//
// Simulation check for bad ALU behavior
//
`ifdef OR1200_WARNINGS
// synopsys translate_off
always @(result) begin
        if (result === 32'bx)
                $display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);
end
// synopsys translate_on
`endif
 
//
// Central part of the ALU
//
always @(alu_op or a or b or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result) begin
`ifdef OR1200_CASE_DEFAULT
        casex (alu_op)          // synopsys parallel_case
`else
        casex (alu_op)          // synopsys full_case parallel_case
`endif
                `OR1200_ALUOP_SHROT : begin
                                result = shifted_rotated;
                end
                `OR1200_ALUOP_ADD : begin
                                result = result_sum;
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC : begin
                                result = result_csum;
                end
`endif
                `OR1200_ALUOP_SUB : begin
                                result = a - b;
                end
                `OR1200_ALUOP_XOR : begin
                                result = a ^ b;
                end
                `OR1200_ALUOP_OR  : begin
                                result = a | b;
                end
                `OR1200_ALUOP_IMM : begin
                                result = b;
                end
                `OR1200_ALUOP_MOVHI : begin
                                if (macrc_op) begin
                                        result = mult_mac_result;
                                end
                                else begin
                                        result = b << 16;
                                end
                end
                `OR1200_ALUOP_MUL : begin
                                result = mult_mac_result;
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: MUL operation: %h * %h = %h", $time, a, b, mult_mac_result);
// synopsys translate_on
`endif
                end
// synopsys translate_off
`ifdef OR1200_SIM_ALU_DIV
                `OR1200_ALUOP_DIV : begin
                                d1 = a;
                                d2 = b;
                                $display("DIV operation: %d / %d = %d", d1, d2, d1/d2);
                                if (d2)
                                        result = d1 / d2;
                                else
                                        result = 32'h00000000;
                end
`endif
`ifdef OR1200_SIM_ALU_DIVU
                `OR1200_ALUOP_DIVU : begin
                                if (b)
                                        result = a / b;
                                else
                                        result = 32'h00000000;
                end
`endif
// synopsys translate_on
`ifdef OR1200_CASE_DEFAULT
                default: begin
`else
                `OR1200_ALUOP_COMP, `OR1200_ALUOP_AND
`endif
                                result = result_and;
                end
        endcase
end
 
//
// Generate flag and flag write enable
//
always @(alu_op or result_sum or result_and or flagcomp) begin
        casex (alu_op)          // synopsys parallel_case
`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
                `OR1200_ALUOP_ADD : begin
                        flagforw = (result_sum == 32'h0000_0000);
                        flag_we = 1'b1;
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC : begin
                        flagforw = (result_csum == 32'h0000_0000);
                        flag_we = 1'b1;
                end
`endif
                `OR1200_ALUOP_AND: begin
                        flagforw = (result_and == 32'h0000_0000);
                        flag_we = 1'b1;
                end
`endif
                `OR1200_ALUOP_COMP: begin
                        flagforw = flagcomp;
                        flag_we = 1'b1;
                end
                default: begin
                        flagforw = 1'b0;
                        flag_we = 1'b0;
                end
        endcase
end
 
//
// Generate SR[CY] write enable
//
always @(alu_op) begin
        casex (alu_op)          // synopsys parallel_case
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC : begin
                        cy_we = 1'b1;
                end
`endif
                default: begin
                        cy_we = 1'b0;
                end
        endcase
end
 
//
// Shifts and rotation
//
always @(shrot_op or a or b) begin
        case (shrot_op)         // synopsys parallel_case
        `OR1200_SHROTOP_SLL :
                                shifted_rotated = (a << b[4:0]);
                `OR1200_SHROTOP_SRL :
                                shifted_rotated = (a >> b[4:0]);
 
`ifdef OR1200_IMPL_ALU_ROTATE
                `OR1200_SHROTOP_ROR :
                                shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) | (a >> b[4:0]);
`endif
                default:
                                shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) | a >> b[4:0];
        endcase
end
 
//
// First type of compare implementation
//
`ifdef OR1200_IMPL_ALU_COMP1
always @(comp_op or a_eq_b or a_lt_b) begin
        case(comp_op[2:0])       // synopsys parallel_case
                `OR1200_COP_SFEQ:
                        flagcomp = a_eq_b;
                `OR1200_COP_SFNE:
                        flagcomp = ~a_eq_b;
                `OR1200_COP_SFGT:
                        flagcomp = ~(a_eq_b | a_lt_b);
                `OR1200_COP_SFGE:
                        flagcomp = ~a_lt_b;
                `OR1200_COP_SFLT:
                        flagcomp = a_lt_b;
                `OR1200_COP_SFLE:
                        flagcomp = a_eq_b | a_lt_b;
                default:
                        flagcomp = 1'b0;
        endcase
end
`endif
 
//
// Second type of compare implementation
//
`ifdef OR1200_IMPL_ALU_COMP2
always @(comp_op or comp_a or comp_b) begin
        case(comp_op[2:0])       // synopsys parallel_case
                `OR1200_COP_SFEQ:
                        flagcomp = (comp_a == comp_b);
                `OR1200_COP_SFNE:
                        flagcomp = (comp_a != comp_b);
                `OR1200_COP_SFGT:
                        flagcomp = (comp_a > comp_b);
                `OR1200_COP_SFGE:
                        flagcomp = (comp_a >= comp_b);
                `OR1200_COP_SFLT:
                        flagcomp = (comp_a < comp_b);
                `OR1200_COP_SFLE:
                        flagcomp = (comp_a <= comp_b);
                default:
                        flagcomp = 1'b0;
        endcase
end
`endif
 
endmodule

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's ALU ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// ALU ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	1032	lampret	`// Revision 1.7 2002/09/03 22:28:21 lampret`
48			`// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.`
49			`//`
50	1022	lampret	`// Revision 1.6 2002/03/29 16:40:10 lampret`
51			`// Added a directive to ignore signed division variables that are only used in simulation.`
52			`//`
53	795	lampret	`// Revision 1.5 2002/03/29 16:33:59 lampret`
54			`// Added again just recently removed full_case directive`
55			`//`
56	794	lampret	`// Revision 1.4 2002/03/29 15:16:53 lampret`
57			`// Some of the warnings fixed.`
58			`//`
59	788	lampret	`// Revision 1.3 2002/01/28 01:15:59 lampret`
60			`// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.`
61			`//`
62	617	lampret	`// Revision 1.2 2002/01/14 06:18:22 lampret`
63			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
64			`//`
65	562	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
66			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
67			`//`
68	504	lampret	`// Revision 1.10 2001/11/12 01:45:40 lampret`
69			`// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.`
70			`//`
71			`// Revision 1.9 2001/10/21 17:57:16 lampret`
72			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
73			`//`
74			`// Revision 1.8 2001/10/19 23:28:45 lampret`
75			`// Fixed some synthesis warnings. Configured with caches and MMUs.`
76			`//`
77			`// Revision 1.7 2001/10/14 13:12:09 lampret`
78			`// MP3 version.`
79			`//`
80			`// Revision 1.1.1.1 2001/10/06 10:18:35 igorm`
81			`// no message`
82			`//`
83			`// Revision 1.2 2001/08/09 13:39:33 lampret`
84			`// Major clean-up.`
85			`//`
86			`// Revision 1.1 2001/07/20 00:46:03 lampret`
87			`// Development version of RTL. Libraries are missing.`
88			`//`
89			`//`
90
91			`// synopsys translate_off`
92			`include "timescale.v"
93			`// synopsys translate_on`
94			`include "or1200_defines.v"
95
96			`module or1200_alu(`
97			`a, b, mult_mac_result, macrc_op,`
98			`alu_op, shrot_op, comp_op,`
99	1032	lampret	`result, flagforw, flag_we,`
100			`cyforw, cy_we, carry`
101	504	lampret	`);`
102
103			parameter width = `OR1200_OPERAND_WIDTH;
104
105			`//`
106			`// I/O`
107			`//`
108			`input [width-1:0] a;`
109			`input [width-1:0] b;`
110			`input [width-1:0] mult_mac_result;`
111			`input macrc_op;`
112			input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
113			input [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
114			input [`OR1200_COMPOP_WIDTH-1:0] comp_op;
115			`output [width-1:0] result;`
116			`output flagforw;`
117			`output flag_we;`
118	1032	lampret	`output cyforw;`
119			`output cy_we;`
120			`input carry;`
121	504	lampret
122			`//`
123			`// Internal wires and regs`
124			`//`
125			`reg [width-1:0] result;`
126			`reg [width-1:0] shifted_rotated;`
127			`reg flagforw;`
128	617	lampret	`reg flagcomp;`
129	504	lampret	`reg flag_we;`
130	1032	lampret	`reg cy_we;`
131	795	lampret	`// synopsys translate_off`
132	788	lampret	`ifdef OR1200_SIM_ALU_DIV
133	504	lampret	`integer d1;`
134			`integer d2;`
135	788	lampret	`endif
136	795	lampret	`// synopsys translate_on`
137	504	lampret	`wire [width-1:0] comp_a;`
138			`wire [width-1:0] comp_b;`
139			`ifdef OR1200_IMPL_ALU_COMP1
140			`wire a_eq_b;`
141			`wire a_lt_b;`
142			`endif
143	617	lampret	`wire [width-1:0] result_sum;`
144	1032	lampret	`ifdef OR1200_IMPL_ADDC
145			`wire [width-1:0] result_csum;`
146			`endif
147	617	lampret	`wire [width-1:0] result_and;`
148	1032	lampret	`wire cyforw;`
149	504	lampret
150			`//`
151			`// Combinatorial logic`
152			`//`
153			`assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};`
154			`assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};`
155			`ifdef OR1200_IMPL_ALU_COMP1
156			`assign a_eq_b = (comp_a == comp_b);`
157			`assign a_lt_b = (comp_a < comp_b);`
158			`endif
159	1032	lampret	`assign {cyforw, result_sum} = a + b;`
160			`ifdef OR1200_IMPL_ADDC
161			`assign {cyforw, result_csum} = a + b + carry;`
162			`endif
163	617	lampret	`assign result_and = a & b;`
164	504	lampret
165			`//`
166			`// Simulation check for bad ALU behavior`
167			`//`
168			`ifdef OR1200_WARNINGS
169			`// synopsys translate_off`
170			`always @(result) begin`
171			`if (result === 32'bx)`
172			`$display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);`
173			`end`
174			`// synopsys translate_on`
175			`endif
176
177			`//`
178			`// Central part of the ALU`
179			`//`
180	617	lampret	`always @(alu_op or a or b or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result) begin`
181	1022	lampret	`ifdef OR1200_CASE_DEFAULT
182			`casex (alu_op) // synopsys parallel_case`
183			`else
184			`casex (alu_op) // synopsys full_case parallel_case`
185			`endif
186	504	lampret	`OR1200_ALUOP_SHROT : begin
187			`result = shifted_rotated;`
188			`end`
189			`OR1200_ALUOP_ADD : begin
190	617	lampret	`result = result_sum;`
191	504	lampret	`end`
192	1032	lampret	`ifdef OR1200_IMPL_ADDC
193			`OR1200_ALUOP_ADDC : begin
194			`result = result_csum;`
195			`end`
196			`endif
197	504	lampret	`OR1200_ALUOP_SUB : begin
198			`result = a - b;`
199			`end`
200			`OR1200_ALUOP_XOR : begin
201			`result = a ^ b;`
202			`end`
203			`OR1200_ALUOP_OR : begin
204			`result = a \| b;`
205			`end`
206			`OR1200_ALUOP_IMM : begin
207			`result = b;`
208			`end`
209			`OR1200_ALUOP_MOVHI : begin
210			`if (macrc_op) begin`
211			`result = mult_mac_result;`
212			`end`
213			`else begin`
214			`result = b << 16;`
215			`end`
216			`end`
217			`OR1200_ALUOP_MUL : begin
218			`result = mult_mac_result;`
219			`ifdef OR1200_VERBOSE
220			`// synopsys translate_off`
221			`$display("%t: MUL operation: %h * %h = %h", $time, a, b, mult_mac_result);`
222			`// synopsys translate_on`
223			`endif
224			`end`
225			`// synopsys translate_off`
226			`ifdef OR1200_SIM_ALU_DIV
227			`OR1200_ALUOP_DIV : begin
228			`d1 = a;`
229			`d2 = b;`
230			`$display("DIV operation: %d / %d = %d", d1, d2, d1/d2);`
231			`if (d2)`
232			`result = d1 / d2;`
233			`else`
234			`result = 32'h00000000;`
235			`end`
236			`endif
237			`ifdef OR1200_SIM_ALU_DIVU
238			`OR1200_ALUOP_DIVU : begin
239			`if (b)`
240			`result = a / b;`
241			`else`
242			`result = 32'h00000000;`
243			`end`
244			`endif
245			`// synopsys translate_on`
246	1022	lampret	`ifdef OR1200_CASE_DEFAULT
247			`default: begin`
248			`else
249			`OR1200_ALUOP_COMP, `OR1200_ALUOP_AND
250			`endif
251	617	lampret	`result = result_and;`
252			`end`
253			`endcase`
254			`end`
255
256			`//`
257			`// Generate flag and flag write enable`
258			`//`
259			`always @(alu_op or result_sum or result_and or flagcomp) begin`
260	788	lampret	`casex (alu_op) // synopsys parallel_case`
261	1032	lampret	`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
262	617	lampret	`OR1200_ALUOP_ADD : begin
263			`flagforw = (result_sum == 32'h0000_0000);`
264	1032	lampret	`flag_we = 1'b1;`
265	617	lampret	`end`
266	1032	lampret	`ifdef OR1200_IMPL_ADDC
267			`OR1200_ALUOP_ADDC : begin
268			`flagforw = (result_csum == 32'h0000_0000);`
269			`flag_we = 1'b1;`
270			`end`
271			`endif
272	617	lampret	`OR1200_ALUOP_AND: begin
273			`flagforw = (result_and == 32'h0000_0000);`
274	1032	lampret	`flag_we = 1'b1;`
275	617	lampret	`end`
276	1032	lampret	`endif
277	504	lampret	`OR1200_ALUOP_COMP: begin
278	617	lampret	`flagforw = flagcomp;`
279			`flag_we = 1'b1;`
280	504	lampret	`end`
281	617	lampret	`default: begin`
282			`flagforw = 1'b0;`
283			`flag_we = 1'b0;`
284	504	lampret	`end`
285			`endcase`
286			`end`
287
288			`//`
289	1032	lampret	`// Generate SR[CY] write enable`
290			`//`
291			`always @(alu_op) begin`
292			`casex (alu_op) // synopsys parallel_case`
293			`ifdef OR1200_IMPL_ADDC
294			`OR1200_ALUOP_ADDC : begin
295			`cy_we = 1'b1;`
296			`end`
297			`endif
298			`default: begin`
299			`cy_we = 1'b0;`
300			`end`
301			`endcase`
302			`end`
303
304			`//`
305	504	lampret	`// Shifts and rotation`
306			`//`
307			`always @(shrot_op or a or b) begin`
308			`case (shrot_op) // synopsys parallel_case`
309	562	lampret	`OR1200_SHROTOP_SLL :
310	504	lampret	`shifted_rotated = (a << b[4:0]);`
311			`OR1200_SHROTOP_SRL :
312			`shifted_rotated = (a >> b[4:0]);`
313	562	lampret
314	504	lampret	`ifdef OR1200_IMPL_ALU_ROTATE
315			`OR1200_SHROTOP_ROR :
316			`shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) \| (a >> b[4:0]);`
317			`endif
318			`default:`
319			`shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) \| a >> b[4:0];`
320			`endcase`
321			`end`
322
323			`//`
324			`// First type of compare implementation`
325			`//`
326			`ifdef OR1200_IMPL_ALU_COMP1
327			`always @(comp_op or a_eq_b or a_lt_b) begin`
328	788	lampret	`case(comp_op[2:0]) // synopsys parallel_case`
329	504	lampret	`OR1200_COP_SFEQ:
330	617	lampret	`flagcomp = a_eq_b;`
331	504	lampret	`OR1200_COP_SFNE:
332	617	lampret	`flagcomp = ~a_eq_b;`
333	504	lampret	`OR1200_COP_SFGT:
334	617	lampret	`flagcomp = ~(a_eq_b \| a_lt_b);`
335	504	lampret	`OR1200_COP_SFGE:
336	617	lampret	`flagcomp = ~a_lt_b;`
337	504	lampret	`OR1200_COP_SFLT:
338	617	lampret	`flagcomp = a_lt_b;`
339	504	lampret	`OR1200_COP_SFLE:
340	617	lampret	`flagcomp = a_eq_b \| a_lt_b;`
341	504	lampret	`default:`
342	617	lampret	`flagcomp = 1'b0;`
343	504	lampret	`endcase`
344			`end`
345			`endif
346
347			`//`
348			`// Second type of compare implementation`
349			`//`
350			`ifdef OR1200_IMPL_ALU_COMP2
351			`always @(comp_op or comp_a or comp_b) begin`
352	788	lampret	`case(comp_op[2:0]) // synopsys parallel_case`
353	504	lampret	`OR1200_COP_SFEQ:
354	617	lampret	`flagcomp = (comp_a == comp_b);`
355	504	lampret	`OR1200_COP_SFNE:
356	617	lampret	`flagcomp = (comp_a != comp_b);`
357	504	lampret	`OR1200_COP_SFGT:
358	617	lampret	`flagcomp = (comp_a > comp_b);`
359	504	lampret	`OR1200_COP_SFGE:
360	617	lampret	`flagcomp = (comp_a >= comp_b);`
361	504	lampret	`OR1200_COP_SFLT:
362	617	lampret	`flagcomp = (comp_a < comp_b);`
363	504	lampret	`OR1200_COP_SFLE:
364	617	lampret	`flagcomp = (comp_a <= comp_b);`
365	504	lampret	`default:`
366	617	lampret	`flagcomp = 1'b0;`
367	504	lampret	`endcase`
368			`end`
369			`endif
370
371			`endmodule`

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