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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Single-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage Single-Port Sync RAM                               ////
////  - Virtual Silicon Single-Port Sync RAM                      ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB4_S16                                   ////
////  - Altera LPM                                                ////
////                                                              ////
////  To Do:                                                      ////
////   - xilinx rams need external tri-state logic                ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2003/04/07 01:19:07  lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2  2002/10/17 20:04:40  lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10  2001/11/27 21:24:04  lampret
// Changed instantiation name of VS RAMs.
//
// Revision 1.9  2001/11/27 19:45:04  lampret
// Fixed VS RAM instantiation - again.
//
// Revision 1.8  2001/11/23 21:42:31  simons
// Program counter divided to PPC and NPC.
//
// Revision 1.6  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.5  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/30 05:38:02  lampret
// Adding empty directories required by HDL coding guidelines
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram_512x20(
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, do
);
 
//
// Default address and data buses width
//
parameter aw = 9;
parameter dw = 20;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input                   clk;    // Clock
input                   rst;    // Reset
input                   ce;     // Chip enable input
input                   we;     // Write enable input
input                   oe;     // Output enable input
input   [aw-1:0] addr;   // address bus inputs
input   [dw-1:0] di;     // input data bus
output  [dw-1:0] do;     // output data bus
 
//
// Internal wires and registers
//
wire    [3:0]            unconnected;
 
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_512x20 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_512x20_bist artisan_ssp(
`else
art_hssp_512x20 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CLK(clk),
        .CEN(~ce),
        .WEN(~we),
        .A(addr),
        .D(di),
        .OEN(~oe),
        .Q(do)
);
 
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .do(do)
);
 
`else
 
`ifdef OR1200_VIRAGE_SSP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
        .clk(clk),
        .adr(addr),
        .d(di),
        .we(we),
        .oe(oe),
        .me(ce),
        .q(do)
);
 
`else
 
`ifdef OR1200_VIRTUALSILICON_SSP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_512x20 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_512x20_bist vs_ssp(
`else
vs_hdsp_512x20 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di),
        .WEN(~we),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(do)
);
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S8 ramb4_s8_0(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[7:0]),
        .EN(ce),
        .WE(we),
        .DO(do[7:0])
);
 
//
// Block 1
//
RAMB4_S8 ramb4_s8_1(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[15:8]),
        .EN(ce),
        .WE(we),
        .DO(do[15:8])
);
 
//
// Block 2
//
RAMB4_S8 ramb4_s8_2(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI({4'b0000, di[19:16]}),
        .EN(ce),
        .WE(we),
        .DO({unconnected, do[19:16]})
);
 
`else
 
`ifdef OR1200_ALTERA_LPM
 
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
 
wire    wr;
 
assign  wr = ce & we;
 
initial $display("Using Altera LPM.");
 
lpm_ram_dq lpm_ram_dq_component (
        .address(addr),
        .inclock(clk),
        .outclock(clk),
        .data(di),
        .we(wr),
        .q(do)
);
 
defparam lpm_ram_dq_component.lpm_width = dw,
        lpm_ram_dq_component.lpm_widthad = aw,
        lpm_ram_dq_component.lpm_indata = "REGISTERED",
        lpm_ram_dq_component.lpm_address_control = "REGISTERED",
        lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
        lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
        // examplar attribute lpm_ram_dq_component NOOPT TRUE
 
`else
 
//
// Generic single-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [dw-1:0] do_reg;                 // RAM data output register
 
//
// Data output drivers
//
assign do = (oe) ? do_reg : {dw{1'b0}};
 
//
// RAM read and write
//
always @(posedge clk)
        if (ce && !we)
                do_reg <= #1 mem[addr];
        else if (ce && we)
                mem[addr] <= #1 di;
 
`endif  // !OR1200_ALTERA_LPM
`endif  // !OR1200_XILINX_RAMB4_S16
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRAGE_SSP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SSP
 
endmodule

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Single-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage Single-Port Sync RAM ////`
22			`//// - Virtual Silicon Single-Port Sync RAM ////`
23			`//// ////`
24			`//// Supported FPGA RAMs are: ////`
25			`//// - Xilinx Virtex RAMB4_S16 ////`
26	1129	lampret	`//// - Altera LPM ////`
27	504	lampret	`//// ////`
28			`//// To Do: ////`
29			`//// - xilinx rams need external tri-state logic ////`
30			`//// - fix avant! two-port ram ////`
31	1129	lampret	`//// - add additional RAMs ////`
32	504	lampret	`//// ////`
33			`//// Author(s): ////`
34			`//// - Damjan Lampret, lampret@opencores.org ////`
35			`//// ////`
36			`//////////////////////////////////////////////////////////////////////`
37			`//// ////`
38			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
39			`//// ////`
40			`//// This source file may be used and distributed without ////`
41			`//// restriction provided that this copyright statement is not ////`
42			`//// removed from the file and that any derivative work contains ////`
43			`//// the original copyright notice and the associated disclaimer. ////`
44			`//// ////`
45			`//// This source file is free software; you can redistribute it ////`
46			`//// and/or modify it under the terms of the GNU Lesser General ////`
47			`//// Public License as published by the Free Software Foundation; ////`
48			`//// either version 2.1 of the License, or (at your option) any ////`
49			`//// later version. ////`
50			`//// ////`
51			`//// This source is distributed in the hope that it will be ////`
52			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
53			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
54			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
55			`//// details. ////`
56			`//// ////`
57			`//// You should have received a copy of the GNU Lesser General ////`
58			`//// Public License along with this source; if not, download it ////`
59			`//// from http://www.opencores.org/lgpl.shtml ////`
60			`//// ////`
61			`//////////////////////////////////////////////////////////////////////`
62			`//`
63			`// CVS Revision History`
64			`//`
65			`// $Log: not supported by cvs2svn $`
66	1214	simons	`// Revision 1.3 2003/04/07 01:19:07 lampret`
67			`// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.`
68			`//`
69	1129	lampret	`// Revision 1.2 2002/10/17 20:04:40 lampret`
70			`// Added BIST scan. Special VS RAMs need to be used to implement BIST.`
71			`//`
72	1063	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
73			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
74			`//`
75	504	lampret	`// Revision 1.10 2001/11/27 21:24:04 lampret`
76			`// Changed instantiation name of VS RAMs.`
77			`//`
78			`// Revision 1.9 2001/11/27 19:45:04 lampret`
79			`// Fixed VS RAM instantiation - again.`
80			`//`
81			`// Revision 1.8 2001/11/23 21:42:31 simons`
82			`// Program counter divided to PPC and NPC.`
83			`//`
84			`// Revision 1.6 2001/10/21 17:57:16 lampret`
85			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
86			`//`
87			`// Revision 1.5 2001/10/14 13:12:09 lampret`
88			`// MP3 version.`
89			`//`
90			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
91			`// no message`
92			`//`
93			`// Revision 1.1 2001/08/09 13:39:33 lampret`
94			`// Major clean-up.`
95			`//`
96			`// Revision 1.2 2001/07/30 05:38:02 lampret`
97			`// Adding empty directories required by HDL coding guidelines`
98			`//`
99			`//`
100
101			`// synopsys translate_off`
102			`include "timescale.v"
103			`// synopsys translate_on`
104			`include "or1200_defines.v"
105
106			`module or1200_spram_512x20(`
107	1063	lampret	`ifdef OR1200_BIST
108			`// RAM BIST`
109	1214	simons	`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
110	1063	lampret	`endif
111	504	lampret	`// Generic synchronous single-port RAM interface`
112			`clk, rst, ce, we, oe, addr, di, do`
113			`);`
114
115			`//`
116			`// Default address and data buses width`
117			`//`
118			`parameter aw = 9;`
119			`parameter dw = 20;`
120
121	1063	lampret	`ifdef OR1200_BIST
122	504	lampret	`//`
123	1063	lampret	`// RAM BIST`
124			`//`
125	1214	simons	`input mbist_si_i;`
126			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
127			`output mbist_so_o;`
128	1063	lampret	`endif
129
130			`//`
131	504	lampret	`// Generic synchronous single-port RAM interface`
132			`//`
133			`input clk; // Clock`
134			`input rst; // Reset`
135			`input ce; // Chip enable input`
136			`input we; // Write enable input`
137			`input oe; // Output enable input`
138			`input [aw-1:0] addr; // address bus inputs`
139			`input [dw-1:0] di; // input data bus`
140			`output [dw-1:0] do; // output data bus`
141
142			`//`
143			`// Internal wires and registers`
144			`//`
145			`wire [3:0] unconnected;`
146
147	1214	simons	`ifdef OR1200_ARTISAN_SSP
148			`else
149	1063	lampret	`ifdef OR1200_VIRTUALSILICON_SSP
150			`else
151			`ifdef OR1200_BIST
152	1214	simons	`assign mbist_so_o = mbist_si_i;`
153	1063	lampret	`endif
154			`endif
155	1214	simons	`endif
156	1063	lampret
157	504	lampret	`ifdef OR1200_ARTISAN_SSP
158
159			`//`
160			`// Instantiation of ASIC memory:`
161			`//`
162			`// Artisan Synchronous Single-Port RAM (ra1sh)`
163			`//`
164			`ifdef UNUSED
165			`art_hssp_512x20 #(dw, 1<<aw, aw) artisan_ssp(`
166			`else
167	1214	simons	`ifdef OR1200_BIST
168			`art_hssp_512x20_bist artisan_ssp(`
169			`else
170	504	lampret	`art_hssp_512x20 artisan_ssp(`
171			`endif
172	1214	simons	`endif
173			`ifdef OR1200_BIST
174			`// RAM BIST`
175			`.mbist_si_i(mbist_si_i),`
176			`.mbist_so_o(mbist_so_o),`
177			`.mbist_ctrl_i(mbist_ctrl_i),`
178			`endif
179			`.CLK(clk),`
180			`.CEN(~ce),`
181			`.WEN(~we),`
182			`.A(addr),`
183			`.D(di),`
184			`.OEN(~oe),`
185			`.Q(do)`
186	504	lampret	`);`
187
188			`else
189
190			`ifdef OR1200_AVANT_ATP
191
192			`//`
193			`// Instantiation of ASIC memory:`
194			`//`
195			`// Avant! Asynchronous Two-Port RAM`
196			`//`
197			`avant_atp avant_atp(`
198			`.web(~we),`
199			`.reb(),`
200			`.oeb(~oe),`
201			`.rcsb(),`
202			`.wcsb(),`
203			`.ra(addr),`
204			`.wa(addr),`
205			`.di(di),`
206			`.do(do)`
207			`);`
208
209			`else
210
211			`ifdef OR1200_VIRAGE_SSP
212
213			`//`
214			`// Instantiation of ASIC memory:`
215			`//`
216			`// Virage Synchronous 1-port R/W RAM`
217			`//`
218			`virage_ssp virage_ssp(`
219			`.clk(clk),`
220			`.adr(addr),`
221			`.d(di),`
222			`.we(we),`
223			`.oe(oe),`
224			`.me(ce),`
225			`.q(do)`
226			`);`
227
228			`else
229
230			`ifdef OR1200_VIRTUALSILICON_SSP
231
232			`//`
233			`// Instantiation of ASIC memory:`
234			`//`
235			`// Virtual Silicon Single-Port Synchronous SRAM`
236			`//`
237			`ifdef UNUSED
238			`vs_hdsp_512x20 #(1<<aw, aw-1, dw-1) vs_ssp(`
239			`else
240	1063	lampret	`ifdef OR1200_BIST
241			`vs_hdsp_512x20_bist vs_ssp(`
242			`else
243	504	lampret	`vs_hdsp_512x20 vs_ssp(`
244			`endif
245	1063	lampret	`endif
246			`ifdef OR1200_BIST
247			`// RAM BIST`
248	1214	simons	`.mbist_si_i(mbist_si_i),`
249			`.mbist_so_o(mbist_so_o),`
250			`.mbist_ctrl_i(mbist_ctrl_i),`
251	1063	lampret	`endif
252	504	lampret	`.CK(clk),`
253			`.ADR(addr),`
254			`.DI(di),`
255			`.WEN(~we),`
256			`.CEN(~ce),`
257			`.OEN(~oe),`
258			`.DOUT(do)`
259			`);`
260
261			`else
262
263			`ifdef OR1200_XILINX_RAMB4
264
265			`//`
266			`// Instantiation of FPGA memory:`
267			`//`
268			`// Virtex/Spartan2`
269			`//`
270
271			`//`
272			`// Block 0`
273			`//`
274			`RAMB4_S8 ramb4_s8_0(`
275			`.CLK(clk),`
276			`.RST(rst),`
277			`.ADDR(addr),`
278			`.DI(di[7:0]),`
279			`.EN(ce),`
280			`.WE(we),`
281			`.DO(do[7:0])`
282			`);`
283
284			`//`
285			`// Block 1`
286			`//`
287			`RAMB4_S8 ramb4_s8_1(`
288			`.CLK(clk),`
289			`.RST(rst),`
290			`.ADDR(addr),`
291			`.DI(di[15:8]),`
292			`.EN(ce),`
293			`.WE(we),`
294			`.DO(do[15:8])`
295			`);`
296
297			`//`
298			`// Block 2`
299			`//`
300			`RAMB4_S8 ramb4_s8_2(`
301			`.CLK(clk),`
302			`.RST(rst),`
303			`.ADDR(addr),`
304			`.DI({4'b0000, di[19:16]}),`
305			`.EN(ce),`
306			`.WE(we),`
307			`.DO({unconnected, do[19:16]})`
308			`);`
309
310			`else
311
312	1129	lampret	`ifdef OR1200_ALTERA_LPM
313
314	504	lampret	`//`
315	1129	lampret	`// Instantiation of FPGA memory:`
316			`//`
317			`// Altera LPM`
318			`//`
319			`// Added By Jamil Khatib`
320			`//`
321
322			`wire wr;`
323
324			`assign wr = ce & we;`
325
326			`initial $display("Using Altera LPM.");`
327
328			`lpm_ram_dq lpm_ram_dq_component (`
329			`.address(addr),`
330			`.inclock(clk),`
331			`.outclock(clk),`
332			`.data(di),`
333			`.we(wr),`
334			`.q(do)`
335			`);`
336
337			`defparam lpm_ram_dq_component.lpm_width = dw,`
338			`lpm_ram_dq_component.lpm_widthad = aw,`
339			`lpm_ram_dq_component.lpm_indata = "REGISTERED",`
340			`lpm_ram_dq_component.lpm_address_control = "REGISTERED",`
341			`lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",`
342			`lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";`
343			`// examplar attribute lpm_ram_dq_component NOOPT TRUE`
344
345			`else
346
347			`//`
348	504	lampret	`// Generic single-port synchronous RAM model`
349			`//`
350
351			`//`
352			`// Generic RAM's registers and wires`
353			`//`
354			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
355			`reg [dw-1:0] do_reg; // RAM data output register`
356
357			`//`
358			`// Data output drivers`
359			`//`
360	1129	lampret	`assign do = (oe) ? do_reg : {dw{1'b0}};`
361	504	lampret
362			`//`
363			`// RAM read and write`
364			`//`
365			`always @(posedge clk)`
366			`if (ce && !we)`
367			`do_reg <= #1 mem[addr];`
368			`else if (ce && we)`
369			`mem[addr] <= #1 di;`
370
371	1129	lampret	`endif // !OR1200_ALTERA_LPM
372	504	lampret	`endif // !OR1200_XILINX_RAMB4_S16
373			`endif // !OR1200_VIRTUALSILICON_SSP
374			`endif // !OR1200_VIRAGE_SSP
375			`endif // !OR1200_AVANT_ATP
376			`endif // !OR1200_ARTISAN_SSP
377
378			`endmodule`

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