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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Single-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage Single-Port Sync RAM                               ////
////  - Virtual Silicon Single-Port Sync RAM                      ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB4_S16                                   ////
////  - Altera LPM                                                ////
////                                                              ////
////  To Do:                                                      ////
////   - xilinx rams need external tri-state logic                ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2002/10/17 20:04:41  lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.7  2001/11/02 18:57:14  lampret
// Modified virtual silicon instantiations.
//
// Revision 1.6  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.5  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/30 05:38:02  lampret
// Adding empty directories required by HDL coding guidelines
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram_64x22(
`ifdef OR1200_BIST
        // RAM BIST
        scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
`endif
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, do
);
 
//
// Default address and data buses width
//
parameter aw = 6;
parameter dw = 22;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input                   scanb_rst,
                        scanb_si,
                        scanb_en,
                        scanb_clk;
output                  scanb_so;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input                   clk;    // Clock
input                   rst;    // Reset
input                   ce;     // Chip enable input
input                   we;     // Write enable input
input                   oe;     // Output enable input
input   [aw-1:0] addr;   // address bus inputs
input   [dw-1:0] di;     // input data bus
output  [dw-1:0] do;     // output data bus
 
//
// Internal wires and registers
//
wire    [9:0]            unconnected;
 
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_64x22 #(dw, 1<<aw, aw) artisan_ssp(
`else
art_hssp_64x22 artisan_ssp(
`endif
        .clk(clk),
        .cen(~ce),
        .wen(~we),
        .a(addr),
        .d(di),
        .oen(~oe),
        .q(do)
);
 
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .do(do)
);
 
`else
 
`ifdef OR1200_VIRAGE_SSP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
        .clk(clk),
        .adr(addr),
        .d(di),
        .we(we),
        .oe(oe),
        .me(ce),
        .q(do)
);
 
`else
 
`ifdef OR1200_VIRTUALSILICON_SSP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_64x22 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_64x22_bist vs_ssp(
`else
vs_hdsp_64x22 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .scanb_rst(scanb_rst),
        .scanb_si(scanb_si),
        .scanb_so(scanb_so),
        .scanb_en(scanb_en),
        .scanb_clk(scanb_clk),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di),
        .WEN(~we),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(do)
);
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S16 ramb4_s16_0(
        .CLK(clk),
        .RST(rst),
        .ADDR({2'b00, addr}),
        .DI(di[15:0]),
        .EN(ce),
        .WE(we),
        .DO(do[15:0])
);
 
//
// Block 1
//
RAMB4_S16 ramb4_s16_1(
        .CLK(clk),
        .RST(rst),
        .ADDR({2'b00, addr}),
        .DI({unconnected, di[21:16]}),
        .EN(ce),
        .WE(we),
        .DO({unconnected, do[21:16]})
);
 
`else
 
`ifdef OR1200_ALTERA_LPM
 
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
 
wire    wr;
 
assign  wr = ce & we;
 
initial $display("Using Altera LPM.");
 
lpm_ram_dq lpm_ram_dq_component (
        .address(addr),
        .inclock(clk),
        .outclock(clk),
        .data(di),
        .we(wr),
        .q(do)
);
 
defparam lpm_ram_dq_component.lpm_width = dw,
        lpm_ram_dq_component.lpm_widthad = aw,
        lpm_ram_dq_component.lpm_indata = "REGISTERED",
        lpm_ram_dq_component.lpm_address_control = "REGISTERED",
        lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
        lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
        // examplar attribute lpm_ram_dq_component NOOPT TRUE
 
`else
 
//
// Generic single-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [dw-1:0] do_reg;                 // RAM data output register
 
//
// Data output drivers
//
assign do = (oe) ? do_reg : {dw{1'b0}};
 
//
// RAM read and write
//
always @(posedge clk)
        if (ce && !we)
                do_reg <= #1 mem[addr];
        else if (ce && we)
                mem[addr] <= #1 di;
 
`endif  // !OR1200_ALTERA_LPM
`endif  // !OR1200_XILINX_RAMB4_S16
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRAGE_SSP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SSP
 
endmodule

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Single-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage Single-Port Sync RAM ////`
22			`//// - Virtual Silicon Single-Port Sync RAM ////`
23			`//// ////`
24			`//// Supported FPGA RAMs are: ////`
25			`//// - Xilinx Virtex RAMB4_S16 ////`
26	1129	lampret	`//// - Altera LPM ////`
27	504	lampret	`//// ////`
28			`//// To Do: ////`
29			`//// - xilinx rams need external tri-state logic ////`
30			`//// - fix avant! two-port ram ////`
31	1129	lampret	`//// - add additional RAMs ////`
32	504	lampret	`//// ////`
33			`//// Author(s): ////`
34			`//// - Damjan Lampret, lampret@opencores.org ////`
35			`//// ////`
36			`//////////////////////////////////////////////////////////////////////`
37			`//// ////`
38			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
39			`//// ////`
40			`//// This source file may be used and distributed without ////`
41			`//// restriction provided that this copyright statement is not ////`
42			`//// removed from the file and that any derivative work contains ////`
43			`//// the original copyright notice and the associated disclaimer. ////`
44			`//// ////`
45			`//// This source file is free software; you can redistribute it ////`
46			`//// and/or modify it under the terms of the GNU Lesser General ////`
47			`//// Public License as published by the Free Software Foundation; ////`
48			`//// either version 2.1 of the License, or (at your option) any ////`
49			`//// later version. ////`
50			`//// ////`
51			`//// This source is distributed in the hope that it will be ////`
52			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
53			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
54			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
55			`//// details. ////`
56			`//// ////`
57			`//// You should have received a copy of the GNU Lesser General ////`
58			`//// Public License along with this source; if not, download it ////`
59			`//// from http://www.opencores.org/lgpl.shtml ////`
60			`//// ////`
61			`//////////////////////////////////////////////////////////////////////`
62			`//`
63			`// CVS Revision History`
64			`//`
65			`// $Log: not supported by cvs2svn $`
66	1129	lampret	`// Revision 1.2 2002/10/17 20:04:41 lampret`
67			`// Added BIST scan. Special VS RAMs need to be used to implement BIST.`
68			`//`
69	1063	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
70			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
71			`//`
72	504	lampret	`// Revision 1.7 2001/11/02 18:57:14 lampret`
73			`// Modified virtual silicon instantiations.`
74			`//`
75			`// Revision 1.6 2001/10/21 17:57:16 lampret`
76			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
77			`//`
78			`// Revision 1.5 2001/10/14 13:12:09 lampret`
79			`// MP3 version.`
80			`//`
81			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
82			`// no message`
83			`//`
84			`// Revision 1.1 2001/08/09 13:39:33 lampret`
85			`// Major clean-up.`
86			`//`
87			`// Revision 1.2 2001/07/30 05:38:02 lampret`
88			`// Adding empty directories required by HDL coding guidelines`
89			`//`
90			`//`
91
92			`// synopsys translate_off`
93			`include "timescale.v"
94			`// synopsys translate_on`
95			`include "or1200_defines.v"
96
97			`module or1200_spram_64x22(`
98	1063	lampret	`ifdef OR1200_BIST
99			`// RAM BIST`
100			`scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,`
101			`endif
102	504	lampret	`// Generic synchronous single-port RAM interface`
103			`clk, rst, ce, we, oe, addr, di, do`
104			`);`
105
106			`//`
107			`// Default address and data buses width`
108			`//`
109			`parameter aw = 6;`
110			`parameter dw = 22;`
111
112	1063	lampret	`ifdef OR1200_BIST
113	504	lampret	`//`
114	1063	lampret	`// RAM BIST`
115			`//`
116			`input scanb_rst,`
117			`scanb_si,`
118			`scanb_en,`
119			`scanb_clk;`
120			`output scanb_so;`
121			`endif
122
123			`//`
124	504	lampret	`// Generic synchronous single-port RAM interface`
125			`//`
126			`input clk; // Clock`
127			`input rst; // Reset`
128			`input ce; // Chip enable input`
129			`input we; // Write enable input`
130			`input oe; // Output enable input`
131			`input [aw-1:0] addr; // address bus inputs`
132			`input [dw-1:0] di; // input data bus`
133			`output [dw-1:0] do; // output data bus`
134
135			`//`
136			`// Internal wires and registers`
137			`//`
138			`wire [9:0] unconnected;`
139
140	1063	lampret	`ifdef OR1200_VIRTUALSILICON_SSP
141			`else
142			`ifdef OR1200_BIST
143			`assign scanb_so = scanb_si;`
144			`endif
145			`endif
146
147	504	lampret	`ifdef OR1200_ARTISAN_SSP
148
149			`//`
150			`// Instantiation of ASIC memory:`
151			`//`
152			`// Artisan Synchronous Single-Port RAM (ra1sh)`
153			`//`
154			`ifdef UNUSED
155			`art_hssp_64x22 #(dw, 1<<aw, aw) artisan_ssp(`
156			`else
157			`art_hssp_64x22 artisan_ssp(`
158			`endif
159			`.clk(clk),`
160			`.cen(~ce),`
161			`.wen(~we),`
162			`.a(addr),`
163			`.d(di),`
164			`.oen(~oe),`
165			`.q(do)`
166			`);`
167
168			`else
169
170			`ifdef OR1200_AVANT_ATP
171
172			`//`
173			`// Instantiation of ASIC memory:`
174			`//`
175			`// Avant! Asynchronous Two-Port RAM`
176			`//`
177			`avant_atp avant_atp(`
178			`.web(~we),`
179			`.reb(),`
180			`.oeb(~oe),`
181			`.rcsb(),`
182			`.wcsb(),`
183			`.ra(addr),`
184			`.wa(addr),`
185			`.di(di),`
186			`.do(do)`
187			`);`
188
189			`else
190
191			`ifdef OR1200_VIRAGE_SSP
192
193			`//`
194			`// Instantiation of ASIC memory:`
195			`//`
196			`// Virage Synchronous 1-port R/W RAM`
197			`//`
198			`virage_ssp virage_ssp(`
199			`.clk(clk),`
200			`.adr(addr),`
201			`.d(di),`
202			`.we(we),`
203			`.oe(oe),`
204			`.me(ce),`
205			`.q(do)`
206			`);`
207
208			`else
209
210			`ifdef OR1200_VIRTUALSILICON_SSP
211
212			`//`
213			`// Instantiation of ASIC memory:`
214			`//`
215			`// Virtual Silicon Single-Port Synchronous SRAM`
216			`//`
217			`ifdef UNUSED
218			`vs_hdsp_64x22 #(1<<aw, aw-1, dw-1) vs_ssp(`
219			`else
220	1063	lampret	`ifdef OR1200_BIST
221			`vs_hdsp_64x22_bist vs_ssp(`
222			`else
223	504	lampret	`vs_hdsp_64x22 vs_ssp(`
224			`endif
225	1063	lampret	`endif
226			`ifdef OR1200_BIST
227			`// RAM BIST`
228			`.scanb_rst(scanb_rst),`
229			`.scanb_si(scanb_si),`
230			`.scanb_so(scanb_so),`
231			`.scanb_en(scanb_en),`
232			`.scanb_clk(scanb_clk),`
233			`endif
234	504	lampret	`.CK(clk),`
235			`.ADR(addr),`
236			`.DI(di),`
237			`.WEN(~we),`
238			`.CEN(~ce),`
239			`.OEN(~oe),`
240			`.DOUT(do)`
241			`);`
242
243			`else
244
245			`ifdef OR1200_XILINX_RAMB4
246
247			`//`
248			`// Instantiation of FPGA memory:`
249			`//`
250			`// Virtex/Spartan2`
251			`//`
252
253			`//`
254			`// Block 0`
255			`//`
256			`RAMB4_S16 ramb4_s16_0(`
257			`.CLK(clk),`
258			`.RST(rst),`
259			`.ADDR({2'b00, addr}),`
260			`.DI(di[15:0]),`
261			`.EN(ce),`
262			`.WE(we),`
263			`.DO(do[15:0])`
264			`);`
265
266			`//`
267			`// Block 1`
268			`//`
269			`RAMB4_S16 ramb4_s16_1(`
270			`.CLK(clk),`
271			`.RST(rst),`
272			`.ADDR({2'b00, addr}),`
273			`.DI({unconnected, di[21:16]}),`
274			`.EN(ce),`
275			`.WE(we),`
276			`.DO({unconnected, do[21:16]})`
277			`);`
278
279			`else
280
281	1129	lampret	`ifdef OR1200_ALTERA_LPM
282
283	504	lampret	`//`
284	1129	lampret	`// Instantiation of FPGA memory:`
285			`//`
286			`// Altera LPM`
287			`//`
288			`// Added By Jamil Khatib`
289			`//`
290
291			`wire wr;`
292
293			`assign wr = ce & we;`
294
295			`initial $display("Using Altera LPM.");`
296
297			`lpm_ram_dq lpm_ram_dq_component (`
298			`.address(addr),`
299			`.inclock(clk),`
300			`.outclock(clk),`
301			`.data(di),`
302			`.we(wr),`
303			`.q(do)`
304			`);`
305
306			`defparam lpm_ram_dq_component.lpm_width = dw,`
307			`lpm_ram_dq_component.lpm_widthad = aw,`
308			`lpm_ram_dq_component.lpm_indata = "REGISTERED",`
309			`lpm_ram_dq_component.lpm_address_control = "REGISTERED",`
310			`lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",`
311			`lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";`
312			`// examplar attribute lpm_ram_dq_component NOOPT TRUE`
313
314			`else
315
316			`//`
317	504	lampret	`// Generic single-port synchronous RAM model`
318			`//`
319
320			`//`
321			`// Generic RAM's registers and wires`
322			`//`
323			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
324			`reg [dw-1:0] do_reg; // RAM data output register`
325
326			`//`
327			`// Data output drivers`
328			`//`
329	1129	lampret	`assign do = (oe) ? do_reg : {dw{1'b0}};`
330	504	lampret
331			`//`
332			`// RAM read and write`
333			`//`
334			`always @(posedge clk)`
335			`if (ce && !we)`
336			`do_reg <= #1 mem[addr];`
337			`else if (ce && we)`
338			`mem[addr] <= #1 di;`
339
340	1129	lampret	`endif // !OR1200_ALTERA_LPM
341	504	lampret	`endif // !OR1200_XILINX_RAMB4_S16
342			`endif // !OR1200_VIRTUALSILICON_SSP
343			`endif // !OR1200_VIRAGE_SSP
344			`endif // !OR1200_AVANT_ATP
345			`endif // !OR1200_ARTISAN_SSP
346
347			`endmodule`

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