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/*******************************************************************************
 *   Copyright 1991, 1992, 1993 Integrated Device Technology Corp.
 *   All right reserved.
 *
 *   This program is proprietary and confidential information of
 *   IDT Corp. and may be used and disclosed only as authorized
 *   in a license agreement controlling such use and disclosure.
 *
 *   IDT reserves the right to make any changes to
 *   the product herein to improve function or design.
 *   IDT does not assume any liability arising out of
 *   the application or use of the product herein.
 *
 *   WARNING: The unlicensed shipping, mailing, or carring of this
 *   technical data outside the United States, or the unlicensed
 *   disclosure, by whatever means, through visits abroad, or the
 *   unlicensed disclosure to foreign national in the United States,
 *   may violate the United States criminal law.
 *
 *   File Name                 : idt71256sa15.v
 *   Function                  : 32Kx8-bit Asynchronous Static RAM
 *   Simulation Tool/Version   : Verilog 2.0
 *
 ******************************************************************************/
 
/*+ **************************** Internal Use Only *****************************
 *+   Revision History
 *+   Name              Version dd-mmm-yy   Notes
 *+   William Lam       0.1        Mar-94   Based on IDT71B256SA part
 *+   Martin Mueller    0.2      2-Sep-94   Updated to reflect IDT71256SA15 timing
 *+   Martin Mueller    0.3      6-Sep-94   Changed to 0.1nS time scale
 *+ ***************************************************************************/
 
/*******************************************************************************
 * Module Name: idt71256sa15
 * Description: 32Kx8 15nS Asynchronous Static RAM
 *
 *******************************************************************************/
`timescale 1ns/100ps
//`timescale 10ps/10ps
 
module idt71256sa15(data, addr, we_, oe_, cs_);
inout [7:0] data;
input [14:0] addr;
input we_, oe_, cs_;
 
//Read Cycle Parameters
parameter Taa  = 15; // address access time
parameter Tacs = 15; // cs_     access time
parameter Tclz =  4; // cs_ to output low Z time
parameter Tchz =  7; // cs_ to output high Z time
parameter Toe  =  7; // oe_ to output  time
parameter Tohz =  6; // oe_ to output Z time
parameter Toh  =  4; // data hold from adr change time
 
//Write Cycle Parameters
parameter Taw  = 10; // adr valid to end of write time
parameter Tcw  = 10; // cs_ to end of write time
parameter Tas  =  0; // address set up time
parameter Twp  = 10; // write pulse width min
parameter Tdw  =  7; // data valid to end of writ time
parameter Tow  =  4; // data act from end of writ time
parameter Twhz =  6; // we_ to output in high Z time
 
reg [7:0] mem[0:32767];
 
time adr_chng,da_chng,we_fall,we_rise;
time cs_fall,cs_rise,oe_fall,oe_rise;
 
wire [7:0] data_in;
reg  [7:0] data_out;
reg  [7:0] temp1,temp2,temp3;
reg outen, out_en, in_en;
 
//integer i;
//initial begin
//    for (i=0; i<32768 ; i=i+4) begin
//       mem[i]   = 8'haa;
//       mem[i+1] = 8'hbb;
//       mem[i+2] = 8'hcc;
//       mem[i+3] = 8'hdd;
//     end 
//end
 
initial
  begin
       in_en = 1'b1;
    if (cs_)
       out_en = 1'b0;
  end
 
// input/output control logic
//---------------------------
assign data   = out_en ? data_out : 'hz;
assign data_in = in_en ? data : 'hz;
 
// read access
//------------
always @(addr)
      if (cs_==0 & we_==1)        //read
         #Taa data_out = mem[addr];
 
always @(addr)
  begin
     adr_chng = $time;
 
              outen  = 1'b0;
         #Toh out_en = outen;
 
//---------------------------------------------
      if (cs_==0 & we_==1)        //read
        begin
           if (oe_==0)
             begin
              outen = 1'b1;
              out_en = 1'b1;
             end
        end
//---------------------------------------------
     if (cs_==0 & we_==0)        //write
       begin
         if (oe_==0)
           begin
                outen = 1'b0;
                out_en = 1'b0;
                     temp1 = data_in;
            #Tdw mem[addr] = temp1;
           end
         else
           begin
                 outen = 1'b0;
                 out_en = 1'b0;
                  temp1 = data_in;
            #(Tdw-Toh) mem[addr] = temp1;
           end
 
         data_out = mem[addr];
       end
  end
 
always @(negedge cs_)
  begin
     cs_fall = $time;
 
     if (cs_fall - adr_chng < Tas)
         $display($time, "  Adr setup time is not enough Tas");
 
      if (we_==1 & oe_==0)
               outen  = 1'b1;
         #Tclz out_en = outen;
 
      if (we_==1)
         #(Tacs-Tclz) data_out = mem[addr];
 
      if (we_==0)
       begin
               outen = 1'b0;
               out_en = 1'b0;
                  temp2 = data_in;
         #Tdw mem[addr] = temp2;
       end
 
  end
 
always @(posedge cs_)
  begin
     cs_rise = $time;
 
   if (we_==0)
    begin
     if (cs_rise - adr_chng < Taw)
       begin
         mem[addr] = 8'hxx;
         $display($time, "  Adr valid to end of write is not enough Taw");
       end
 
     if (cs_rise - cs_fall < Tcw)
       begin
         mem[addr] = 8'hxx;
         $display($time, "  cs_ to end of write is not enough Tcw");
       end
 
     if (cs_rise - da_chng < Tdw)
       begin
         mem[addr] = 8'hxx;
         $display($time, "  Data setup is not enough");
       end
    end
 
               outen  = 1'b0;
         #Tchz out_en = outen;
 
  end
 
always @(negedge oe_)
  begin
     oe_fall = $time;
 
         data_out = mem[addr];
 
      if (we_==1 & cs_==0)
              outen  = 1'b1;
         #Toe out_en = outen;
  end
 
always @(posedge oe_)
  begin
     oe_rise = $time;
 
               outen  = 1'b0;
         #Tohz out_en = outen;
  end
 
// write to ram
//-------------
always @(negedge we_)
  begin
     we_fall = $time;
 
     if (we_fall - adr_chng < Tas)
         $display($time, "  Address set-up to WE low is not enough");
 
     if (cs_==0 & oe_==0)
       begin
               outen  = 1'b0;
         #Twhz out_en = outen;
                  temp3 = data_in;
         #Tdw mem[addr] = temp3;
 
              data_out = mem[addr];
       end
 
     if (cs_==0 & oe_==1)
       begin
               outen = 1'b0;
               out_en = 1'b0;
                  temp3 = data_in;
         #Tdw mem[addr] = temp3;
 
              data_out = mem[addr];
       end
  end
 
always @(posedge we_)
  begin
     we_rise = $time;
 
   if (cs_==0)
    begin
     if (we_rise - da_chng < Tdw)
       begin
         mem[addr] = 8'hxx;
         $display($time, "  Data setup is not enough");
       end
     if (we_rise - adr_chng < Taw)
       begin
         mem[addr] = 8'hxx;
         $display($time, "  Addr setup is not enough");
       end
    end
   if (cs_==0 & oe_==0)
    begin
     if (we_rise - we_fall < (Twhz+Tdw) )
       begin
         mem[addr] = 8'hxx;
         $display($time, "  WE pulse width needs to be Twhz+Tdw");
       end
 
               outen  = 1'b1;
         #Tow  out_en = outen;
    end
   if (cs_==0 & oe_==1)
    begin
     if (we_rise - we_fall < Twp)
       begin
         mem[addr] = 8'hxx;
         $display($time, "  WE pulse width needs to be Twp");
       end
    end
  end
 
always @ (data)
  begin
     da_chng = $time;
 
     if (we_==0 & cs_==0)
       begin
            #Tdw mem[addr] = data_in;
 
                  data_out = mem[addr];
       end
  end
 
endmodule

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[/] [or1k/] [branches/] [mp3_stable/] [mp3/] [bench/] [models/] [idt71256sa15.v] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	266	lampret
2			`/*******************************************************************************`
3			`* Copyright 1991, 1992, 1993 Integrated Device Technology Corp.`
4			`* All right reserved.`
5			`*`
6			`* This program is proprietary and confidential information of`
7			`* IDT Corp. and may be used and disclosed only as authorized`
8			`* in a license agreement controlling such use and disclosure.`
9			`*`
10			`* IDT reserves the right to make any changes to`
11			`* the product herein to improve function or design.`
12			`* IDT does not assume any liability arising out of`
13			`* the application or use of the product herein.`
14			`*`
15			`* WARNING: The unlicensed shipping, mailing, or carring of this`
16			`* technical data outside the United States, or the unlicensed`
17			`* disclosure, by whatever means, through visits abroad, or the`
18			`* unlicensed disclosure to foreign national in the United States,`
19			`* may violate the United States criminal law.`
20			`*`
21			`* File Name : idt71256sa15.v`
22			`* Function : 32Kx8-bit Asynchronous Static RAM`
23			`* Simulation Tool/Version : Verilog 2.0`
24			`*`
25			`******************************************************************************/`
26
27			`/+ ************************* Internal Use Only ***************************`
28			`*+ Revision History`
29			`*+ Name Version dd-mmm-yy Notes`
30			`*+ William Lam 0.1 Mar-94 Based on IDT71B256SA part`
31			`*+ Martin Mueller 0.2 2-Sep-94 Updated to reflect IDT71256SA15 timing`
32			`*+ Martin Mueller 0.3 6-Sep-94 Changed to 0.1nS time scale`
33			`+ **************************************************************************/`
34
35			`/*******************************************************************************`
36			`* Module Name: idt71256sa15`
37			`* Description: 32Kx8 15nS Asynchronous Static RAM`
38			`*`
39			`*******************************************************************************/`
40			`timescale 1ns/100ps
41			//`timescale 10ps/10ps
42
43			`module idt71256sa15(data, addr, we_, oe_, cs_);`
44			`inout [7:0] data;`
45			`input [14:0] addr;`
46			`input we_, oe_, cs_;`
47
48			`//Read Cycle Parameters`
49			`parameter Taa = 15; // address access time`
50			`parameter Tacs = 15; // cs_ access time`
51			`parameter Tclz = 4; // cs_ to output low Z time`
52			`parameter Tchz = 7; // cs_ to output high Z time`
53			`parameter Toe = 7; // oe_ to output time`
54			`parameter Tohz = 6; // oe_ to output Z time`
55			`parameter Toh = 4; // data hold from adr change time`
56
57			`//Write Cycle Parameters`
58			`parameter Taw = 10; // adr valid to end of write time`
59			`parameter Tcw = 10; // cs_ to end of write time`
60			`parameter Tas = 0; // address set up time`
61			`parameter Twp = 10; // write pulse width min`
62			`parameter Tdw = 7; // data valid to end of writ time`
63			`parameter Tow = 4; // data act from end of writ time`
64			`parameter Twhz = 6; // we_ to output in high Z time`
65
66			`reg [7:0] mem[0:32767];`
67
68			`time adr_chng,da_chng,we_fall,we_rise;`
69			`time cs_fall,cs_rise,oe_fall,oe_rise;`
70
71			`wire [7:0] data_in;`
72			`reg [7:0] data_out;`
73			`reg [7:0] temp1,temp2,temp3;`
74			`reg outen, out_en, in_en;`
75
76			`//integer i;`
77			`//initial begin`
78			`// for (i=0; i<32768 ; i=i+4) begin`
79			`// mem[i] = 8'haa;`
80			`// mem[i+1] = 8'hbb;`
81			`// mem[i+2] = 8'hcc;`
82			`// mem[i+3] = 8'hdd;`
83			`// end`
84			`//end`
85
86			`initial`
87			`begin`
88			`in_en = 1'b1;`
89			`if (cs_)`
90			`out_en = 1'b0;`
91			`end`
92
93			`// input/output control logic`
94			`//---------------------------`
95			`assign data = out_en ? data_out : 'hz;`
96			`assign data_in = in_en ? data : 'hz;`
97
98			`// read access`
99			`//------------`
100			`always @(addr)`
101			`if (cs_==0 & we_==1) //read`
102			`#Taa data_out = mem[addr];`
103
104			`always @(addr)`
105			`begin`
106			`adr_chng = $time;`
107
108			`outen = 1'b0;`
109			`#Toh out_en = outen;`
110
111			`//---------------------------------------------`
112			`if (cs_==0 & we_==1) //read`
113			`begin`
114			`if (oe_==0)`
115			`begin`
116			`outen = 1'b1;`
117			`out_en = 1'b1;`
118			`end`
119			`end`
120			`//---------------------------------------------`
121			`if (cs_==0 & we_==0) //write`
122			`begin`
123			`if (oe_==0)`
124			`begin`
125			`outen = 1'b0;`
126			`out_en = 1'b0;`
127			`temp1 = data_in;`
128			`#Tdw mem[addr] = temp1;`
129			`end`
130			`else`
131			`begin`
132			`outen = 1'b0;`
133			`out_en = 1'b0;`
134			`temp1 = data_in;`
135			`#(Tdw-Toh) mem[addr] = temp1;`
136			`end`
137
138			`data_out = mem[addr];`
139			`end`
140			`end`
141
142			`always @(negedge cs_)`
143			`begin`
144			`cs_fall = $time;`
145
146			`if (cs_fall - adr_chng < Tas)`
147			`$display($time, " Adr setup time is not enough Tas");`
148
149			`if (we_==1 & oe_==0)`
150			`outen = 1'b1;`
151			`#Tclz out_en = outen;`
152
153			`if (we_==1)`
154			`#(Tacs-Tclz) data_out = mem[addr];`
155
156			`if (we_==0)`
157			`begin`
158			`outen = 1'b0;`
159			`out_en = 1'b0;`
160			`temp2 = data_in;`
161			`#Tdw mem[addr] = temp2;`
162			`end`
163
164			`end`
165
166			`always @(posedge cs_)`
167			`begin`
168			`cs_rise = $time;`
169
170			`if (we_==0)`
171			`begin`
172			`if (cs_rise - adr_chng < Taw)`
173			`begin`
174			`mem[addr] = 8'hxx;`
175			`$display($time, " Adr valid to end of write is not enough Taw");`
176			`end`
177
178			`if (cs_rise - cs_fall < Tcw)`
179			`begin`
180			`mem[addr] = 8'hxx;`
181			`$display($time, " cs_ to end of write is not enough Tcw");`
182			`end`
183
184			`if (cs_rise - da_chng < Tdw)`
185			`begin`
186			`mem[addr] = 8'hxx;`
187			`$display($time, " Data setup is not enough");`
188			`end`
189			`end`
190
191			`outen = 1'b0;`
192			`#Tchz out_en = outen;`
193
194			`end`
195
196			`always @(negedge oe_)`
197			`begin`
198			`oe_fall = $time;`
199
200			`data_out = mem[addr];`
201
202			`if (we_==1 & cs_==0)`
203			`outen = 1'b1;`
204			`#Toe out_en = outen;`
205			`end`
206
207			`always @(posedge oe_)`
208			`begin`
209			`oe_rise = $time;`
210
211			`outen = 1'b0;`
212			`#Tohz out_en = outen;`
213			`end`
214
215			`// write to ram`
216			`//-------------`
217			`always @(negedge we_)`
218			`begin`
219			`we_fall = $time;`
220
221			`if (we_fall - adr_chng < Tas)`
222			`$display($time, " Address set-up to WE low is not enough");`
223
224			`if (cs_==0 & oe_==0)`
225			`begin`
226			`outen = 1'b0;`
227			`#Twhz out_en = outen;`
228			`temp3 = data_in;`
229			`#Tdw mem[addr] = temp3;`
230
231			`data_out = mem[addr];`
232			`end`
233
234			`if (cs_==0 & oe_==1)`
235			`begin`
236			`outen = 1'b0;`
237			`out_en = 1'b0;`
238			`temp3 = data_in;`
239			`#Tdw mem[addr] = temp3;`
240
241			`data_out = mem[addr];`
242			`end`
243			`end`
244
245			`always @(posedge we_)`
246			`begin`
247			`we_rise = $time;`
248
249			`if (cs_==0)`
250			`begin`
251			`if (we_rise - da_chng < Tdw)`
252			`begin`
253			`mem[addr] = 8'hxx;`
254			`$display($time, " Data setup is not enough");`
255			`end`
256			`if (we_rise - adr_chng < Taw)`
257			`begin`
258			`mem[addr] = 8'hxx;`
259			`$display($time, " Addr setup is not enough");`
260			`end`
261			`end`
262			`if (cs_==0 & oe_==0)`
263			`begin`
264			`if (we_rise - we_fall < (Twhz+Tdw) )`
265			`begin`
266			`mem[addr] = 8'hxx;`
267			`$display($time, " WE pulse width needs to be Twhz+Tdw");`
268			`end`
269
270			`outen = 1'b1;`
271			`#Tow out_en = outen;`
272			`end`
273			`if (cs_==0 & oe_==1)`
274			`begin`
275			`if (we_rise - we_fall < Twp)`
276			`begin`
277			`mem[addr] = 8'hxx;`
278			`$display($time, " WE pulse width needs to be Twp");`
279			`end`
280			`end`
281			`end`
282
283			`always @ (data)`
284			`begin`
285			`da_chng = $time;`
286
287			`if (we_==0 & cs_==0)`
288			`begin`
289			`#Tdw mem[addr] = data_in;`
290
291			`data_out = mem[addr];`
292			`end`
293			`end`
294
295			`endmodule`