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/* $Id: C_GATE_BIT_V3_0.v,v 1.1.1.1 2001-11-04 19:00:04 lampret Exp $
--
-- Filename - C_GATE_BIT_V3_0.v
-- Author - Xilinx
-- Creation - 25 Jan 1999
--
-- Description - This file contains the Verilog behavior for the Baseblocks C_GATE_BIT_V3_0 module
*/
 
`ifdef C_GATE_BIT_V3_0_DEF
`else
`define C_GATE_BIT_V3_0_DEF
 
`ifdef C_REG_FD_V3_0_DEF
`else
`include "XilinxCoreLib/C_REG_FD_V3_0.v"
`endif
 
`define c_set 0
`define c_clear 1
`define c_override 0
`define c_no_override 1
`define c_and 0
`define c_nand 1
`define c_or 2
`define c_nor 3
`define c_xor 4
`define c_xnor 5
 
module C_GATE_BIT_V3_0 (I, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, O, Q);
 
        parameter C_AINIT_VAL           = "0";
        parameter C_ENABLE_RLOCS        = 0;
        parameter C_GATE_TYPE           = `c_and;
        parameter C_HAS_ACLR            = 0;
        parameter C_HAS_AINIT           = 0;
        parameter C_HAS_ASET            = 0;
        parameter C_HAS_CE                      = 0;
        parameter C_HAS_O                       = 0;
        parameter C_HAS_Q                       = 1;
        parameter C_HAS_SCLR            = 0;
        parameter C_HAS_SINIT           = 0;
        parameter C_HAS_SSET            = 0;
        parameter C_INPUTS                      = 2;
        parameter C_INPUT_INV_MASK      = "";
        parameter C_PIPE_STAGES         = 0;
        parameter C_SINIT_VAL           = "0";
        parameter C_SYNC_ENABLE         = `c_override;
        parameter C_SYNC_PRIORITY       = `c_clear;
 
 
        input [C_INPUTS-1 : 0] I;
        input CLK;
        input CE;
        input ACLR;
        input ASET;
        input AINIT;
        input SCLR;
        input SSET;
        input SINIT;
        output O;
        output Q;
 
        // Internal values to drive signals when input is missing
        wire intCE;
        reg intO;
        wire intQ;
        reg lastCLK;
 
        reg [C_PIPE_STAGES+2 : 0] intQpipe;
        reg intQpipeend;
 
        wire Q = (C_HAS_Q == 1 ? intQ : 1'bx);
        wire O = (C_HAS_O == 1 ? intO : 1'bx);
 
        // Sort out default values for missing ports
 
        assign intCE = defval(CE, C_HAS_CE, 1);
 
        integer j;
        integer pipe;
 
        reg [C_INPUTS-1 : 0] tmpsig;
        reg tmpres;
 
        // Output register
        C_REG_FD_V3_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
                           C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
                           C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
                reg1 (.D(intQpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
                          .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
                          .Q(intQ));
 
        initial
        begin
 
                #1;
 
                intQpipe = 'b0;
 
                if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate?
                        tmpres = 1;
                else
                        tmpres = 0;
 
                tmpsig = to_bits(C_INPUT_INV_MASK);
 
                for(j = 0; j < C_INPUTS; j = j + 1)
                begin
                        if(tmpsig[j] == 1)
                        begin
                                if(C_GATE_TYPE == 0) // AND gate
                                begin
                                        if(I[j] !== 1'bx)
                                                tmpres = tmpres & ~I[j];
                                        else if(tmpres === 1'b1)
                                                tmpres = 1'bx;
                                end
                                else if(C_GATE_TYPE == 1) // NAND gate
                                begin
                                        if(I[j] !== 1'bx)
                                                tmpres = tmpres & ~I[j];
                                        else if(tmpres === 1'b1)
                                                tmpres = 1'bx;
                                end
                                else if(C_GATE_TYPE == 2) // OR gate
                                begin
                                        if(I[j] !== 1'bx)
                                                tmpres = tmpres | ~I[j];
                                        else if(tmpres === 1'b0)
                                                tmpres = 1'bx;
                                end
                                else if(C_GATE_TYPE == 3) // NOR gate
                                begin
                                        if(I[j] !== 1'bx)
                                                tmpres = tmpres | ~I[j];
                                        else if(tmpres === 1'b0)
                                                tmpres = 1'bx;
                                end
                                else if(C_GATE_TYPE == 4) // XOR gate
                                begin
                                        if(I[j] !== 1'bx)
                                                tmpres = tmpres ^ ~I[j];
                                        else
                                                tmpres = 1'bx;
                                end
                                else if(C_GATE_TYPE == 5) // XNOR gate
                                begin
                                        if(I[j] !== 1'bx)
                                                tmpres = tmpres ^ ~I[j];
                                        else
                                                tmpres = 1'bx;
                                end
                        end
                        else // No input inversion on bit j of input    
                        begin
                                if(C_GATE_TYPE == 0) // AND gate
                                begin
                                        if(I[j] !== 1'bx)
                                                tmpres = tmpres & I[j];
                                        else if(tmpres === 1'b1)
                                                tmpres = 1'bx;
                                end
                                else if(C_GATE_TYPE == 1) // NAND gate
                                begin
                                        if(I[j] !== 1'bx)
                                                tmpres = tmpres & I[j];
                                        else if(tmpres === 1'b1)
                                                tmpres = 1'bx;
                                end
                                else if(C_GATE_TYPE == 2) // OR gate
                                begin
                                        if(I[j] !== 1'bx)
                                                tmpres = tmpres | I[j];
                                        else if(tmpres === 1'b0)
                                                tmpres = 1'bx;
                                end
                                else if(C_GATE_TYPE == 3) // NOR gate
                                begin
                                        if(I[j] !== 1'bx)
                                                tmpres = tmpres | I[j];
                                        else if(tmpres === 1'b0)
                                                tmpres = 1'bx;
                                end
                                else if(C_GATE_TYPE == 4) // XOR gate
                                begin
                                        if(I[j] !== 1'bx)
                                                tmpres = tmpres ^ I[j];
                                        else
                                                tmpres = 1'bx;
                                end
                                else if(C_GATE_TYPE == 5) // XNOR gate
                                begin
                                        if(I[j] !== 1'bx)
                                                tmpres = tmpres ^ I[j];
                                        else
                                                tmpres = 1'bx;
                                end
                        end
                end
 
                if(C_GATE_TYPE == 1 || C_GATE_TYPE == 3 || C_GATE_TYPE == 5)
                        tmpres = ~tmpres;
 
                intO <= tmpres;
 
                if(C_PIPE_STAGES < 2) // No pipeline
                        intQpipeend = intO;
                else // Pipeline stages required
                begin
                        intQpipeend = intQpipe[2];
                end
        end
 
        always @(CLK)
                lastCLK <= CLK;
 
        always@(I)
        begin
                if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate?
                        tmpres = 1;
                else
                        tmpres = 0;
                for(j = 0; j < C_INPUTS; j = j + 1)
                begin
                        if(tmpsig[j] == 1)
                        begin
                                if(C_GATE_TYPE == 0) // AND gate
                                begin
                                        if(I[j] !== 1'bx)
                                                tmpres = tmpres & ~I[j];
                                        else if(tmpres === 1'b1)
                                                tmpres = 1'bx;
                                end
                                else if(C_GATE_TYPE == 1) // NAND gate
                                begin
                                        if(I[j] !== 1'bx)
                                                tmpres = tmpres & ~I[j];
                                        else if(tmpres === 1'b1)
                                                tmpres = 1'bx;
                                end
                                else if(C_GATE_TYPE == 2) // OR gate
                                begin
                                        if(I[j] !== 1'bx)
                                                tmpres = tmpres | ~I[j];
                                        else if(tmpres === 1'b0)
                                                tmpres = 1'bx;
                                end
                                else if(C_GATE_TYPE == 3) // NOR gate
                                begin
                                        if(I[j] !== 1'bx)
                                                tmpres = tmpres | ~I[j];
                                        else if(tmpres === 1'b0)
                                                tmpres = 1'bx;
                                end
                                else if(C_GATE_TYPE == 4) // XOR gate
                                begin
                                        if(I[j] !== 1'bx)
                                                tmpres = tmpres ^ ~I[j];
                                        else
                                                tmpres = 1'bx;
                                end
                                else if(C_GATE_TYPE == 5) // XNOR gate
                                begin
                                        if(I[j] !== 1'bx)
                                                tmpres = tmpres ^ ~I[j];
                                        else
                                                tmpres = 1'bx;
                                end
                        end
                        else // No input inversion on bit j of input    
                        begin
                                if(C_GATE_TYPE == 0) // AND gate
                                begin
                                        if(I[j] !== 1'bx)
                                                tmpres = tmpres & I[j];
                                        else if(tmpres === 1'b1)
                                                tmpres = 1'bx;
                                end
                                else if(C_GATE_TYPE == 1) // NAND gate
                                begin
                                        if(I[j] !== 1'bx)
                                                tmpres = tmpres & I[j];
                                        else if(tmpres === 1'b1)
                                                tmpres = 1'bx;
                                end
                                else if(C_GATE_TYPE == 2) // OR gate
                                begin
                                        if(I[j] !== 1'bx)
                                                tmpres = tmpres | I[j];
                                        else if(tmpres === 1'b0)
                                                tmpres = 1'bx;
                                end
                                else if(C_GATE_TYPE == 3) // NOR gate
                                begin
                                        if(I[j] !== 1'bx)
                                                tmpres = tmpres | I[j];
                                        else if(tmpres === 1'b0)
                                                tmpres = 1'bx;
                                end
                                else if(C_GATE_TYPE == 4) // XOR gate
                                begin
                                        if(I[j] !== 1'bx)
                                                tmpres = tmpres ^ I[j];
                                        else
                                                tmpres = 1'bx;
                                end
                                else if(C_GATE_TYPE == 5) // XNOR gate
                                begin
                                        if(I[j] !== 1'bx)
                                                tmpres = tmpres ^ I[j];
                                        else
                                                tmpres = 1'bx;
                                end
                        end
                end
 
                if(C_GATE_TYPE == 1 || C_GATE_TYPE == 3 || C_GATE_TYPE == 5)
                        tmpres = ~tmpres;
 
                intO <= #1 tmpres;
        end
 
        always@(posedge CLK)
        begin
                if(CLK === 1'b1 && lastCLK === 1'b0 && intCE === 1'b1) // OK! Update pipelines!
                begin
                        for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1)
                        begin
                                intQpipe[pipe] <= intQpipe[pipe+1];
                        end
                        intQpipe[C_PIPE_STAGES] <= intO;
                end
                else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || intCE === 1'bx) // POSSIBLY Update pipelines!
                begin
                        for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1)
                        begin
                                if(intQpipe[pipe] !== intQpipe[pipe+1])
                                        intQpipe[pipe] <= 1'bx;
                        end
                        if(intQpipe[C_PIPE_STAGES] !== intO)
                                intQpipe[C_PIPE_STAGES] <= 1'bx;
                end
        end
 
        always@(intO or intQpipe[2])
        begin
                if(C_PIPE_STAGES < 2) // No pipeline
                        intQpipeend <= intO;
                else // Pipeline stages required
                begin
                        intQpipeend <= intQpipe[2];
                end
        end
 
        function defval;
        input i;
        input hassig;
        input val;
                begin
                        if(hassig == 1)
                                defval = i;
                        else
                                defval = val;
                end
        endfunction
 
        function [C_INPUTS - 1 : 0] to_bits;
        input [C_INPUTS*8 : 1] instring;
        integer i;
        begin
                for(i = C_INPUTS; i > 0; i = i - 1)
                begin // Is this character a '0'? (ASCII = 48 = 00110000)
                        if(instring[(i*8)] == 0 &&
                                instring[(i*8)-1] == 0 &&
                                instring[(i*8)-2] == 1 &&
                                instring[(i*8)-3] == 1 &&
                                instring[(i*8)-4] == 0 &&
                                instring[(i*8)-5] == 0 &&
                                instring[(i*8)-6] == 0 &&
                                instring[(i*8)-7] == 0)
                                        to_bits[i-1] = 0;
                          // Or is it a '1'? 
                        else if(instring[(i*8)] == 0 &&
                                instring[(i*8)-1] == 0 &&
                                instring[(i*8)-2] == 1 &&
                                instring[(i*8)-3] == 1 &&
                                instring[(i*8)-4] == 0 &&
                                instring[(i*8)-5] == 0 &&
                                instring[(i*8)-6] == 0 &&
                                instring[(i*8)-7] == 1)
 
                                        to_bits[i-1] = 1;
                                  // Or is it a ' '? (a null char - in which case insert a '0')
                                else if(instring[(i*8)] == 0 &&
                                        instring[(i*8)-1] == 0 &&
                                        instring[(i*8)-2] == 0 &&
                                        instring[(i*8)-3] == 0 &&
                                        instring[(i*8)-4] == 0 &&
                                        instring[(i*8)-5] == 0 &&
                                        instring[(i*8)-6] == 0 &&
                                        instring[(i*8)-7] == 0)
                                                to_bits[i-1] = 0;
                        else
                        begin
                                $display("Error: non-binary digit in string \"%s\"\nExiting simulation...", instring);
                                $finish;
                        end
                end
        end
        endfunction
 
endmodule
 
`undef c_set
`undef c_clear
`undef c_override
`undef c_no_override
`undef c_and
`undef c_nand
`undef c_or
`undef c_nor
`undef c_xor
`undef c_xnor
 
`endif

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[/] [or1k/] [branches/] [mp3_stable/] [mp3/] [lib/] [xilinx/] [coregen/] [XilinxCoreLib/] [C_GATE_BIT_V3_0.v] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	266	lampret	`/* $Id: C_GATE_BIT_V3_0.v,v 1.1.1.1 2001-11-04 19:00:04 lampret Exp $`
2			`--`
3			`-- Filename - C_GATE_BIT_V3_0.v`
4			`-- Author - Xilinx`
5			`-- Creation - 25 Jan 1999`
6			`--`
7			`-- Description - This file contains the Verilog behavior for the Baseblocks C_GATE_BIT_V3_0 module`
8			`*/`
9
10			`ifdef C_GATE_BIT_V3_0_DEF
11			`else
12			`define C_GATE_BIT_V3_0_DEF
13
14			`ifdef C_REG_FD_V3_0_DEF
15			`else
16			`include "XilinxCoreLib/C_REG_FD_V3_0.v"
17			`endif
18
19			`define c_set 0
20			`define c_clear 1
21			`define c_override 0
22			`define c_no_override 1
23			`define c_and 0
24			`define c_nand 1
25			`define c_or 2
26			`define c_nor 3
27			`define c_xor 4
28			`define c_xnor 5
29
30			`module C_GATE_BIT_V3_0 (I, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, O, Q);`
31
32			`parameter C_AINIT_VAL = "0";`
33			`parameter C_ENABLE_RLOCS = 0;`
34			parameter C_GATE_TYPE = `c_and;
35			`parameter C_HAS_ACLR = 0;`
36			`parameter C_HAS_AINIT = 0;`
37			`parameter C_HAS_ASET = 0;`
38			`parameter C_HAS_CE = 0;`
39			`parameter C_HAS_O = 0;`
40			`parameter C_HAS_Q = 1;`
41			`parameter C_HAS_SCLR = 0;`
42			`parameter C_HAS_SINIT = 0;`
43			`parameter C_HAS_SSET = 0;`
44			`parameter C_INPUTS = 2;`
45			`parameter C_INPUT_INV_MASK = "";`
46			`parameter C_PIPE_STAGES = 0;`
47			`parameter C_SINIT_VAL = "0";`
48			parameter C_SYNC_ENABLE = `c_override;
49			parameter C_SYNC_PRIORITY = `c_clear;
50
51
52			`input [C_INPUTS-1 : 0] I;`
53			`input CLK;`
54			`input CE;`
55			`input ACLR;`
56			`input ASET;`
57			`input AINIT;`
58			`input SCLR;`
59			`input SSET;`
60			`input SINIT;`
61			`output O;`
62			`output Q;`
63
64			`// Internal values to drive signals when input is missing`
65			`wire intCE;`
66			`reg intO;`
67			`wire intQ;`
68			`reg lastCLK;`
69
70			`reg [C_PIPE_STAGES+2 : 0] intQpipe;`
71			`reg intQpipeend;`
72
73			`wire Q = (C_HAS_Q == 1 ? intQ : 1'bx);`
74			`wire O = (C_HAS_O == 1 ? intO : 1'bx);`
75
76			`// Sort out default values for missing ports`
77
78			`assign intCE = defval(CE, C_HAS_CE, 1);`
79
80			`integer j;`
81			`integer pipe;`
82
83			`reg [C_INPUTS-1 : 0] tmpsig;`
84			`reg tmpres;`
85
86			`// Output register`
87			`C_REG_FD_V3_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,`
88			`C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,`
89			`C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)`
90			`reg1 (.D(intQpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),`
91			`.AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),`
92			`.Q(intQ));`
93
94			`initial`
95			`begin`
96
97			`#1;`
98
99			`intQpipe = 'b0;`
100
101			`if(C_GATE_TYPE == 0 \|\| C_GATE_TYPE == 1) // AND or NAND gate?`
102			`tmpres = 1;`
103			`else`
104			`tmpres = 0;`
105
106			`tmpsig = to_bits(C_INPUT_INV_MASK);`
107
108			`for(j = 0; j < C_INPUTS; j = j + 1)`
109			`begin`
110			`if(tmpsig[j] == 1)`
111			`begin`
112			`if(C_GATE_TYPE == 0) // AND gate`
113			`begin`
114			`if(I[j] !== 1'bx)`
115			`tmpres = tmpres & ~I[j];`
116			`else if(tmpres === 1'b1)`
117			`tmpres = 1'bx;`
118			`end`
119			`else if(C_GATE_TYPE == 1) // NAND gate`
120			`begin`
121			`if(I[j] !== 1'bx)`
122			`tmpres = tmpres & ~I[j];`
123			`else if(tmpres === 1'b1)`
124			`tmpres = 1'bx;`
125			`end`
126			`else if(C_GATE_TYPE == 2) // OR gate`
127			`begin`
128			`if(I[j] !== 1'bx)`
129			`tmpres = tmpres \| ~I[j];`
130			`else if(tmpres === 1'b0)`
131			`tmpres = 1'bx;`
132			`end`
133			`else if(C_GATE_TYPE == 3) // NOR gate`
134			`begin`
135			`if(I[j] !== 1'bx)`
136			`tmpres = tmpres \| ~I[j];`
137			`else if(tmpres === 1'b0)`
138			`tmpres = 1'bx;`
139			`end`
140			`else if(C_GATE_TYPE == 4) // XOR gate`
141			`begin`
142			`if(I[j] !== 1'bx)`
143			`tmpres = tmpres ^ ~I[j];`
144			`else`
145			`tmpres = 1'bx;`
146			`end`
147			`else if(C_GATE_TYPE == 5) // XNOR gate`
148			`begin`
149			`if(I[j] !== 1'bx)`
150			`tmpres = tmpres ^ ~I[j];`
151			`else`
152			`tmpres = 1'bx;`
153			`end`
154			`end`
155			`else // No input inversion on bit j of input`
156			`begin`
157			`if(C_GATE_TYPE == 0) // AND gate`
158			`begin`
159			`if(I[j] !== 1'bx)`
160			`tmpres = tmpres & I[j];`
161			`else if(tmpres === 1'b1)`
162			`tmpres = 1'bx;`
163			`end`
164			`else if(C_GATE_TYPE == 1) // NAND gate`
165			`begin`
166			`if(I[j] !== 1'bx)`
167			`tmpres = tmpres & I[j];`
168			`else if(tmpres === 1'b1)`
169			`tmpres = 1'bx;`
170			`end`
171			`else if(C_GATE_TYPE == 2) // OR gate`
172			`begin`
173			`if(I[j] !== 1'bx)`
174			`tmpres = tmpres \| I[j];`
175			`else if(tmpres === 1'b0)`
176			`tmpres = 1'bx;`
177			`end`
178			`else if(C_GATE_TYPE == 3) // NOR gate`
179			`begin`
180			`if(I[j] !== 1'bx)`
181			`tmpres = tmpres \| I[j];`
182			`else if(tmpres === 1'b0)`
183			`tmpres = 1'bx;`
184			`end`
185			`else if(C_GATE_TYPE == 4) // XOR gate`
186			`begin`
187			`if(I[j] !== 1'bx)`
188			`tmpres = tmpres ^ I[j];`
189			`else`
190			`tmpres = 1'bx;`
191			`end`
192			`else if(C_GATE_TYPE == 5) // XNOR gate`
193			`begin`
194			`if(I[j] !== 1'bx)`
195			`tmpres = tmpres ^ I[j];`
196			`else`
197			`tmpres = 1'bx;`
198			`end`
199			`end`
200			`end`
201
202			`if(C_GATE_TYPE == 1 \|\| C_GATE_TYPE == 3 \|\| C_GATE_TYPE == 5)`
203			`tmpres = ~tmpres;`
204
205			`intO <= tmpres;`
206
207			`if(C_PIPE_STAGES < 2) // No pipeline`
208			`intQpipeend = intO;`
209			`else // Pipeline stages required`
210			`begin`
211			`intQpipeend = intQpipe[2];`
212			`end`
213			`end`
214
215			`always @(CLK)`
216			`lastCLK <= CLK;`
217
218			`always@(I)`
219			`begin`
220			`if(C_GATE_TYPE == 0 \|\| C_GATE_TYPE == 1) // AND or NAND gate?`
221			`tmpres = 1;`
222			`else`
223			`tmpres = 0;`
224			`for(j = 0; j < C_INPUTS; j = j + 1)`
225			`begin`
226			`if(tmpsig[j] == 1)`
227			`begin`
228			`if(C_GATE_TYPE == 0) // AND gate`
229			`begin`
230			`if(I[j] !== 1'bx)`
231			`tmpres = tmpres & ~I[j];`
232			`else if(tmpres === 1'b1)`
233			`tmpres = 1'bx;`
234			`end`
235			`else if(C_GATE_TYPE == 1) // NAND gate`
236			`begin`
237			`if(I[j] !== 1'bx)`
238			`tmpres = tmpres & ~I[j];`
239			`else if(tmpres === 1'b1)`
240			`tmpres = 1'bx;`
241			`end`
242			`else if(C_GATE_TYPE == 2) // OR gate`
243			`begin`
244			`if(I[j] !== 1'bx)`
245			`tmpres = tmpres \| ~I[j];`
246			`else if(tmpres === 1'b0)`
247			`tmpres = 1'bx;`
248			`end`
249			`else if(C_GATE_TYPE == 3) // NOR gate`
250			`begin`
251			`if(I[j] !== 1'bx)`
252			`tmpres = tmpres \| ~I[j];`
253			`else if(tmpres === 1'b0)`
254			`tmpres = 1'bx;`
255			`end`
256			`else if(C_GATE_TYPE == 4) // XOR gate`
257			`begin`
258			`if(I[j] !== 1'bx)`
259			`tmpres = tmpres ^ ~I[j];`
260			`else`
261			`tmpres = 1'bx;`
262			`end`
263			`else if(C_GATE_TYPE == 5) // XNOR gate`
264			`begin`
265			`if(I[j] !== 1'bx)`
266			`tmpres = tmpres ^ ~I[j];`
267			`else`
268			`tmpres = 1'bx;`
269			`end`
270			`end`
271			`else // No input inversion on bit j of input`
272			`begin`
273			`if(C_GATE_TYPE == 0) // AND gate`
274			`begin`
275			`if(I[j] !== 1'bx)`
276			`tmpres = tmpres & I[j];`
277			`else if(tmpres === 1'b1)`
278			`tmpres = 1'bx;`
279			`end`
280			`else if(C_GATE_TYPE == 1) // NAND gate`
281			`begin`
282			`if(I[j] !== 1'bx)`
283			`tmpres = tmpres & I[j];`
284			`else if(tmpres === 1'b1)`
285			`tmpres = 1'bx;`
286			`end`
287			`else if(C_GATE_TYPE == 2) // OR gate`
288			`begin`
289			`if(I[j] !== 1'bx)`
290			`tmpres = tmpres \| I[j];`
291			`else if(tmpres === 1'b0)`
292			`tmpres = 1'bx;`
293			`end`
294			`else if(C_GATE_TYPE == 3) // NOR gate`
295			`begin`
296			`if(I[j] !== 1'bx)`
297			`tmpres = tmpres \| I[j];`
298			`else if(tmpres === 1'b0)`
299			`tmpres = 1'bx;`
300			`end`
301			`else if(C_GATE_TYPE == 4) // XOR gate`
302			`begin`
303			`if(I[j] !== 1'bx)`
304			`tmpres = tmpres ^ I[j];`
305			`else`
306			`tmpres = 1'bx;`
307			`end`
308			`else if(C_GATE_TYPE == 5) // XNOR gate`
309			`begin`
310			`if(I[j] !== 1'bx)`
311			`tmpres = tmpres ^ I[j];`
312			`else`
313			`tmpres = 1'bx;`
314			`end`
315			`end`
316			`end`
317
318			`if(C_GATE_TYPE == 1 \|\| C_GATE_TYPE == 3 \|\| C_GATE_TYPE == 5)`
319			`tmpres = ~tmpres;`
320
321			`intO <= #1 tmpres;`
322			`end`
323
324			`always@(posedge CLK)`
325			`begin`
326			`if(CLK === 1'b1 && lastCLK === 1'b0 && intCE === 1'b1) // OK! Update pipelines!`
327			`begin`
328			`for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1)`
329			`begin`
330			`intQpipe[pipe] <= intQpipe[pipe+1];`
331			`end`
332			`intQpipe[C_PIPE_STAGES] <= intO;`
333			`end`
334			`else if((CLK === 1'bx && lastCLK === 1'b0) \|\| (CLK === 1'b1 && lastCLK === 1'bx) \|\| intCE === 1'bx) // POSSIBLY Update pipelines!`
335			`begin`
336			`for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1)`
337			`begin`
338			`if(intQpipe[pipe] !== intQpipe[pipe+1])`
339			`intQpipe[pipe] <= 1'bx;`
340			`end`
341			`if(intQpipe[C_PIPE_STAGES] !== intO)`
342			`intQpipe[C_PIPE_STAGES] <= 1'bx;`
343			`end`
344			`end`
345
346			`always@(intO or intQpipe[2])`
347			`begin`
348			`if(C_PIPE_STAGES < 2) // No pipeline`
349			`intQpipeend <= intO;`
350			`else // Pipeline stages required`
351			`begin`
352			`intQpipeend <= intQpipe[2];`
353			`end`
354			`end`
355
356			`function defval;`
357			`input i;`
358			`input hassig;`
359			`input val;`
360			`begin`
361			`if(hassig == 1)`
362			`defval = i;`
363			`else`
364			`defval = val;`
365			`end`
366			`endfunction`
367
368			`function [C_INPUTS - 1 : 0] to_bits;`
369			`input [C_INPUTS*8 : 1] instring;`
370			`integer i;`
371			`begin`
372			`for(i = C_INPUTS; i > 0; i = i - 1)`
373			`begin // Is this character a '0'? (ASCII = 48 = 00110000)`
374			`if(instring[(i*8)] == 0 &&`
375			`instring[(i*8)-1] == 0 &&`
376			`instring[(i*8)-2] == 1 &&`
377			`instring[(i*8)-3] == 1 &&`
378			`instring[(i*8)-4] == 0 &&`
379			`instring[(i*8)-5] == 0 &&`
380			`instring[(i*8)-6] == 0 &&`
381			`instring[(i*8)-7] == 0)`
382			`to_bits[i-1] = 0;`
383			`// Or is it a '1'?`
384			`else if(instring[(i*8)] == 0 &&`
385			`instring[(i*8)-1] == 0 &&`
386			`instring[(i*8)-2] == 1 &&`
387			`instring[(i*8)-3] == 1 &&`
388			`instring[(i*8)-4] == 0 &&`
389			`instring[(i*8)-5] == 0 &&`
390			`instring[(i*8)-6] == 0 &&`
391			`instring[(i*8)-7] == 1)`
392
393			`to_bits[i-1] = 1;`
394			`// Or is it a ' '? (a null char - in which case insert a '0')`
395			`else if(instring[(i*8)] == 0 &&`
396			`instring[(i*8)-1] == 0 &&`
397			`instring[(i*8)-2] == 0 &&`
398			`instring[(i*8)-3] == 0 &&`
399			`instring[(i*8)-4] == 0 &&`
400			`instring[(i*8)-5] == 0 &&`
401			`instring[(i*8)-6] == 0 &&`
402			`instring[(i*8)-7] == 0)`
403			`to_bits[i-1] = 0;`
404			`else`
405			`begin`
406			`$display("Error: non-binary digit in string \"%s\"\nExiting simulation...", instring);`
407			`$finish;`
408			`end`
409			`end`
410			`end`
411			`endfunction`
412
413			`endmodule`
414
415			`undef c_set
416			`undef c_clear
417			`undef c_override
418			`undef c_no_override
419			`undef c_and
420			`undef c_nand
421			`undef c_or
422			`undef c_nor
423			`undef c_xor
424			`undef c_xnor
425
426			`endif