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/* $Id: C_REG_FD_V3_0.v,v 1.1.1.1 2001-11-04 19:00:04 lampret Exp $
--
-- Filename - C_REG_FD_V3_0.v
-- Author - Xilinx
-- Creation - 21 Oct 1998
--
-- Description - This file contains the Verilog behavior for the baseblocks C_REG_FD_V3_0 module
*/
 
`ifdef C_REG_FD_V3_0_DEF
`else
`define C_REG_FD_V3_0_DEF
 
`define c_set 0
`define c_clear 1
`define c_override 0
`define c_no_override 1
 
`define all1s {C_WIDTH{1'b1}}
`define all0s 'b0
`define allXs {C_WIDTH{1'bx}}
 
module C_REG_FD_V3_0 (D, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, Q);
 
        parameter C_AINIT_VAL           = "";
        parameter C_ENABLE_RLOCS        = 1;
        parameter C_HAS_ACLR            = 0;
        parameter C_HAS_AINIT           = 0;
        parameter C_HAS_ASET            = 0;
        parameter C_HAS_CE                      = 0;
        parameter C_HAS_SCLR            = 0;
        parameter C_HAS_SINIT           = 0;
        parameter C_HAS_SSET            = 0;
        parameter C_SINIT_VAL           = "";
        parameter C_SYNC_ENABLE         = `c_override;
        parameter C_SYNC_PRIORITY       = `c_clear;
        parameter C_WIDTH                       = 16;
 
 
        input [C_WIDTH-1 : 0] D;
        input CLK;
        input CE;
        input ACLR;
        input ASET;
        input AINIT;
        input SCLR;
        input SSET;
        input SINIT;
        output [C_WIDTH-1 : 0] Q;
 
        reg [C_WIDTH-1 : 0] data;
        reg [C_WIDTH-1 : 0] datatmp;
        // Internal values to drive signals when input is missing
        wire intCE;
        wire intACLR;
        wire intASET;
        wire intAINIT;
        wire intSCLR;
        wire intSSET;
        wire intSINIT;
        wire intCLK;
 
        wire [C_WIDTH-1 : 0] #1 Q = data;
 
        // Sort out default values for missing ports
 
        assign intCLK = CLK;
        assign intACLR = defval(ACLR, C_HAS_ACLR, 0);
        assign intASET = defval(ASET, C_HAS_ASET, 0);
        assign intAINIT = defval(AINIT, C_HAS_AINIT, 0);
        assign intSCLR = defval(SCLR, C_HAS_SCLR, 0);
        assign intSSET = defval(SSET, C_HAS_SSET, 0);
        assign intSINIT = defval(SINIT, C_HAS_SINIT, 0);
        assign intCE = ((((C_HAS_ACLR == 1 || C_HAS_ASET == 1 || C_HAS_AINIT == 1) &&
                                        (C_HAS_SCLR == 1 || C_HAS_SSET == 1 || C_HAS_SINIT == 1)) ||
                                        (C_HAS_SCLR == 1 && C_HAS_SSET == 1 && C_SYNC_PRIORITY == `c_set)) &&
                                        (C_HAS_CE == 1) && (C_SYNC_ENABLE == `c_override) ?
                                                (CE | intSCLR | intSSET | intSINIT) : ((C_HAS_CE == 1) ? CE : 1'b1));
 
        reg lastCLK;
        reg lastintACLR;
        reg lastintASET;
 
        reg [C_WIDTH-1 : 0] AIV;
        reg [C_WIDTH-1 : 0] SIV;
 
 
        integer i;
        integer ASYNC_CTRL;
 
        initial
        begin
                ASYNC_CTRL <= 1;
                lastCLK = #1 1'b0;
                lastintACLR <= 1'b0;
                lastintASET <= 1'b0;
                AIV = to_bits(C_AINIT_VAL);
                SIV = to_bits(C_SINIT_VAL);
                if(C_HAS_ACLR === 1)
                        data <= #1 `all0s;
                else if(C_HAS_ASET === 1)
                        data <= #1 `all1s;
                else if(C_HAS_AINIT === 1)
                    data <= #1 AIV;
                else if(C_HAS_SCLR === 1)
                        data <= #1 `all0s;
                else if(C_HAS_SSET === 1)
                        data <= #1 `all1s;
                else if(C_HAS_SINIT === 1)
                        data <= #1 SIV;
                else
                        data <= #1 AIV;
        end
 
        always@(posedge intCLK or intCE or intACLR or intASET or intAINIT)
        begin
                datatmp = data;
 
                for(i = 0; i < C_WIDTH; i = i + 1)
                begin
                        if(intACLR === 1'b1)
                                datatmp[i] = 1'b0;
                        else if(intACLR === 1'b0 && intASET === 1'b1)
                                datatmp[i] = 1'b1;
                        else if(intAINIT === 1'b1)
                                datatmp[i] = AIV[i];
                        else if(intACLR === 1'bx && intASET !== 1'b0)
                                datatmp[i] = 1'bx;
                        else if(intACLR != lastintACLR && lastintASET != intASET
                                                && lastintACLR === 1'b1 && lastintASET === 1'b1
                                                && intACLR === 1'b0 && intASET === 1'b0)
                                datatmp[i] = 1'bx;
                        else
                        begin
                                ASYNC_CTRL = 0;
                                if(lastCLK !== intCLK && lastCLK === 1'b0 && intCLK === 1'b1)
                                begin
                                        if((intCE !== 1'b0 || C_SYNC_ENABLE === 0) &&
                                                (C_SYNC_PRIORITY == 0 && intSSET === 1'bx && intSCLR !== 1'b0))
                                        begin
                                                datatmp[i] = 1'bx;
                                                ASYNC_CTRL = 1;
                                        end
                                        if((intCE !== 1'b0 || C_SYNC_ENABLE === 0) &&
                                        (C_SYNC_PRIORITY == 1 && intSSET !== 1'b0 && intSCLR === 1'bx))
                                        begin
                                                datatmp[i] = 1'bx;
                                                ASYNC_CTRL = 1;
                                        end
                                        if(intCE === 1'b1 && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0)
                                                datatmp[i] = D[i];
                                        else if(intCE === 1'bx && datatmp[i] !== D[i] && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0)
                                                datatmp[i] = 1'bx;
 
                                        if(intSINIT === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0) && ASYNC_CTRL == 0)
                                                datatmp[i] = SIV[i];
                                        else if(intSINIT === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== SIV[i])
                                                datatmp[i] = 1'bx;
                                        else if(intSINIT === 1'bx && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== SIV[i])
                                                datatmp[i] = 1'bx;
 
                                        if(intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0) && ASYNC_CTRL == 0)
                                                datatmp[i] = 1'b0;
                                        else if(intSCLR === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== 1'b0 && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0))
                                                datatmp[i] = 1'bx;
                                        else if(intSCLR === 1'bx && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== 1'b0 && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0))
                                                datatmp[i] = 1'bx;
 
                                        if(intSSET === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0) && ASYNC_CTRL == 0)
                                                datatmp[i] = 1'b1;
                                        else if(intSSET === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== 1'b1 && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0))
                                                datatmp[i] = 1'bx;
                                        else if(intSSET === 1'bx && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== 1'b1 && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0))
                                                datatmp[i] = 1'bx;
                                end
                                else if(lastCLK !== intCLK && ((lastCLK === 1'b0 && intCLK === 1'bx)
                                                        || (lastCLK === 1'bx && intCLK === 1'b1)))
                                begin
                                        if((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 && intSSET === 1'bx && intSCLR !== 1'b0))
                                                datatmp[i] = 1'bx;
                                        else if((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 && intSSET !== 1'b0 && intSCLR === 1'bx))
                                                datatmp[i] = 1'bx;
 
                                        if(intCE !== 1'b0 && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && datatmp[i] !== D[i])
                                                datatmp[i] = 1'bx;
 
                                        if(intSINIT !== 1'b0 && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== SIV[i])
                                                datatmp[i] = 1'bx;
 
                                        if(intSCLR !== 1'b0 && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0) && datatmp[i] !== 1'b0)
                                                datatmp[i] = 1'bx;
 
                                        if(intSSET !== 1'b0 && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0) && datatmp[i] !== 1'b1)
                                                datatmp[i] = 1'bx;
                                end
 
                                if(intACLR === 1'b0 && intASET === 1'bx)
                                begin
                                        if(datatmp[i] !== 1'b1)
                                        begin
                                                datatmp[i] = 1'bx;
                                                ASYNC_CTRL = 1;
                                        end
                                end
                                else if(intACLR === 1'bx && intASET === 1'b0)
                                begin
                                        if(datatmp[i] !== 1'b0)
                                        begin
                                                datatmp[i] = 1'bx;
                                                ASYNC_CTRL = 1;
                                        end
                                end
                                else if(intAINIT === 1'bx)
                                begin
                                        if(datatmp[i] !== AIV[i])
                                        begin
                                                datatmp[i] = 1'bx;
                                                ASYNC_CTRL = 1;
                                        end
                                end
                        end
                end
 
                data <= datatmp;
        end
 
 
        always@(intACLR or intASET)
        begin
                lastintACLR <= intACLR;
                lastintASET <= intASET;
                if($time != 0)
                        if(intACLR === 1'b0 && intASET === 1'b0 && lastintACLR !== 1'b0 && lastintASET !== 1'b0) // RACE
                                data <= `allXs;
        end
 
        always@(intCLK)
                lastCLK <= intCLK;
 
 
        function defval;
        input i;
        input hassig;
        input val;
                begin
                        if(hassig == 1)
                                defval = i;
                        else
                                defval = val;
                end
        endfunction
 
        function [C_WIDTH - 1 : 0] to_bits;
        input [C_WIDTH*8 : 1] instring;
        integer i;
        integer non_null_string;
        begin
                non_null_string = 0;
                for(i = C_WIDTH; i > 0; i = i - 1)
                begin // Is the string empty?
                        if(instring[(i*8)] == 0 &&
                                instring[(i*8)-1] == 0 &&
                                instring[(i*8)-2] == 0 &&
                                instring[(i*8)-3] == 0 &&
                                instring[(i*8)-4] == 0 &&
                                instring[(i*8)-5] == 0 &&
                                instring[(i*8)-6] == 0 &&
                                instring[(i*8)-7] == 0 &&
                                non_null_string == 0)
                                        non_null_string = 0; // Use the return value to flag a non-empty string
                        else
                                        non_null_string = 1; // Non-null character!
                end
                if(non_null_string == 0) // String IS empty! Just return the value to be all '0's
                begin
                        for(i = C_WIDTH; i > 0; i = i - 1)
                                to_bits[i-1] = 0;
                end
                else
                begin
                        for(i = C_WIDTH; i > 0; i = i - 1)
                        begin // Is this character a '0'? (ASCII = 48 = 00110000)
                                if(instring[(i*8)] == 0 &&
                                        instring[(i*8)-1] == 0 &&
                                        instring[(i*8)-2] == 1 &&
                                        instring[(i*8)-3] == 1 &&
                                        instring[(i*8)-4] == 0 &&
                                        instring[(i*8)-5] == 0 &&
                                        instring[(i*8)-6] == 0 &&
                                        instring[(i*8)-7] == 0)
                                                to_bits[i-1] = 0;
                                  // Or is it a '1'? 
                                else if(instring[(i*8)] == 0 &&
                                        instring[(i*8)-1] == 0 &&
                                        instring[(i*8)-2] == 1 &&
                                        instring[(i*8)-3] == 1 &&
                                        instring[(i*8)-4] == 0 &&
                                        instring[(i*8)-5] == 0 &&
                                        instring[(i*8)-6] == 0 &&
                                        instring[(i*8)-7] == 1)
                                                to_bits[i-1] = 1;
                                  // Or is it a ' '? (a null char - in which case insert a '0')
                                else if(instring[(i*8)] == 0 &&
                                        instring[(i*8)-1] == 0 &&
                                        instring[(i*8)-2] == 0 &&
                                        instring[(i*8)-3] == 0 &&
                                        instring[(i*8)-4] == 0 &&
                                        instring[(i*8)-5] == 0 &&
                                        instring[(i*8)-6] == 0 &&
                                        instring[(i*8)-7] == 0)
                                                to_bits[i-1] = 0;
                                else
                                begin
                                        $display("Error: non-binary digit in string \"%s\"\nExiting simulation...", instring);
                                        $finish;
                                end
                        end
                end
        end
        endfunction
 
endmodule
 
`undef c_set
`undef c_clear
`undef c_override
`undef c_no_override
 
`undef all1s
`undef all0s
`undef allXs
 
`endif

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[/] [or1k/] [branches/] [mp3_stable/] [mp3/] [lib/] [xilinx/] [coregen/] [XilinxCoreLib/] [C_REG_FD_V3_0.v] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	266	lampret	`/* $Id: C_REG_FD_V3_0.v,v 1.1.1.1 2001-11-04 19:00:04 lampret Exp $`
2			`--`
3			`-- Filename - C_REG_FD_V3_0.v`
4			`-- Author - Xilinx`
5			`-- Creation - 21 Oct 1998`
6			`--`
7			`-- Description - This file contains the Verilog behavior for the baseblocks C_REG_FD_V3_0 module`
8			`*/`
9
10			`ifdef C_REG_FD_V3_0_DEF
11			`else
12			`define C_REG_FD_V3_0_DEF
13
14			`define c_set 0
15			`define c_clear 1
16			`define c_override 0
17			`define c_no_override 1
18
19			`define all1s {C_WIDTH{1'b1}}
20			`define all0s 'b0
21			`define allXs {C_WIDTH{1'bx}}
22
23			`module C_REG_FD_V3_0 (D, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, Q);`
24
25			`parameter C_AINIT_VAL = "";`
26			`parameter C_ENABLE_RLOCS = 1;`
27			`parameter C_HAS_ACLR = 0;`
28			`parameter C_HAS_AINIT = 0;`
29			`parameter C_HAS_ASET = 0;`
30			`parameter C_HAS_CE = 0;`
31			`parameter C_HAS_SCLR = 0;`
32			`parameter C_HAS_SINIT = 0;`
33			`parameter C_HAS_SSET = 0;`
34			`parameter C_SINIT_VAL = "";`
35			parameter C_SYNC_ENABLE = `c_override;
36			parameter C_SYNC_PRIORITY = `c_clear;
37			`parameter C_WIDTH = 16;`
38
39
40			`input [C_WIDTH-1 : 0] D;`
41			`input CLK;`
42			`input CE;`
43			`input ACLR;`
44			`input ASET;`
45			`input AINIT;`
46			`input SCLR;`
47			`input SSET;`
48			`input SINIT;`
49			`output [C_WIDTH-1 : 0] Q;`
50
51			`reg [C_WIDTH-1 : 0] data;`
52			`reg [C_WIDTH-1 : 0] datatmp;`
53			`// Internal values to drive signals when input is missing`
54			`wire intCE;`
55			`wire intACLR;`
56			`wire intASET;`
57			`wire intAINIT;`
58			`wire intSCLR;`
59			`wire intSSET;`
60			`wire intSINIT;`
61			`wire intCLK;`
62
63			`wire [C_WIDTH-1 : 0] #1 Q = data;`
64
65			`// Sort out default values for missing ports`
66
67			`assign intCLK = CLK;`
68			`assign intACLR = defval(ACLR, C_HAS_ACLR, 0);`
69			`assign intASET = defval(ASET, C_HAS_ASET, 0);`
70			`assign intAINIT = defval(AINIT, C_HAS_AINIT, 0);`
71			`assign intSCLR = defval(SCLR, C_HAS_SCLR, 0);`
72			`assign intSSET = defval(SSET, C_HAS_SSET, 0);`
73			`assign intSINIT = defval(SINIT, C_HAS_SINIT, 0);`
74			`assign intCE = ((((C_HAS_ACLR == 1 \|\| C_HAS_ASET == 1 \|\| C_HAS_AINIT == 1) &&`
75			`(C_HAS_SCLR == 1 \|\| C_HAS_SSET == 1 \|\| C_HAS_SINIT == 1)) \|\|`
76			(C_HAS_SCLR == 1 && C_HAS_SSET == 1 && C_SYNC_PRIORITY == `c_set)) &&
77			(C_HAS_CE == 1) && (C_SYNC_ENABLE == `c_override) ?
78			`(CE \| intSCLR \| intSSET \| intSINIT) : ((C_HAS_CE == 1) ? CE : 1'b1));`
79
80			`reg lastCLK;`
81			`reg lastintACLR;`
82			`reg lastintASET;`
83
84			`reg [C_WIDTH-1 : 0] AIV;`
85			`reg [C_WIDTH-1 : 0] SIV;`
86
87
88			`integer i;`
89			`integer ASYNC_CTRL;`
90
91			`initial`
92			`begin`
93			`ASYNC_CTRL <= 1;`
94			`lastCLK = #1 1'b0;`
95			`lastintACLR <= 1'b0;`
96			`lastintASET <= 1'b0;`
97			`AIV = to_bits(C_AINIT_VAL);`
98			`SIV = to_bits(C_SINIT_VAL);`
99			`if(C_HAS_ACLR === 1)`
100			data <= #1 `all0s;
101			`else if(C_HAS_ASET === 1)`
102			data <= #1 `all1s;
103			`else if(C_HAS_AINIT === 1)`
104			`data <= #1 AIV;`
105			`else if(C_HAS_SCLR === 1)`
106			data <= #1 `all0s;
107			`else if(C_HAS_SSET === 1)`
108			data <= #1 `all1s;
109			`else if(C_HAS_SINIT === 1)`
110			`data <= #1 SIV;`
111			`else`
112			`data <= #1 AIV;`
113			`end`
114
115			`always@(posedge intCLK or intCE or intACLR or intASET or intAINIT)`
116			`begin`
117			`datatmp = data;`
118
119			`for(i = 0; i < C_WIDTH; i = i + 1)`
120			`begin`
121			`if(intACLR === 1'b1)`
122			`datatmp[i] = 1'b0;`
123			`else if(intACLR === 1'b0 && intASET === 1'b1)`
124			`datatmp[i] = 1'b1;`
125			`else if(intAINIT === 1'b1)`
126			`datatmp[i] = AIV[i];`
127			`else if(intACLR === 1'bx && intASET !== 1'b0)`
128			`datatmp[i] = 1'bx;`
129			`else if(intACLR != lastintACLR && lastintASET != intASET`
130			`&& lastintACLR === 1'b1 && lastintASET === 1'b1`
131			`&& intACLR === 1'b0 && intASET === 1'b0)`
132			`datatmp[i] = 1'bx;`
133			`else`
134			`begin`
135			`ASYNC_CTRL = 0;`
136			`if(lastCLK !== intCLK && lastCLK === 1'b0 && intCLK === 1'b1)`
137			`begin`
138			`if((intCE !== 1'b0 \|\| C_SYNC_ENABLE === 0) &&`
139			`(C_SYNC_PRIORITY == 0 && intSSET === 1'bx && intSCLR !== 1'b0))`
140			`begin`
141			`datatmp[i] = 1'bx;`
142			`ASYNC_CTRL = 1;`
143			`end`
144			`if((intCE !== 1'b0 \|\| C_SYNC_ENABLE === 0) &&`
145			`(C_SYNC_PRIORITY == 1 && intSSET !== 1'b0 && intSCLR === 1'bx))`
146			`begin`
147			`datatmp[i] = 1'bx;`
148			`ASYNC_CTRL = 1;`
149			`end`
150			`if(intCE === 1'b1 && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0)`
151			`datatmp[i] = D[i];`
152			`else if(intCE === 1'bx && datatmp[i] !== D[i] && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0)`
153			`datatmp[i] = 1'bx;`
154
155			`if(intSINIT === 1'b1 && (intCE === 1'b1 \|\| C_SYNC_ENABLE == 0) && ASYNC_CTRL == 0)`
156			`datatmp[i] = SIV[i];`
157			`else if(intSINIT === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== SIV[i])`
158			`datatmp[i] = 1'bx;`
159			`else if(intSINIT === 1'bx && (intCE !== 1'b0 \|\| C_SYNC_ENABLE == 0) && datatmp[i] !== SIV[i])`
160			`datatmp[i] = 1'bx;`
161
162			`if(intSCLR === 1'b1 && (intCE === 1'b1 \|\| C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 \|\| intSSET === 1'b0) && ASYNC_CTRL == 0)`
163			`datatmp[i] = 1'b0;`
164			`else if(intSCLR === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== 1'b0 && (C_SYNC_PRIORITY == 1 \|\| intSSET === 1'b0))`
165			`datatmp[i] = 1'bx;`
166			`else if(intSCLR === 1'bx && (intCE !== 1'b0 \|\| C_SYNC_ENABLE == 0) && datatmp[i] !== 1'b0 && (C_SYNC_PRIORITY == 1 \|\| intSSET === 1'b0))`
167			`datatmp[i] = 1'bx;`
168
169			`if(intSSET === 1'b1 && (intCE === 1'b1 \|\| C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 \|\| intSCLR === 1'b0) && ASYNC_CTRL == 0)`
170			`datatmp[i] = 1'b1;`
171			`else if(intSSET === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== 1'b1 && (C_SYNC_PRIORITY == 0 \|\| intSCLR === 1'b0))`
172			`datatmp[i] = 1'bx;`
173			`else if(intSSET === 1'bx && (intCE !== 1'b0 \|\| C_SYNC_ENABLE == 0) && datatmp[i] !== 1'b1 && (C_SYNC_PRIORITY == 0 \|\| intSCLR === 1'b0))`
174			`datatmp[i] = 1'bx;`
175			`end`
176			`else if(lastCLK !== intCLK && ((lastCLK === 1'b0 && intCLK === 1'bx)`
177			`\|\| (lastCLK === 1'bx && intCLK === 1'b1)))`
178			`begin`
179			`if((intCE !== 1'b0 \|\| C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 && intSSET === 1'bx && intSCLR !== 1'b0))`
180			`datatmp[i] = 1'bx;`
181			`else if((intCE !== 1'b0 \|\| C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 && intSSET !== 1'b0 && intSCLR === 1'bx))`
182			`datatmp[i] = 1'bx;`
183
184			`if(intCE !== 1'b0 && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && datatmp[i] !== D[i])`
185			`datatmp[i] = 1'bx;`
186
187			`if(intSINIT !== 1'b0 && (intCE !== 1'b0 \|\| C_SYNC_ENABLE == 0) && datatmp[i] !== SIV[i])`
188			`datatmp[i] = 1'bx;`
189
190			`if(intSCLR !== 1'b0 && (intCE !== 1'b0 \|\| C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 \|\| intSSET === 1'b0) && datatmp[i] !== 1'b0)`
191			`datatmp[i] = 1'bx;`
192
193			`if(intSSET !== 1'b0 && (intCE !== 1'b0 \|\| C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 \|\| intSCLR === 1'b0) && datatmp[i] !== 1'b1)`
194			`datatmp[i] = 1'bx;`
195			`end`
196
197			`if(intACLR === 1'b0 && intASET === 1'bx)`
198			`begin`
199			`if(datatmp[i] !== 1'b1)`
200			`begin`
201			`datatmp[i] = 1'bx;`
202			`ASYNC_CTRL = 1;`
203			`end`
204			`end`
205			`else if(intACLR === 1'bx && intASET === 1'b0)`
206			`begin`
207			`if(datatmp[i] !== 1'b0)`
208			`begin`
209			`datatmp[i] = 1'bx;`
210			`ASYNC_CTRL = 1;`
211			`end`
212			`end`
213			`else if(intAINIT === 1'bx)`
214			`begin`
215			`if(datatmp[i] !== AIV[i])`
216			`begin`
217			`datatmp[i] = 1'bx;`
218			`ASYNC_CTRL = 1;`
219			`end`
220			`end`
221			`end`
222			`end`
223
224			`data <= datatmp;`
225			`end`
226
227
228			`always@(intACLR or intASET)`
229			`begin`
230			`lastintACLR <= intACLR;`
231			`lastintASET <= intASET;`
232			`if($time != 0)`
233			`if(intACLR === 1'b0 && intASET === 1'b0 && lastintACLR !== 1'b0 && lastintASET !== 1'b0) // RACE`
234			data <= `allXs;
235			`end`
236
237			`always@(intCLK)`
238			`lastCLK <= intCLK;`
239
240
241			`function defval;`
242			`input i;`
243			`input hassig;`
244			`input val;`
245			`begin`
246			`if(hassig == 1)`
247			`defval = i;`
248			`else`
249			`defval = val;`
250			`end`
251			`endfunction`
252
253			`function [C_WIDTH - 1 : 0] to_bits;`
254			`input [C_WIDTH*8 : 1] instring;`
255			`integer i;`
256			`integer non_null_string;`
257			`begin`
258			`non_null_string = 0;`
259			`for(i = C_WIDTH; i > 0; i = i - 1)`
260			`begin // Is the string empty?`
261			`if(instring[(i*8)] == 0 &&`
262			`instring[(i*8)-1] == 0 &&`
263			`instring[(i*8)-2] == 0 &&`
264			`instring[(i*8)-3] == 0 &&`
265			`instring[(i*8)-4] == 0 &&`
266			`instring[(i*8)-5] == 0 &&`
267			`instring[(i*8)-6] == 0 &&`
268			`instring[(i*8)-7] == 0 &&`
269			`non_null_string == 0)`
270			`non_null_string = 0; // Use the return value to flag a non-empty string`
271			`else`
272			`non_null_string = 1; // Non-null character!`
273			`end`
274			`if(non_null_string == 0) // String IS empty! Just return the value to be all '0's`
275			`begin`
276			`for(i = C_WIDTH; i > 0; i = i - 1)`
277			`to_bits[i-1] = 0;`
278			`end`
279			`else`
280			`begin`
281			`for(i = C_WIDTH; i > 0; i = i - 1)`
282			`begin // Is this character a '0'? (ASCII = 48 = 00110000)`
283			`if(instring[(i*8)] == 0 &&`
284			`instring[(i*8)-1] == 0 &&`
285			`instring[(i*8)-2] == 1 &&`
286			`instring[(i*8)-3] == 1 &&`
287			`instring[(i*8)-4] == 0 &&`
288			`instring[(i*8)-5] == 0 &&`
289			`instring[(i*8)-6] == 0 &&`
290			`instring[(i*8)-7] == 0)`
291			`to_bits[i-1] = 0;`
292			`// Or is it a '1'?`
293			`else if(instring[(i*8)] == 0 &&`
294			`instring[(i*8)-1] == 0 &&`
295			`instring[(i*8)-2] == 1 &&`
296			`instring[(i*8)-3] == 1 &&`
297			`instring[(i*8)-4] == 0 &&`
298			`instring[(i*8)-5] == 0 &&`
299			`instring[(i*8)-6] == 0 &&`
300			`instring[(i*8)-7] == 1)`
301			`to_bits[i-1] = 1;`
302			`// Or is it a ' '? (a null char - in which case insert a '0')`
303			`else if(instring[(i*8)] == 0 &&`
304			`instring[(i*8)-1] == 0 &&`
305			`instring[(i*8)-2] == 0 &&`
306			`instring[(i*8)-3] == 0 &&`
307			`instring[(i*8)-4] == 0 &&`
308			`instring[(i*8)-5] == 0 &&`
309			`instring[(i*8)-6] == 0 &&`
310			`instring[(i*8)-7] == 0)`
311			`to_bits[i-1] = 0;`
312			`else`
313			`begin`
314			`$display("Error: non-binary digit in string \"%s\"\nExiting simulation...", instring);`
315			`$finish;`
316			`end`
317			`end`
318			`end`
319			`end`
320			`endfunction`
321
322			`endmodule`
323
324			`undef c_set
325			`undef c_clear
326			`undef c_override
327			`undef c_no_override
328
329			`undef all1s
330			`undef all0s
331			`undef allXs
332
333			`endif