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lampret |
#Xilinx CORE Generator 3.1i_ip_update3: Project Manager (Do not edit)
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#Mon Aug 20 00:52:10 PDT 2001
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synchronous_dram_controller|nmi_electronics_ltd.|xc4000+virtex+spartan2|1.0=active
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accumulator|xilinx|virtex_all|1.0=inactive
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c8251_programmable_communications_interface|cast_inc.|virtex+spartan2|1.0=active
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c16450_universal_asynchronous_receiver_transmitter|cast_inc.|spartan2+virtex|1.0=active
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accumulator|xilinx|virtex_all+virtex2|2.0=inactive
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accumulator|xilinx|virtex_all+virtex2|3.0=inactive
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accumulator|xilinx|virtex_all+virtex2|4.0=active
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viewlogiclibraryalias=
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numerically_controlled_oscillator|xilinx|xc4000_all+virtex_all|1.1=active
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1024-pt_complex_fast_fourier_transform.|xilinx|virtex2|2.0=active
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fast_ethernet_mac_core_evaluation_board|coreel_microsystems|xc4000|1.0=active
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c2901_microprocessor_slice|cast_inc.|virtex+spartan2|1.0=active
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distributed_arithmetic_fir_filter|xilinx|virtex_all+virtex2|5.0=active
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distributed_arithmetic_fir_filter|xilinx|virtex_all+virtex2|3.0=inactive
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distributed_arithmetic_fir_filter|xilinx|virtex_all+virtex2|4.0=inactive
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8x8_multiplier|xilinx|xc4000_all|1.0=active
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xilinxfamily=Virtex
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three-input_multiplexer|xilinx|xc4000_all|1.0=active
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ld-based_parallel_latch|xilinx|virtex_all|1.0=inactive
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| 22 |
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xf_des_data_encryption_standard_engine_core|memec_design_services|xc4000+spartan|1.0=active
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asynchronous_fifo|xilinx|virtex_all+virtex2|3.0=active
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asynchronous_fifo|xilinx|virtex_all+virtex2|2.0=inactive
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1's_or_2's_complement|xilinx|xc4000_all|1.0=active
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des_-_triple_des_cryptoprocessor|xentec,_inc.|virtex+spartan2|1.0=active
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can_bus_interface|sican_microelectronics|xc4000|1.0=active
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registered_rom|xilinx|xc4000_all|1.0=active
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hdlc32|xilinx|virtex+spartan2|1.0=active
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sine-cosine_look-up_table|xilinx|xc4000_all+virtex_all|1.0=inactive
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fast_ethernet_mac_transmitter_&_receiver|coreel_microsystems|virtex+xc4000+++spartan2|1.0=active
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gva-220_dsp_hardware_accelerator|gv_&_associates_inc.|xc4000+spartan|1.0=active
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compact_uart|cast_inc.|virtex+spartan2|1.0=active
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square_root|xilinx|xc4000_all|1.0=active
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mux_slice_bufe|xilinx|virtex_all|1.0=active
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64-pt_complex_fast_fourier_transform|xilinx|virtex|1.0=active
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fd-based_shift_register|xilinx|virtex_all|1.0=inactive
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asynchronous_fifo|xilinx|virtex_all|1.0=inactive
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integrator|xilinx|xc4000_all|1.0=active
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cascaded_integrator_comb_filter|xilinx|virtex_all+virtex2|1.0=active
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multiply_accumulator|xilinx|virtex_all+virtex2|1.1=active
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multiply_accumulator|xilinx|virtex_all+virtex2|1.0=inactive
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16-pt_complex_fast_fourier_transform|xilinx|virtex|1.0=active
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cell_assembler_(cc201)|coreel_microsystems|xc4000|1.0=active
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interleaver-deinterleaver|cselt_s.p.a|virtex+spartan+spartan2|1.0=active
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designflow=Verilog
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fd-based_parallel_register|xilinx|virtex_all+virtex2|4.0=active
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fd-based_parallel_register|xilinx|virtex_all+virtex2|3.0=inactive
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fd-based_parallel_register|xilinx|virtex_all+virtex2|2.0=inactive
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variable_parallel_multiplier|xilinx|virtex_all+virtex2|2.0=active
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pci32_spartan_xl_interface|xilinx|spartan|1.0=active
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bus_multiplexer|xilinx|virtex_all|1.0=inactive
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bit_multiplexer|xilinx|virtex_all|1.0=inactive
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fileversion=2
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synchronous_fifo|xilinx|virtex_all+virtex2|1.0=inactive
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synchronous_fifo|xilinx|virtex_all+virtex2|2.0=active
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twos_complementer|xilinx|virtex_all+virtex2|4.0=active
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twos_complementer|xilinx|virtex_all+virtex2|3.0=inactive
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twos_complementer|xilinx|virtex_all+virtex2|2.0=inactive
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dual_port_block_memory|xilinx|virtex2+virtex_all|3.0=inactive
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dual_port_block_memory|xilinx|virtex2+virtex_all|3.1=active
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sine-cosine_look-up_table|xilinx|virtex_all+virtex2|3.0=active
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parallel_to_serial_converter|xilinx|xc4000_all|1.0=active
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256-pt_complex_fast_fourier_transform.|xilinx|virtex2|2.0=active
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sine-cosine_look-up_table|xilinx|virtex_all|2.1=inactive
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sine-cosine_look-up_table|xilinx|virtex_all|2.0=inactive
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block_memory_dual_port_virtex_ii|xilinx|virtex2|2.0=active
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ima-32_inverse_multiplexer_for_atm|applied_telecom,_inc.|xc4000+virtex|1.0=active
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arbiter|cselt_s.p.a|virtex+spartan+spartan2|1.0=active
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iss_adpcm|integrated_silicon_systems,_ltd.|virtex+spartan2|1.0=active
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xilinx_pci64_plus_64-bit_design_kit|xilinx|virtex|1.0=active
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32_point_parameterisable_complex_fast_fourier_transform|xilinx|virtex_all+virtex|1.0=active
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busformat=BusFormatParen
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vtoolsd_windows_device_driver_development_kit|xilinx|xc4000+spartan|1.0=active
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utopia_level-3_atm_transmitter|xentec,_inc.|virtex|1.0=active
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utopia_level-3_phy_transmitter|xentec,_inc.|virtex|1.0=active
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dvb_satellite_modulator_core|memec_design_services|virtex|1.0=active
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xilinx_reed-solomon_encoder|xilinx|virtex_all+xc4000+spartan|1.0=active
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xilinx_reed-solomon_decoder|xilinx|virtex_all+xc4000+spartan|1.0=active
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symmetric_16_deep_time_skew_buffer|xilinx|xc4000_all|1.0=active
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twos_complementer|xilinx|virtex_all|1.0=inactive
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pci32_virtex_interface|xilinx|virtex|1.0=active
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mt1f_t1_framer|virtual_ip_group,_inc|xc4000|1.0=active
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xf8279_programmable_keyboard_display_interface|memec_design_services|xc4000+spartan|1.0=active
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adpcm32|xilinx|virtex+spartan2|1.0=active
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| 86 |
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distributed_memory|xilinx|virtex_all+virtex2|2.0=inactive
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| 87 |
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distributed_memory|xilinx|virtex_all+virtex2|3.0=inactive
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| 88 |
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distributed_memory|xilinx|virtex_all+virtex2|4.0=active
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pci32_spartan_interface|xilinx|spartan|1.0=active
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binary_counter|xilinx|virtex_all|1.0=inactive
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iss_reed-solomon_encoder|integrated_silicon_systems,_ltd.|virtex+xc4000+spartan+spartan2|1.0=active
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iss_reed-solomon_decoder|integrated_silicon_systems,_ltd.|virtex+xc4000+spartan+spartan2|1.0=active
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direct_digital_synthesizer|xilinx|virtex_all+virtex2|3.0=active
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v8-urisc_8-bit_risc_microprocessor|vautomation|xc4000|1.0=active
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multiplexer_slice_buft|xilinx|virtex_all+virtex2|2.0=inactive
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multiplexer_slice_bufe|xilinx|virtex_all+virtex2|2.0=inactive
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multiplexer_slice_buft|xilinx|virtex_all+virtex2|3.0=inactive
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multiplexer_slice_bufe|xilinx|virtex_all+virtex2|3.0=inactive
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multiplexer_slice_buft|xilinx|virtex_all+virtex2|4.0=active
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multiplexer_slice_bufe|xilinx|virtex_all+virtex2|4.0=active
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gva-270_virtex-e_dsp_hardware_accelerator|gv_&_associates_inc.|virtex|1.0=active
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registered_scaled_adder|xilinx|xc4000_all|1.0=active
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bit_gate|xilinx|virtex_all|1.0=inactive
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bus_gate|xilinx|virtex_all|1.0=inactive
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ycrcb_to_rgb|perigee_llc|xc4000|1.0=active
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parallel_multiplier_-_area_optimized|xilinx|xc4000_all|1.0=active
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| 107 |
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cell_delineation_(cc200)|coreel_microsystems|xc4000|1.0=active
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| 108 |
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d80530_microcontroller|cast_inc.|virtex|1.0=active
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pipelined_delay_element|xilinx|xc4000_all|1.0=active
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ram-based_shift_register|xilinx|virtex_all+virtex2|4.0=active
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ram-based_shift_register|xilinx|virtex_all+virtex2|3.0=inactive
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ram-based_shift_register|xilinx|virtex_all+virtex2|2.0=inactive
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non-pipelined_constant_coefficient_multiplier|xilinx|xc4000_all|1.0=active
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| 114 |
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utopia_slave_(cc143s)|coreel_microsystems|virtex+xc4000+spartan+spartan2|1.0=active
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| 115 |
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distributed_sample_scrambler|cselt_s.p.a|virtex+spartan+spartan2|1.0=active
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| 116 |
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flip805x-pr_core|dolphin_integration|virtex+spartan2|1.0=active
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| 117 |
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noisy_transmission_channel_model|cselt_s.p.a|virtex+spartan+spartan2|1.0=active
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| 118 |
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m8259_programmable_interrupt_controller|virtual_ip_group,_inc|xc4000+spartan|1.0=active
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| 119 |
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des_cryptoprocessor|xentec,_inc.|virtex+spartan2|1.0=active
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| 120 |
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decode_8b/10b|xilinx|virtex_all+virtex2|2.0=active
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| 121 |
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decode_8b/10b|xilinx|virtex_all+virtex2|1.0=inactive
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| 122 |
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single_port_block_memory|xilinx|virtex_all+virtex2|3.1=active
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single_port_block_memory|xilinx|virtex_all+virtex2|3.0=inactive
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register|xilinx|xc4000_all|1.0=active
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simulationoutputproducts=Verilog
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pci32_spartan-ii_interface|xilinx|spartan2|1.0=active
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| 127 |
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sda_fir_filter|xilinx|xc4000_all|1.0=active
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| 128 |
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arc_32-bit_configurable_risc_processor|arc_cores|virtex+spartan2|1.0=active
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| 129 |
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microprocessor-based_core_evaluation_card|nmi_electronics_ltd.|xc4000|1.0=active
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| 130 |
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multiplier|xilinx|virtex_all+virtex2|3.0=active
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| 131 |
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multiplier|xilinx|virtex_all+virtex2|2.0=inactive
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| 132 |
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dynamic_constant_coefficient_multiplier|xilinx|virtex_all|1.0=inactive
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| 133 |
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non-symmetric_32_deep_time_skew_buffer|xilinx|xc4000_all|1.0=active
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corelibraryid=996502259468
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m16450_universal_asynchronous_receiver/transmitter|virtual_ip_group,_inc|xc4000+spartan|1.0=active
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| 136 |
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pipelined_divider|xilinx|xc4000_all+virtex_all+virtex2|2.0=active
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| 137 |
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adder_subtracter|xilinx|virtex_all+virtex2|4.0=active
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| 138 |
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adder_subtracter|xilinx|virtex_all+virtex2|3.0=inactive
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| 139 |
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adder_subtracter|xilinx|virtex_all+virtex2|2.0=inactive
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| 140 |
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200_mhz_sdram_controller|rapid_prototypes,_inc.|xc4000+virtex+spartan2|1.0=active
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| 141 |
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xf8255_programmable_peripheral_interface|memec_design_services|xc4000+spartan|1.0=active
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| 142 |
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12x12_multiplier|xilinx|xc4000_all|1.0=active
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| 143 |
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viterbi_decoder|cselt_s.p.a|virtex+spartan+spartan2|1.0=active
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| 144 |
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encode_8b/10b|xilinx|virtex_all+virtex2|1.0=active
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| 145 |
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m8254_programmable_timer|virtual_ip_group,_inc|virtex+spartan+spartan2|1.0=active
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| 146 |
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xf8250_asynchronous_communication_core(uart)|memec_design_services|xc4000+spartan|1.0=active
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| 147 |
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single-channel_xf-hdlc_controller|memec_design_services|xc4000+spartan+virtex+spartan2|1.0=active
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| 148 |
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fd-based_shift_register|xilinx|virtex_all+virtex2|4.0=active
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| 149 |
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fd-based_shift_register|xilinx|virtex_all+virtex2|3.0=inactive
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| 150 |
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fd-based_shift_register|xilinx|virtex_all+virtex2|2.0=inactive
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| 151 |
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distributed_memory|xilinx|virtex_all|1.0=inactive
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| 152 |
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crc10_generator_&_verifier_(cc-130)|coreel_microsystems|xc4000+spartan|1.0=active
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| 153 |
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crc32_generator_&_verifier_(cc-131)|coreel_microsystems|xc4000+spartan|1.0=active
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| 154 |
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registered_loadable_adder|xilinx|xc4000_all|1.0=active
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| 155 |
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compact_version_of_d80530_microcontroller|cast_inc.|virtex|1.0=active
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| 156 |
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registered_subtracter|xilinx|xc4000_all|1.0=active
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| 157 |
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256-pt_complex_fast_fourier_transform|xilinx|virtex|1.0=active
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| 158 |
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gva-100_dsp_prototyping_platform|gv_&_associates_inc.|xc4000|1.0=active
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| 159 |
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xilinx_pci64/66_virtex_interface|xilinx|virtex|1.0=active
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| 160 |
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utopia_master_(cc140f)|coreel_microsystems|xc4000|1.0=active
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| 161 |
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utopia_level-3_phy_receiver|xentec,_inc.|virtex|1.0=active
|
| 162 |
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utopia_level-3_atm_receiver|xentec,_inc.|virtex|1.0=active
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| 163 |
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memec_reed-solomon_encoder|memec_design_services|xc4000+virtex+spartan+spartan2|1.0=active
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| 164 |
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1024-pt_complex_fast_fourier_transform|xilinx|virtex|1.0=active
|
| 165 |
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gva-250_virtex_dsp_hardware_accelerator|gv_&_associates_inc.|virtex|1.0=active
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| 166 |
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bit_multiplexer|xilinx|virtex_all+virtex2|2.0=inactive
|
| 167 |
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bus_multiplexer|xilinx|virtex_all+virtex2|2.0=inactive
|
| 168 |
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bit_multiplexer|xilinx|virtex_all+virtex2|3.0=inactive
|
| 169 |
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|
bus_multiplexer|xilinx|virtex_all+virtex2|3.0=inactive
|
| 170 |
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bit_multiplexer|xilinx|virtex_all+virtex2|4.0=active
|
| 171 |
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bus_multiplexer|xilinx|virtex_all+virtex2|4.0=active
|
| 172 |
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adder_subtracter|xilinx|virtex_all|1.0=inactive
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| 173 |
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dynamic_constant_coefficient_multiplier|xilinx|virtex_all+virtex2|2.0=active
|
| 174 |
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flowvendor=Exemplar
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| 175 |
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registered_loadable_subtracter|xilinx|xc4000_all|1.0=active
|
| 176 |
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two-input_multiplexer|xilinx|xc4000_all|1.0=active
|
| 177 |
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variable_parallel_multiplier|xilinx|virtex_all|1.0=inactive
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| 178 |
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registered_dualport_ram|xilinx|xc4000_all|1.0=active
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| 179 |
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registered_serial_adder|xilinx|xc4000_all|1.0=active
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| 180 |
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distributed_sample_descrambler|cselt_s.p.a|virtex+spartan+spartan2|1.0=active
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| 181 |
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xf8256_multifunction_microprocessor_support_controller|memec_design_services|xc4000+spartan|1.0=active
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| 182 |
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c8259a_programmable_interrupt_controller|cast_inc.|virtex+spartan2|1.0=active
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| 183 |
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dct-idct_forward_and_inverse_discrete_cosine_transform|xentec,_inc.|virtex+spartan2|1.0=active
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| 184 |
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multiplexer_slice_buft|xilinx|virtex_all|1.0=inactive
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| 185 |
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dual_channel_numerically_controlled_oscillator|xilinx|xc4000_all+virtex_all|1.1=active
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| 186 |
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comparator|xilinx|virtex_all|1.0=inactive
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| 187 |
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registered_singleport_ram|xilinx|xc4000_all|1.0=active
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| 188 |
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gva-200a_dsp_hardware_accelerator|gv_&_associates_inc.|xc4000+spartan|1.0=active
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| 189 |
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registered_adder|xilinx|xc4000_all|1.0=active
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| 190 |
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64-pt_complex_fast_fourier_transform.|xilinx|virtex2|2.0=active
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| 191 |
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utopia_slave_(cc141)|coreel_microsystems|xc4000|1.0=active
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| 192 |
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rgb2ycrcb_color_space_converter|perigee_llc|xc4000+spartan+virtex+spartan2|1.0=active
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| 193 |
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bus_gate|xilinx|virtex_all+virtex2|4.0=active
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| 194 |
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bit_gate|xilinx|virtex_all+virtex2|4.0=active
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| 195 |
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bus_gate|xilinx|virtex_all+virtex2|3.0=inactive
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| 196 |
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bit_gate|xilinx|virtex_all+virtex2|3.0=inactive
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| 197 |
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bus_gate|xilinx|virtex_all+virtex2|2.0=inactive
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| 198 |
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bit_gate|xilinx|virtex_all+virtex2|2.0=inactive
|
| 199 |
|
|
fd-based_parallel_register|xilinx|virtex_all|1.0=inactive
|
| 200 |
|
|
binary_decoder|xilinx|virtex_all|1.0=inactive
|
| 201 |
|
|
distributed_arithmetic_fir_filter|xilinx|virtex_all|1.0=inactive
|
| 202 |
|
|
binary_counter|xilinx|virtex_all+virtex2|2.0=inactive
|
| 203 |
|
|
binary_counter|xilinx|virtex_all+virtex2|3.0=inactive
|
| 204 |
|
|
binary_counter|xilinx|virtex_all+virtex2|4.0=active
|
| 205 |
|
|
scaled_by_one-half_accumulator|xilinx|xc4000_all|1.0=active
|
| 206 |
|
|
block_memory_single_port_virtex_ii|xilinx|virtex2|2.0=active
|
| 207 |
|
|
pci64/66_spartan-ii_interface|xilinx|spartan2|1.0=active
|
| 208 |
|
|
pipelined_divider|xilinx|xc4000_all+virtex_all|1.0=inactive
|
| 209 |
|
|
ppp8_hdlc|coreel_microsystems|xc4000+virtex+spartan2|1.0=active
|
| 210 |
|
|
parallel_distributed_arithmetic_fir_filter|xilinx|xc4000_all|1.0=active
|
| 211 |
|
|
bit_bus_gate|xilinx|virtex_all+virtex2|2.0=inactive
|
| 212 |
|
|
bit_bus_gate|xilinx|virtex_all+virtex2|3.0=inactive
|
| 213 |
|
|
bit_bus_gate|xilinx|virtex_all+virtex2|4.0=active
|
| 214 |
|
|
m16550a_universal_asynchronous_receiver/transmitter_with_fifos|virtual_ip_group,_inc|xc4000+spartan|1.0=active
|
| 215 |
|
|
single_port_block_memory|xilinx|virtex+spartan2|1.0=inactive
|
| 216 |
|
|
jpeg_codec|xentec,_inc.|virtex|1.0=active
|
| 217 |
|
|
non-symmetric_16_deep_time_skew_buffer|xilinx|xc4000_all|1.0=active
|
| 218 |
|
|
c8255a_peripheral_interface|cast_inc.|virtex+spartan2|1.0=active
|
| 219 |
|
|
c16550_universal_asynchronous_receiver_transmitter_with_fifos|cast_inc.|spartan2+virtex|1.0=active
|
| 220 |
|
|
pipelined_constant_coefficient_multiplier|xilinx|xc4000_all|1.0=active
|
| 221 |
|
|
bit_correlator|xilinx|virtex_all+virtex2|2.0=active
|
| 222 |
|
|
convolutional_encoder|cselt_s.p.a|virtex+spartan+spartan2|1.0=active
|
| 223 |
|
|
16-pt_complex_fast_fourier_transform.|xilinx|virtex2|2.0=active
|
| 224 |
|
|
utopia_level-2_phy_side_rx_interface|cselt_s.p.a|virtex+spartan+spartan2|1.0=active
|
| 225 |
|
|
utopia_level-2_phy_side_tx_interface|cselt_s.p.a|virtex+spartan+spartan2|1.0=active
|
| 226 |
|
|
hdlc1|xilinx|virtex+spartan2|1.0=active
|
| 227 |
|
|
longitudinal_time_code_generator|deltatec|xc4000+virtex|1.0=active
|
| 228 |
|
|
m8237_dma_controller|virtual_ip_group,_inc|xc4000|1.0=active
|
| 229 |
|
|
ycrcb2rgb_color_space_converter|perigee_llc|xc4000+spartan+virtex+spartan2|1.0=active
|
| 230 |
|
|
xf-twsi_two-wire_serial_interface_master|memec_design_services|xc4000+spartan|1.0=active
|
| 231 |
|
|
ld-based_parallel_latch|xilinx|virtex_all+virtex2|4.0=active
|
| 232 |
|
|
ld-based_parallel_latch|xilinx|virtex_all+virtex2|3.0=inactive
|
| 233 |
|
|
ld-based_parallel_latch|xilinx|virtex_all+virtex2|2.0=inactive
|
| 234 |
|
|
c6850_asynchronous_communications_interface_adapter|cast_inc.|spartan2+virtex|1.0=active
|
| 235 |
|
|
synchronous_fifo|xilinx|xc4000_all|1.0=inactive
|
| 236 |
|
|
four-input_multiplexer|xilinx|xc4000_all|1.0=active
|
| 237 |
|
|
m8255_programmable_peripheral_interface|virtual_ip_group,_inc|virtex+spartan+spartan2|1.0=active
|
| 238 |
|
|
dual_port_block_memory|xilinx|virtex+spartan2|1.0=inactive
|
| 239 |
|
|
ima-8_inverse_multiplexer_for_atm|applied_telecom,_inc.|spartan2|1.0=active
|
| 240 |
|
|
content_addressable_memory|xilinx|virtex_all+virtex2|1.0=active
|
| 241 |
|
|
c2910a_microprogram_controller|cast_inc.|virtex+xc4000+spartan|1.0=active
|
| 242 |
|
|
binary_decoder|xilinx|virtex_all+virtex2|2.0=inactive
|
| 243 |
|
|
binary_decoder|xilinx|virtex_all+virtex2|3.0=inactive
|
| 244 |
|
|
binary_decoder|xilinx|virtex_all+virtex2|4.0=active
|
| 245 |
|
|
comb_filter|xilinx|xc4000_all|1.0=active
|
| 246 |
|
|
8051_compatible_high-speed_8-bit_risc_microcontroller|cast_inc.|virtex|1.0=active
|
| 247 |
|
|
ram-based_shift_register|xilinx|virtex_all|1.0=inactive
|
| 248 |
|
|
xf-twsi-ms_two-wire_serial_interface_master-slave|memec_design_services|virtex+spartan2+xc4000+spartan|1.0=active
|
| 249 |
|
|
comparator|xilinx|virtex_all+virtex2|2.0=inactive
|
| 250 |
|
|
comparator|xilinx|virtex_all+virtex2|3.0=inactive
|
| 251 |
|
|
comparator|xilinx|virtex_all+virtex2|4.0=active
|
| 252 |
|
|
memec_reed-solomon_decoder|memec_design_services|virtex+xc4000+spartan2|1.0=active
|
| 253 |
|
|
intellicore_prototyping_system|vautomation|xc4000|1.0=active
|
| 254 |
|
|
bit_bus_gate|xilinx|virtex_all|1.0=inactive
|
| 255 |
|
|
direct_digital_synthesizer|xilinx|virtex_all|2.0=inactive
|
