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// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/CY4_42.v,v 1.1.1.1 2001-11-04 18:59:47 lampret Exp $
 
/*
 
FUNCTION        : Carry modes functions
 
*/
 
`timescale  100 ps / 10 ps
 
`celldefine
 
module CY4_42 (C0, C1, C2, C3, C4, C5, C6, C7);
 
    parameter cds_action = "ignore";
 
    output C0, C1, C2, C3, C4, C5, C6, C7;
 
        supply0 C7;
        supply0 C6;
        supply0 C5;
        supply0 C4;
        supply0 C3;
        supply1 C2;
        supply0 C1;
        supply0 C0;
 
endmodule
 
`endcelldefine

Line No.	Rev	Author	Line
1	266	lampret	`// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/CY4_42.v,v 1.1.1.1 2001-11-04 18:59:47 lampret Exp $`
2
3			`/*`
4
5			`FUNCTION : Carry modes functions`
6
7			`*/`
8
9			`timescale 100 ps / 10 ps
10
11			`celldefine
12
13			`module CY4_42 (C0, C1, C2, C3, C4, C5, C6, C7);`
14
15			`parameter cds_action = "ignore";`
16
17			`output C0, C1, C2, C3, C4, C5, C6, C7;`
18
19			`supply0 C7;`
20			`supply0 C6;`
21			`supply0 C5;`
22			`supply0 C4;`
23			`supply0 C3;`
24			`supply1 C2;`
25			`supply0 C1;`
26			`supply0 C0;`
27
28			`endmodule`
29
30			`endcelldefine

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