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// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/NAND4B4.v,v 1.1.1.1 2001-11-04 18:59:49 lampret Exp $

/*

FUNCTION        : 4-INPUT NAND GATE

*/

`timescale  100 ps / 10 ps

`celldefine

module NAND4B4 (O, I0, I1, I2, I3);

    parameter cds_action = "ignore";

    output O;

    input  I0, I1, I2, I3;

    not N3 (i3_inv, I3);

    not N2 (i2_inv, I2);

    not N1 (i1_inv, I1);

    not N0 (i0_inv, I0);

    nand A1 (O, i0_inv, i1_inv, i2_inv, i3_inv);

    specify

        (I0 *> O) = (1, 1);

        (I1 *> O) = (1, 1);

        (I2 *> O) = (1, 1);

        (I3 *> O) = (1, 1);

    endspecify

endmodule

`endcelldefine