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[/] [or1k/] [branches/] [mp3_stable/] [mp3/] [lib/] [xilinx/] [unisims/] [RAM32X8S.v] - Blame information for rev 1765

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1 266 lampret 
// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/RAM32X8S.v,v 1.1.1.1 2001-11-04 18:59:50 lampret Exp $
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/*
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FUNCTION        : 32x8 Static RAM with synchronous write capability
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*/
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`timescale  100 ps / 10 ps
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`celldefine
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module RAM32X8S (O, A0, A1, A2, A3, A4, D, WCLK, WE);
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    parameter cds_action = "ignore";
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    parameter INIT_00 = 32'h00000000;
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    parameter INIT_01 = 32'h00000000;
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    parameter INIT_02 = 32'h00000000;
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    parameter INIT_03 = 32'h00000000;
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    parameter INIT_04 = 32'h00000000;
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    parameter INIT_05 = 32'h00000000;
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    parameter INIT_06 = 32'h00000000;
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    parameter INIT_07 = 32'h00000000;
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    output [7:0] O;
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    input  A0, A1, A2, A3, A4, WCLK, WE;
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    input [7:0] D;
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    reg  mem [256:0];
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    reg  [8:0] count;
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    wire [4:0] adr;
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    wire [7:0] d_in, o_out;
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    wire wclk_in, we_in;
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    buf b_d0   (d_in[0], D[0]);
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    buf b_d1   (d_in[1], D[1]);
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    buf b_d2   (d_in[2], D[2]);
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    buf b_d3   (d_in[3], D[3]);
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    buf b_d4   (d_in[4], D[4]);
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    buf b_d5   (d_in[5], D[5]);
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    buf b_d6   (d_in[6], D[6]);
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    buf b_d7   (d_in[7], D[7]);
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    buf b_wclk (wclk_in, WCLK);
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    buf b_we   (we_in, WE);
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    buf b_a4 (adr[4], A4);
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    buf b_a3 (adr[3], A3);
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    buf b_a2 (adr[2], A2);
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    buf b_a1 (adr[1], A1);
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    buf b_a0 (adr[0], A0);
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    buf b_o0 (O[0], o_out[0]);
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    buf b_o1 (O[1], o_out[1]);
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    buf b_o2 (O[2], o_out[2]);
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    buf b_o3 (O[3], o_out[3]);
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    buf b_o4 (O[4], o_out[4]);
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    buf b_o5 (O[5], o_out[5]);
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    buf b_o6 (O[6], o_out[6]);
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    buf b_o7 (O[7], o_out[7]);
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    buf b_o_out0 (o_out[0], mem[adr + 32 * 0]);
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    buf b_o_out1 (o_out[1], mem[adr + 32 * 1]);
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    buf b_o_out2 (o_out[2], mem[adr + 32 * 2]);
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    buf b_o_out3 (o_out[3], mem[adr + 32 * 3]);
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    buf b_o_out4 (o_out[4], mem[adr + 32 * 4]);
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    buf b_o_out5 (o_out[5], mem[adr + 32 * 5]);
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    buf b_o_out6 (o_out[6], mem[adr + 32 * 6]);
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    buf b_o_out7 (o_out[7], mem[adr + 32 * 7]);
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    initial begin
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        for (count = 0; count < 32; count = count + 1) begin
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            mem[count + 32 * 0] <= INIT_00[count];
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            mem[count + 32 * 1] <= INIT_01[count];
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            mem[count + 32 * 2] <= INIT_02[count];
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            mem[count + 32 * 3] <= INIT_03[count];
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            mem[count + 32 * 4] <= INIT_04[count];
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            mem[count + 32 * 5] <= INIT_05[count];
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            mem[count + 32 * 6] <= INIT_06[count];
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            mem[count + 32 * 7] <= INIT_07[count];
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        end
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    end
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    always @(posedge wclk_in) begin
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        if (we_in == 1'b1) begin
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            mem[adr + 32 * 0] <= d_in[0];
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            mem[adr + 32 * 1] <= d_in[1];
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            mem[adr + 32 * 2] <= d_in[2];
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            mem[adr + 32 * 3] <= d_in[3];
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            mem[adr + 32 * 4] <= d_in[4];
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            mem[adr + 32 * 5] <= d_in[5];
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            mem[adr + 32 * 6] <= d_in[6];
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            mem[adr + 32 * 7] <= d_in[7];
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        end
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    end
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    specify
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        if (WE)
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            (WCLK => O[0]) = (1, 1);
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        if (WE)
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            (WCLK => O[1]) = (1, 1);
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        if (WE)
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            (WCLK => O[2]) = (1, 1);
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        if (WE)
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            (WCLK => O[3]) = (1, 1);
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        if (WE)
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            (WCLK => O[4]) = (1, 1);
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        if (WE)
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            (WCLK => O[5]) = (1, 1);
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        if (WE)
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            (WCLK => O[6]) = (1, 1);
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        if (WE)
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            (WCLK => O[7]) = (1, 1);
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        (A4 => O[0]) = (1, 1);
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        (A3 => O[0]) = (1, 1);
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        (A2 => O[0]) = (1, 1);
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        (A1 => O[0]) = (1, 1);
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        (A0 => O[0]) = (1, 1);
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        (A4 => O[1]) = (1, 1);
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        (A3 => O[1]) = (1, 1);
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        (A2 => O[1]) = (1, 1);
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        (A1 => O[1]) = (1, 1);
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        (A0 => O[1]) = (1, 1);
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        (A4 => O[2]) = (1, 1);
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        (A3 => O[2]) = (1, 1);
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        (A2 => O[2]) = (1, 1);
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        (A1 => O[2]) = (1, 1);
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        (A0 => O[2]) = (1, 1);
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        (A4 => O[3]) = (1, 1);
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        (A3 => O[3]) = (1, 1);
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        (A2 => O[3]) = (1, 1);
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        (A1 => O[3]) = (1, 1);
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        (A0 => O[3]) = (1, 1);
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        (A4 => O[4]) = (1, 1);
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        (A3 => O[4]) = (1, 1);
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        (A2 => O[4]) = (1, 1);
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        (A1 => O[4]) = (1, 1);
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        (A0 => O[4]) = (1, 1);
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        (A4 => O[5]) = (1, 1);
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        (A3 => O[5]) = (1, 1);
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        (A2 => O[5]) = (1, 1);
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        (A1 => O[5]) = (1, 1);
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        (A0 => O[5]) = (1, 1);
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        (A4 => O[6]) = (1, 1);
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        (A3 => O[6]) = (1, 1);
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        (A2 => O[6]) = (1, 1);
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        (A1 => O[6]) = (1, 1);
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        (A0 => O[6]) = (1, 1);
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        (A4 => O[7]) = (1, 1);
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        (A3 => O[7]) = (1, 1);
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        (A2 => O[7]) = (1, 1);
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        (A1 => O[7]) = (1, 1);
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        (A0 => O[7]) = (1, 1);
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    endspecify
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endmodule
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`endcelldefine

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