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[/] [or1k/] [branches/] [mp3_stable/] [mp3/] [lib/] [xilinx/] [unisims/] [RAMB16_S36.v] - Blame information for rev 1765

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1 266 lampret 
// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/RAMB16_S36.v,v 1.1.1.1 2001-11-04 18:59:54 lampret Exp $
2 
 
3 
/*
4 
 
5 
FUNCTION        : 16x36 Block RAM with synchronous write capability
6 
 
7 
*/
8 
 
9 
`timescale  100 ps / 10 ps
10 
 
11 
`celldefine
12 
 
13 
module RAMB16_S36 (DO, DOP, ADDR, DI, DIP, EN, CLK, WE, SSR);
14 
 
15 
    parameter cds_action = "ignore";
16 
    parameter INIT = 36'h0;
17 
    parameter SRVAL = 36'h0;
18 
    parameter WRITE_MODE = "WRITE_FIRST";
19 
 
20 
    parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
21 
    parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
22 
    parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
23 
    parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
24 
    parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
25 
    parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
26 
    parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
27 
    parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
28 
    parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
29 
    parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
30 
    parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
31 
    parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
32 
    parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
33 
    parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
34 
    parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
35 
    parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
36 
    parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
37 
    parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
38 
    parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
39 
    parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
40 
    parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
41 
    parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
42 
    parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
43 
    parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
44 
    parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
45 
    parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
46 
    parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
47 
    parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
48 
    parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
49 
    parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
50 
    parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
51 
    parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
52 
    parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
53 
    parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
54 
    parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
55 
    parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
56 
    parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
57 
    parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
58 
    parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
59 
    parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
60 
    parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
61 
    parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
62 
    parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
63 
    parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
64 
    parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
65 
    parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
66 
    parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
67 
    parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
68 
    parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
69 
    parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
70 
    parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
71 
    parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
72 
    parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
73 
    parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
74 
    parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
75 
    parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
76 
    parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
77 
    parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
78 
    parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
79 
    parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
80 
    parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
81 
    parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
82 
    parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
83 
    parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
84 
    parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
85 
    parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
86 
    parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
87 
    parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
88 
    parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
89 
    parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
90 
    parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
91 
    parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
92 
 
93 
    output [31:0] DO;
94 
    output [3:0] DOP;
95 
    reg do0_out, do1_out, do2_out, do3_out, do4_out, do5_out, do6_out, do7_out, do8_out, do9_out, do10_out, do11_out, do12_out, do13_out, do14_out, do15_out, do16_out, do17_out, do18_out, do19_out, do20_out, do21_out, do22_out, do23_out, do24_out, do25_out, do26_out, do27_out, do28_out, do29_out, do30_out, do31_out;
96 
    reg dop0_out, dop1_out, dop2_out, dop3_out;
97 
 
98 
    input [8:0] ADDR;
99 
    input [31:0] DI;
100 
    input [3:0] DIP;
101 
    input EN, CLK, WE, SSR;
102 
 
103 
    reg [18431:0] mem;
104 
    reg [8:0] count;
105 
    reg [1:0] wr_mode;
106 
 
107 
    wire [8:0] addr_int;
108 
    wire [31:0] di_int;
109 
    wire [3:0] dip_int;
110 
    wire en_int, clk_int, we_int, ssr_int;
111 
 
112 
    tri0 GSR = glbl.GSR;
113 
 
114 
    always @(GSR)
115 
        if (GSR) begin
116 
            assign do0_out = INIT[0];
117 
            assign do1_out = INIT[1];
118 
            assign do2_out = INIT[2];
119 
            assign do3_out = INIT[3];
120 
            assign do4_out = INIT[4];
121 
            assign do5_out = INIT[5];
122 
            assign do6_out = INIT[6];
123 
            assign do7_out = INIT[7];
124 
            assign do8_out = INIT[8];
125 
            assign do9_out = INIT[9];
126 
            assign do10_out = INIT[10];
127 
            assign do11_out = INIT[11];
128 
            assign do12_out = INIT[12];
129 
            assign do13_out = INIT[13];
130 
            assign do14_out = INIT[14];
131 
            assign do15_out = INIT[15];
132 
            assign do16_out = INIT[16];
133 
            assign do17_out = INIT[17];
134 
            assign do18_out = INIT[18];
135 
            assign do19_out = INIT[19];
136 
            assign do20_out = INIT[20];
137 
            assign do21_out = INIT[21];
138 
            assign do22_out = INIT[22];
139 
            assign do23_out = INIT[23];
140 
            assign do24_out = INIT[24];
141 
            assign do25_out = INIT[25];
142 
            assign do26_out = INIT[26];
143 
            assign do27_out = INIT[27];
144 
            assign do28_out = INIT[28];
145 
            assign do29_out = INIT[29];
146 
            assign do30_out = INIT[30];
147 
            assign do31_out = INIT[31];
148 
            assign dop0_out = INIT[32];
149 
            assign dop1_out = INIT[33];
150 
            assign dop2_out = INIT[34];
151 
            assign dop3_out = INIT[35];
152 
        end
153 
        else begin
154 
            deassign do0_out;
155 
            deassign do1_out;
156 
            deassign do2_out;
157 
            deassign do3_out;
158 
            deassign do4_out;
159 
            deassign do5_out;
160 
            deassign do6_out;
161 
            deassign do7_out;
162 
            deassign do8_out;
163 
            deassign do9_out;
164 
            deassign do10_out;
165 
            deassign do11_out;
166 
            deassign do12_out;
167 
            deassign do13_out;
168 
            deassign do14_out;
169 
            deassign do15_out;
170 
            deassign do16_out;
171 
            deassign do17_out;
172 
            deassign do18_out;
173 
            deassign do19_out;
174 
            deassign do20_out;
175 
            deassign do21_out;
176 
            deassign do22_out;
177 
            deassign do23_out;
178 
            deassign do24_out;
179 
            deassign do25_out;
180 
            deassign do26_out;
181 
            deassign do27_out;
182 
            deassign do28_out;
183 
            deassign do29_out;
184 
            deassign do30_out;
185 
            deassign do31_out;
186 
            deassign dop0_out;
187 
            deassign dop1_out;
188 
            deassign dop2_out;
189 
            deassign dop3_out;
190 
        end
191 
 
192 
    buf b_do_out0 (DO[0], do0_out);
193 
    buf b_do_out1 (DO[1], do1_out);
194 
    buf b_do_out2 (DO[2], do2_out);
195 
    buf b_do_out3 (DO[3], do3_out);
196 
    buf b_do_out4 (DO[4], do4_out);
197 
    buf b_do_out5 (DO[5], do5_out);
198 
    buf b_do_out6 (DO[6], do6_out);
199 
    buf b_do_out7 (DO[7], do7_out);
200 
    buf b_do_out8 (DO[8], do8_out);
201 
    buf b_do_out9 (DO[9], do9_out);
202 
    buf b_do_out10 (DO[10], do10_out);
203 
    buf b_do_out11 (DO[11], do11_out);
204 
    buf b_do_out12 (DO[12], do12_out);
205 
    buf b_do_out13 (DO[13], do13_out);
206 
    buf b_do_out14 (DO[14], do14_out);
207 
    buf b_do_out15 (DO[15], do15_out);
208 
    buf b_do_out16 (DO[16], do16_out);
209 
    buf b_do_out17 (DO[17], do17_out);
210 
    buf b_do_out18 (DO[18], do18_out);
211 
    buf b_do_out19 (DO[19], do19_out);
212 
    buf b_do_out20 (DO[20], do20_out);
213 
    buf b_do_out21 (DO[21], do21_out);
214 
    buf b_do_out22 (DO[22], do22_out);
215 
    buf b_do_out23 (DO[23], do23_out);
216 
    buf b_do_out24 (DO[24], do24_out);
217 
    buf b_do_out25 (DO[25], do25_out);
218 
    buf b_do_out26 (DO[26], do26_out);
219 
    buf b_do_out27 (DO[27], do27_out);
220 
    buf b_do_out28 (DO[28], do28_out);
221 
    buf b_do_out29 (DO[29], do29_out);
222 
    buf b_do_out30 (DO[30], do30_out);
223 
    buf b_do_out31 (DO[31], do31_out);
224 
    buf b_dop_out0 (DOP[0], dop0_out);
225 
    buf b_dop_out1 (DOP[1], dop1_out);
226 
    buf b_dop_out2 (DOP[2], dop2_out);
227 
    buf b_dop_out3 (DOP[3], dop3_out);
228 
    buf b_addr_0 (addr_int[0], ADDR[0]);
229 
    buf b_addr_1 (addr_int[1], ADDR[1]);
230 
    buf b_addr_2 (addr_int[2], ADDR[2]);
231 
    buf b_addr_3 (addr_int[3], ADDR[3]);
232 
    buf b_addr_4 (addr_int[4], ADDR[4]);
233 
    buf b_addr_5 (addr_int[5], ADDR[5]);
234 
    buf b_addr_6 (addr_int[6], ADDR[6]);
235 
    buf b_addr_7 (addr_int[7], ADDR[7]);
236 
    buf b_addr_8 (addr_int[8], ADDR[8]);
237 
    buf b_di_0 (di_int[0], DI[0]);
238 
    buf b_di_1 (di_int[1], DI[1]);
239 
    buf b_di_2 (di_int[2], DI[2]);
240 
    buf b_di_3 (di_int[3], DI[3]);
241 
    buf b_di_4 (di_int[4], DI[4]);
242 
    buf b_di_5 (di_int[5], DI[5]);
243 
    buf b_di_6 (di_int[6], DI[6]);
244 
    buf b_di_7 (di_int[7], DI[7]);
245 
    buf b_di_8 (di_int[8], DI[8]);
246 
    buf b_di_9 (di_int[9], DI[9]);
247 
    buf b_di_10 (di_int[10], DI[10]);
248 
    buf b_di_11 (di_int[11], DI[11]);
249 
    buf b_di_12 (di_int[12], DI[12]);
250 
    buf b_di_13 (di_int[13], DI[13]);
251 
    buf b_di_14 (di_int[14], DI[14]);
252 
    buf b_di_15 (di_int[15], DI[15]);
253 
    buf b_di_16 (di_int[16], DI[16]);
254 
    buf b_di_17 (di_int[17], DI[17]);
255 
    buf b_di_18 (di_int[18], DI[18]);
256 
    buf b_di_19 (di_int[19], DI[19]);
257 
    buf b_di_20 (di_int[20], DI[20]);
258 
    buf b_di_21 (di_int[21], DI[21]);
259 
    buf b_di_22 (di_int[22], DI[22]);
260 
    buf b_di_23 (di_int[23], DI[23]);
261 
    buf b_di_24 (di_int[24], DI[24]);
262 
    buf b_di_25 (di_int[25], DI[25]);
263 
    buf b_di_26 (di_int[26], DI[26]);
264 
    buf b_di_27 (di_int[27], DI[27]);
265 
    buf b_di_28 (di_int[28], DI[28]);
266 
    buf b_di_29 (di_int[29], DI[29]);
267 
    buf b_di_30 (di_int[30], DI[30]);
268 
    buf b_di_31 (di_int[31], DI[31]);
269 
    buf b_dip_0 (dip_int[0], DIP[0]);
270 
    buf b_dip_1 (dip_int[1], DIP[1]);
271 
    buf b_dip_2 (dip_int[2], DIP[2]);
272 
    buf b_dip_3 (dip_int[3], DIP[3]);
273 
    buf b_en (en_int, EN);
274 
    buf b_clk (clk_int, CLK);
275 
    buf b_we (we_int, WE);
276 
    buf b_ssr (ssr_int, SSR);
277 
 
278 
    initial begin
279 
        for (count = 0; count < 256; count = count + 1) begin
280 
            mem[count]            <= INIT_00[count];
281 
            mem[256 * 1 + count]  <= INIT_01[count];
282 
            mem[256 * 2 + count]  <= INIT_02[count];
283 
            mem[256 * 3 + count]  <= INIT_03[count];
284 
            mem[256 * 4 + count]  <= INIT_04[count];
285 
            mem[256 * 5 + count]  <= INIT_05[count];
286 
            mem[256 * 6 + count]  <= INIT_06[count];
287 
            mem[256 * 7 + count]  <= INIT_07[count];
288 
            mem[256 * 8 + count]  <= INIT_08[count];
289 
            mem[256 * 9 + count]  <= INIT_09[count];
290 
            mem[256 * 10 + count] <= INIT_0A[count];
291 
            mem[256 * 11 + count] <= INIT_0B[count];
292 
            mem[256 * 12 + count] <= INIT_0C[count];
293 
            mem[256 * 13 + count] <= INIT_0D[count];
294 
            mem[256 * 14 + count] <= INIT_0E[count];
295 
            mem[256 * 15 + count] <= INIT_0F[count];
296 
            mem[256 * 16 + count] <= INIT_10[count];
297 
            mem[256 * 17 + count] <= INIT_11[count];
298 
            mem[256 * 18 + count] <= INIT_12[count];
299 
            mem[256 * 19 + count] <= INIT_13[count];
300 
            mem[256 * 20 + count] <= INIT_14[count];
301 
            mem[256 * 21 + count] <= INIT_15[count];
302 
            mem[256 * 22 + count] <= INIT_16[count];
303 
            mem[256 * 23 + count] <= INIT_17[count];
304 
            mem[256 * 24 + count] <= INIT_18[count];
305 
            mem[256 * 25 + count] <= INIT_19[count];
306 
            mem[256 * 26 + count] <= INIT_1A[count];
307 
            mem[256 * 27 + count] <= INIT_1B[count];
308 
            mem[256 * 28 + count] <= INIT_1C[count];
309 
            mem[256 * 29 + count] <= INIT_1D[count];
310 
            mem[256 * 30 + count] <= INIT_1E[count];
311 
            mem[256 * 31 + count] <= INIT_1F[count];
312 
            mem[256 * 32 + count] <= INIT_20[count];
313 
            mem[256 * 33 + count] <= INIT_21[count];
314 
            mem[256 * 34 + count] <= INIT_22[count];
315 
            mem[256 * 35 + count] <= INIT_23[count];
316 
            mem[256 * 36 + count] <= INIT_24[count];
317 
            mem[256 * 37 + count] <= INIT_25[count];
318 
            mem[256 * 38 + count] <= INIT_26[count];
319 
            mem[256 * 39 + count] <= INIT_27[count];
320 
            mem[256 * 40 + count] <= INIT_28[count];
321 
            mem[256 * 41 + count] <= INIT_29[count];
322 
            mem[256 * 42 + count] <= INIT_2A[count];
323 
            mem[256 * 43 + count] <= INIT_2B[count];
324 
            mem[256 * 44 + count] <= INIT_2C[count];
325 
            mem[256 * 45 + count] <= INIT_2D[count];
326 
            mem[256 * 46 + count] <= INIT_2E[count];
327 
            mem[256 * 47 + count] <= INIT_2F[count];
328 
            mem[256 * 48 + count] <= INIT_30[count];
329 
            mem[256 * 49 + count] <= INIT_31[count];
330 
            mem[256 * 50 + count] <= INIT_32[count];
331 
            mem[256 * 51 + count] <= INIT_33[count];
332 
            mem[256 * 52 + count] <= INIT_34[count];
333 
            mem[256 * 53 + count] <= INIT_35[count];
334 
            mem[256 * 54 + count] <= INIT_36[count];
335 
            mem[256 * 55 + count] <= INIT_37[count];
336 
            mem[256 * 56 + count] <= INIT_38[count];
337 
            mem[256 * 57 + count] <= INIT_39[count];
338 
            mem[256 * 58 + count] <= INIT_3A[count];
339 
            mem[256 * 59 + count] <= INIT_3B[count];
340 
            mem[256 * 60 + count] <= INIT_3C[count];
341 
            mem[256 * 61 + count] <= INIT_3D[count];
342 
            mem[256 * 62 + count] <= INIT_3E[count];
343 
            mem[256 * 63 + count] <= INIT_3F[count];
344 
            mem[256 * 64 + count] <= INITP_00[count];
345 
            mem[256 * 65 + count] <= INITP_01[count];
346 
            mem[256 * 66 + count] <= INITP_02[count];
347 
            mem[256 * 67 + count] <= INITP_03[count];
348 
            mem[256 * 68 + count] <= INITP_04[count];
349 
            mem[256 * 69 + count] <= INITP_05[count];
350 
            mem[256 * 70 + count] <= INITP_06[count];
351 
            mem[256 * 71 + count] <= INITP_07[count];
352 
        end
353 
    end
354 
 
355 
    initial begin
356 
        case (WRITE_MODE)
357 
            "WRITE_FIRST" : wr_mode <= 2'b00;
358 
            "READ_FIRST"  : wr_mode <= 2'b01;
359 
            "NO_CHANGE"   : wr_mode <= 2'b10;
360 
            default       : begin
361 
                                $display("Error : WRITE_MODE = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE);
362 
                                $finish;
363 
                            end
364 
        endcase
365 
    end
366 
 
367 
    always @(posedge clk_int) begin
368 
        if (en_int == 1'b1) begin
369 
            if (ssr_int == 1'b1) begin
370 
                do0_out <= SRVAL[0];
371 
                do1_out <= SRVAL[1];
372 
                do2_out <= SRVAL[2];
373 
                do3_out <= SRVAL[3];
374 
                do4_out <= SRVAL[4];
375 
                do5_out <= SRVAL[5];
376 
                do6_out <= SRVAL[6];
377 
                do7_out <= SRVAL[7];
378 
                do8_out <= SRVAL[8];
379 
                do9_out <= SRVAL[9];
380 
                do10_out <= SRVAL[10];
381 
                do11_out <= SRVAL[11];
382 
                do12_out <= SRVAL[12];
383 
                do13_out <= SRVAL[13];
384 
                do14_out <= SRVAL[14];
385 
                do15_out <= SRVAL[15];
386 
                do16_out <= SRVAL[16];
387 
                do17_out <= SRVAL[17];
388 
                do18_out <= SRVAL[18];
389 
                do19_out <= SRVAL[19];
390 
                do20_out <= SRVAL[20];
391 
                do21_out <= SRVAL[21];
392 
                do22_out <= SRVAL[22];
393 
                do23_out <= SRVAL[23];
394 
                do24_out <= SRVAL[24];
395 
                do25_out <= SRVAL[25];
396 
                do26_out <= SRVAL[26];
397 
                do27_out <= SRVAL[27];
398 
                do28_out <= SRVAL[28];
399 
                do29_out <= SRVAL[29];
400 
                do30_out <= SRVAL[30];
401 
                do31_out <= SRVAL[31];
402 
                dop0_out <= SRVAL[32];
403 
                dop1_out <= SRVAL[33];
404 
                dop2_out <= SRVAL[34];
405 
                dop3_out <= SRVAL[35];
406 
            end
407 
            else begin
408 
                if (we_int == 1'b1) begin
409 
                    if (wr_mode == 2'b00) begin
410 
                        do0_out <= di_int[0];
411 
                        do1_out <= di_int[1];
412 
                        do2_out <= di_int[2];
413 
                        do3_out <= di_int[3];
414 
                        do4_out <= di_int[4];
415 
                        do5_out <= di_int[5];
416 
                        do6_out <= di_int[6];
417 
                        do7_out <= di_int[7];
418 
                        do8_out <= di_int[8];
419 
                        do9_out <= di_int[9];
420 
                        do10_out <= di_int[10];
421 
                        do11_out <= di_int[11];
422 
                        do12_out <= di_int[12];
423 
                        do13_out <= di_int[13];
424 
                        do14_out <= di_int[14];
425 
                        do15_out <= di_int[15];
426 
                        do16_out <= di_int[16];
427 
                        do17_out <= di_int[17];
428 
                        do18_out <= di_int[18];
429 
                        do19_out <= di_int[19];
430 
                        do20_out <= di_int[20];
431 
                        do21_out <= di_int[21];
432 
                        do22_out <= di_int[22];
433 
                        do23_out <= di_int[23];
434 
                        do24_out <= di_int[24];
435 
                        do25_out <= di_int[25];
436 
                        do26_out <= di_int[26];
437 
                        do27_out <= di_int[27];
438 
                        do28_out <= di_int[28];
439 
                        do29_out <= di_int[29];
440 
                        do30_out <= di_int[30];
441 
                        do31_out <= di_int[31];
442 
                        dop0_out <= dip_int[0];
443 
                        dop1_out <= dip_int[1];
444 
                        dop2_out <= dip_int[2];
445 
                        dop3_out <= dip_int[3];
446 
                    end
447 
                    else if (wr_mode == 2'b01) begin
448 
                        do0_out <= mem[addr_int * 32 + 0];
449 
                        do1_out <= mem[addr_int * 32 + 1];
450 
                        do2_out <= mem[addr_int * 32 + 2];
451 
                        do3_out <= mem[addr_int * 32 + 3];
452 
                        do4_out <= mem[addr_int * 32 + 4];
453 
                        do5_out <= mem[addr_int * 32 + 5];
454 
                        do6_out <= mem[addr_int * 32 + 6];
455 
                        do7_out <= mem[addr_int * 32 + 7];
456 
                        do8_out <= mem[addr_int * 32 + 8];
457 
                        do9_out <= mem[addr_int * 32 + 9];
458 
                        do10_out <= mem[addr_int * 32 + 10];
459 
                        do11_out <= mem[addr_int * 32 + 11];
460 
                        do12_out <= mem[addr_int * 32 + 12];
461 
                        do13_out <= mem[addr_int * 32 + 13];
462 
                        do14_out <= mem[addr_int * 32 + 14];
463 
                        do15_out <= mem[addr_int * 32 + 15];
464 
                        do16_out <= mem[addr_int * 32 + 16];
465 
                        do17_out <= mem[addr_int * 32 + 17];
466 
                        do18_out <= mem[addr_int * 32 + 18];
467 
                        do19_out <= mem[addr_int * 32 + 19];
468 
                        do20_out <= mem[addr_int * 32 + 20];
469 
                        do21_out <= mem[addr_int * 32 + 21];
470 
                        do22_out <= mem[addr_int * 32 + 22];
471 
                        do23_out <= mem[addr_int * 32 + 23];
472 
                        do24_out <= mem[addr_int * 32 + 24];
473 
                        do25_out <= mem[addr_int * 32 + 25];
474 
                        do26_out <= mem[addr_int * 32 + 26];
475 
                        do27_out <= mem[addr_int * 32 + 27];
476 
                        do28_out <= mem[addr_int * 32 + 28];
477 
                        do29_out <= mem[addr_int * 32 + 29];
478 
                        do30_out <= mem[addr_int * 32 + 30];
479 
                        do31_out <= mem[addr_int * 32 + 31];
480 
                        dop0_out <= mem[16384 + addr_int * 4 + 0];
481 
                        dop1_out <= mem[16384 + addr_int * 4 + 1];
482 
                        dop2_out <= mem[16384 + addr_int * 4 + 2];
483 
                        dop3_out <= mem[16384 + addr_int * 4 + 3];
484 
                    end
485 
                    else begin
486 
                        do0_out <= do0_out;
487 
                        do1_out <= do1_out;
488 
                        do2_out <= do2_out;
489 
                        do3_out <= do3_out;
490 
                        do4_out <= do4_out;
491 
                        do5_out <= do5_out;
492 
                        do6_out <= do6_out;
493 
                        do7_out <= do7_out;
494 
                        do8_out <= do8_out;
495 
                        do9_out <= do9_out;
496 
                        do10_out <= do10_out;
497 
                        do11_out <= do11_out;
498 
                        do12_out <= do12_out;
499 
                        do13_out <= do13_out;
500 
                        do14_out <= do14_out;
501 
                        do15_out <= do15_out;
502 
                        do16_out <= do16_out;
503 
                        do17_out <= do17_out;
504 
                        do18_out <= do18_out;
505 
                        do19_out <= do19_out;
506 
                        do20_out <= do20_out;
507 
                        do21_out <= do21_out;
508 
                        do22_out <= do22_out;
509 
                        do23_out <= do23_out;
510 
                        do24_out <= do24_out;
511 
                        do25_out <= do25_out;
512 
                        do26_out <= do26_out;
513 
                        do27_out <= do27_out;
514 
                        do28_out <= do28_out;
515 
                        do29_out <= do29_out;
516 
                        do30_out <= do30_out;
517 
                        do31_out <= do31_out;
518 
                        dop0_out <= dop0_out;
519 
                        dop1_out <= dop1_out;
520 
                        dop2_out <= dop2_out;
521 
                        dop3_out <= dop3_out;
522 
                    end
523 
                end
524 
                else begin
525 
                    do0_out <= mem[addr_int * 32 + 0];
526 
                    do1_out <= mem[addr_int * 32 + 1];
527 
                    do2_out <= mem[addr_int * 32 + 2];
528 
                    do3_out <= mem[addr_int * 32 + 3];
529 
                    do4_out <= mem[addr_int * 32 + 4];
530 
                    do5_out <= mem[addr_int * 32 + 5];
531 
                    do6_out <= mem[addr_int * 32 + 6];
532 
                    do7_out <= mem[addr_int * 32 + 7];
533 
                    do8_out <= mem[addr_int * 32 + 8];
534 
                    do9_out <= mem[addr_int * 32 + 9];
535 
                    do10_out <= mem[addr_int * 32 + 10];
536 
                    do11_out <= mem[addr_int * 32 + 11];
537 
                    do12_out <= mem[addr_int * 32 + 12];
538 
                    do13_out <= mem[addr_int * 32 + 13];
539 
                    do14_out <= mem[addr_int * 32 + 14];
540 
                    do15_out <= mem[addr_int * 32 + 15];
541 
                    do16_out <= mem[addr_int * 32 + 16];
542 
                    do17_out <= mem[addr_int * 32 + 17];
543 
                    do18_out <= mem[addr_int * 32 + 18];
544 
                    do19_out <= mem[addr_int * 32 + 19];
545 
                    do20_out <= mem[addr_int * 32 + 20];
546 
                    do21_out <= mem[addr_int * 32 + 21];
547 
                    do22_out <= mem[addr_int * 32 + 22];
548 
                    do23_out <= mem[addr_int * 32 + 23];
549 
                    do24_out <= mem[addr_int * 32 + 24];
550 
                    do25_out <= mem[addr_int * 32 + 25];
551 
                    do26_out <= mem[addr_int * 32 + 26];
552 
                    do27_out <= mem[addr_int * 32 + 27];
553 
                    do28_out <= mem[addr_int * 32 + 28];
554 
                    do29_out <= mem[addr_int * 32 + 29];
555 
                    do30_out <= mem[addr_int * 32 + 30];
556 
                    do31_out <= mem[addr_int * 32 + 31];
557 
                    dop0_out <= mem[16384 + addr_int * 4 + 0];
558 
                    dop1_out <= mem[16384 + addr_int * 4 + 1];
559 
                    dop2_out <= mem[16384 + addr_int * 4 + 2];
560 
                    dop3_out <= mem[16384 + addr_int * 4 + 3];
561 
                end
562 
            end
563 
        end
564 
    end
565 
 
566 
    always @(posedge clk_int) begin
567 
        if (en_int == 1'b1 && we_int == 1'b1) begin
568 
            mem[addr_int * 32 + 0] <= di_int[0];
569 
            mem[addr_int * 32 + 1] <= di_int[1];
570 
            mem[addr_int * 32 + 2] <= di_int[2];
571 
            mem[addr_int * 32 + 3] <= di_int[3];
572 
            mem[addr_int * 32 + 4] <= di_int[4];
573 
            mem[addr_int * 32 + 5] <= di_int[5];
574 
            mem[addr_int * 32 + 6] <= di_int[6];
575 
            mem[addr_int * 32 + 7] <= di_int[7];
576 
            mem[addr_int * 32 + 8] <= di_int[8];
577 
            mem[addr_int * 32 + 9] <= di_int[9];
578 
            mem[addr_int * 32 + 10] <= di_int[10];
579 
            mem[addr_int * 32 + 11] <= di_int[11];
580 
            mem[addr_int * 32 + 12] <= di_int[12];
581 
            mem[addr_int * 32 + 13] <= di_int[13];
582 
            mem[addr_int * 32 + 14] <= di_int[14];
583 
            mem[addr_int * 32 + 15] <= di_int[15];
584 
            mem[addr_int * 32 + 16] <= di_int[16];
585 
            mem[addr_int * 32 + 17] <= di_int[17];
586 
            mem[addr_int * 32 + 18] <= di_int[18];
587 
            mem[addr_int * 32 + 19] <= di_int[19];
588 
            mem[addr_int * 32 + 20] <= di_int[20];
589 
            mem[addr_int * 32 + 21] <= di_int[21];
590 
            mem[addr_int * 32 + 22] <= di_int[22];
591 
            mem[addr_int * 32 + 23] <= di_int[23];
592 
            mem[addr_int * 32 + 24] <= di_int[24];
593 
            mem[addr_int * 32 + 25] <= di_int[25];
594 
            mem[addr_int * 32 + 26] <= di_int[26];
595 
            mem[addr_int * 32 + 27] <= di_int[27];
596 
            mem[addr_int * 32 + 28] <= di_int[28];
597 
            mem[addr_int * 32 + 29] <= di_int[29];
598 
            mem[addr_int * 32 + 30] <= di_int[30];
599 
            mem[addr_int * 32 + 31] <= di_int[31];
600 
            mem[16384 + addr_int * 4 + 0] <= dip_int[0];
601 
            mem[16384 + addr_int * 4 + 1] <= dip_int[1];
602 
            mem[16384 + addr_int * 4 + 2] <= dip_int[2];
603 
            mem[16384 + addr_int * 4 + 3] <= dip_int[3];
604 
        end
605 
    end
606 
 
607 
    specify
608 
        (CLK *> DO) = (1, 1);
609 
        (CLK *> DOP) = (1, 1);
610 
    endspecify
611 
 
612 
endmodule
613 
 
614 
`endcelldefine

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