URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [mp3_stable/] [mp3/] [lib/] [xilinx/] [unisims/] [RAMB16_S4.v] - Blame information for rev 1765

Details | Compare with Previous | View Log


// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/RAMB16_S4.v,v 1.1.1.1 2001-11-04 18:59:56 lampret Exp $
 
/*
 
FUNCTION        : 16x4 Block RAM with synchronous write capability
 
*/
 
`timescale  100 ps / 10 ps
 
`celldefine
 
module RAMB16_S4 (DO, ADDR, DI, EN, CLK, WE, SSR);
 
    parameter cds_action = "ignore";
    parameter INIT = 4'h0;
    parameter SRVAL = 4'h0;
    parameter WRITE_MODE = "WRITE_FIRST";
 
    parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 
    output [3:0] DO;
    reg do0_out, do1_out, do2_out, do3_out;
 
    input [11:0] ADDR;
    input [3:0] DI;
    input EN, CLK, WE, SSR;
 
    reg [18431:0] mem;
    reg [8:0] count;
    reg [1:0] wr_mode;
 
    wire [11:0] addr_int;
    wire [3:0] di_int;
    wire en_int, clk_int, we_int, ssr_int;
 
    tri0 GSR = glbl.GSR;
 
    always @(GSR)
        if (GSR) begin
            assign do0_out = INIT[0];
            assign do1_out = INIT[1];
            assign do2_out = INIT[2];
            assign do3_out = INIT[3];
        end
        else begin
            deassign do0_out;
            deassign do1_out;
            deassign do2_out;
            deassign do3_out;
        end
 
    buf b_do_out0 (DO[0], do0_out);
    buf b_do_out1 (DO[1], do1_out);
    buf b_do_out2 (DO[2], do2_out);
    buf b_do_out3 (DO[3], do3_out);
    buf b_addr_0 (addr_int[0], ADDR[0]);
    buf b_addr_1 (addr_int[1], ADDR[1]);
    buf b_addr_2 (addr_int[2], ADDR[2]);
    buf b_addr_3 (addr_int[3], ADDR[3]);
    buf b_addr_4 (addr_int[4], ADDR[4]);
    buf b_addr_5 (addr_int[5], ADDR[5]);
    buf b_addr_6 (addr_int[6], ADDR[6]);
    buf b_addr_7 (addr_int[7], ADDR[7]);
    buf b_addr_8 (addr_int[8], ADDR[8]);
    buf b_addr_9 (addr_int[9], ADDR[9]);
    buf b_addr_10 (addr_int[10], ADDR[10]);
    buf b_addr_11 (addr_int[11], ADDR[11]);
    buf b_di_0 (di_int[0], DI[0]);
    buf b_di_1 (di_int[1], DI[1]);
    buf b_di_2 (di_int[2], DI[2]);
    buf b_di_3 (di_int[3], DI[3]);
    buf b_en (en_int, EN);
    buf b_clk (clk_int, CLK);
    buf b_we (we_int, WE);
    buf b_ssr (ssr_int, SSR);
 
    initial begin
        for (count = 0; count < 256; count = count + 1) begin
            mem[count]            <= INIT_00[count];
            mem[256 * 1 + count]  <= INIT_01[count];
            mem[256 * 2 + count]  <= INIT_02[count];
            mem[256 * 3 + count]  <= INIT_03[count];
            mem[256 * 4 + count]  <= INIT_04[count];
            mem[256 * 5 + count]  <= INIT_05[count];
            mem[256 * 6 + count]  <= INIT_06[count];
            mem[256 * 7 + count]  <= INIT_07[count];
            mem[256 * 8 + count]  <= INIT_08[count];
            mem[256 * 9 + count]  <= INIT_09[count];
            mem[256 * 10 + count] <= INIT_0A[count];
            mem[256 * 11 + count] <= INIT_0B[count];
            mem[256 * 12 + count] <= INIT_0C[count];
            mem[256 * 13 + count] <= INIT_0D[count];
            mem[256 * 14 + count] <= INIT_0E[count];
            mem[256 * 15 + count] <= INIT_0F[count];
            mem[256 * 16 + count] <= INIT_10[count];
            mem[256 * 17 + count] <= INIT_11[count];
            mem[256 * 18 + count] <= INIT_12[count];
            mem[256 * 19 + count] <= INIT_13[count];
            mem[256 * 20 + count] <= INIT_14[count];
            mem[256 * 21 + count] <= INIT_15[count];
            mem[256 * 22 + count] <= INIT_16[count];
            mem[256 * 23 + count] <= INIT_17[count];
            mem[256 * 24 + count] <= INIT_18[count];
            mem[256 * 25 + count] <= INIT_19[count];
            mem[256 * 26 + count] <= INIT_1A[count];
            mem[256 * 27 + count] <= INIT_1B[count];
            mem[256 * 28 + count] <= INIT_1C[count];
            mem[256 * 29 + count] <= INIT_1D[count];
            mem[256 * 30 + count] <= INIT_1E[count];
            mem[256 * 31 + count] <= INIT_1F[count];
            mem[256 * 32 + count] <= INIT_20[count];
            mem[256 * 33 + count] <= INIT_21[count];
            mem[256 * 34 + count] <= INIT_22[count];
            mem[256 * 35 + count] <= INIT_23[count];
            mem[256 * 36 + count] <= INIT_24[count];
            mem[256 * 37 + count] <= INIT_25[count];
            mem[256 * 38 + count] <= INIT_26[count];
            mem[256 * 39 + count] <= INIT_27[count];
            mem[256 * 40 + count] <= INIT_28[count];
            mem[256 * 41 + count] <= INIT_29[count];
            mem[256 * 42 + count] <= INIT_2A[count];
            mem[256 * 43 + count] <= INIT_2B[count];
            mem[256 * 44 + count] <= INIT_2C[count];
            mem[256 * 45 + count] <= INIT_2D[count];
            mem[256 * 46 + count] <= INIT_2E[count];
            mem[256 * 47 + count] <= INIT_2F[count];
            mem[256 * 48 + count] <= INIT_30[count];
            mem[256 * 49 + count] <= INIT_31[count];
            mem[256 * 50 + count] <= INIT_32[count];
            mem[256 * 51 + count] <= INIT_33[count];
            mem[256 * 52 + count] <= INIT_34[count];
            mem[256 * 53 + count] <= INIT_35[count];
            mem[256 * 54 + count] <= INIT_36[count];
            mem[256 * 55 + count] <= INIT_37[count];
            mem[256 * 56 + count] <= INIT_38[count];
            mem[256 * 57 + count] <= INIT_39[count];
            mem[256 * 58 + count] <= INIT_3A[count];
            mem[256 * 59 + count] <= INIT_3B[count];
            mem[256 * 60 + count] <= INIT_3C[count];
            mem[256 * 61 + count] <= INIT_3D[count];
            mem[256 * 62 + count] <= INIT_3E[count];
            mem[256 * 63 + count] <= INIT_3F[count];
        end
    end
 
    initial begin
        case (WRITE_MODE)
            "WRITE_FIRST" : wr_mode <= 2'b00;
            "READ_FIRST"  : wr_mode <= 2'b01;
            "NO_CHANGE"   : wr_mode <= 2'b10;
            default       : begin
                                $display("Error : WRITE_MODE = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE);
                                $finish;
                            end
        endcase
    end
 
    always @(posedge clk_int) begin
        if (en_int == 1'b1) begin
            if (ssr_int == 1'b1) begin
                do0_out <= SRVAL[0];
                do1_out <= SRVAL[1];
                do2_out <= SRVAL[2];
                do3_out <= SRVAL[3];
            end
            else begin
                if (we_int == 1'b1) begin
                    if (wr_mode == 2'b00) begin
                        do0_out <= di_int[0];
                        do1_out <= di_int[1];
                        do2_out <= di_int[2];
                        do3_out <= di_int[3];
                    end
                    else if (wr_mode == 2'b01) begin
                        do0_out <= mem[addr_int * 4 + 0];
                        do1_out <= mem[addr_int * 4 + 1];
                        do2_out <= mem[addr_int * 4 + 2];
                        do3_out <= mem[addr_int * 4 + 3];
                    end
                    else begin
                        do0_out <= do0_out;
                        do1_out <= do1_out;
                        do2_out <= do2_out;
                        do3_out <= do3_out;
                    end
                end
                else begin
                    do0_out <= mem[addr_int * 4 + 0];
                    do1_out <= mem[addr_int * 4 + 1];
                    do2_out <= mem[addr_int * 4 + 2];
                    do3_out <= mem[addr_int * 4 + 3];
                end
            end
        end
    end
 
    always @(posedge clk_int) begin
        if (en_int == 1'b1 && we_int == 1'b1) begin
            mem[addr_int * 4 + 0] <= di_int[0];
            mem[addr_int * 4 + 1] <= di_int[1];
            mem[addr_int * 4 + 2] <= di_int[2];
            mem[addr_int * 4 + 3] <= di_int[3];
        end
    end
 
    specify
        (CLK *> DO) = (1, 1);
    endspecify
 
endmodule
 
`endcelldefine

Browse

Tools

Subversion Repositories or1k

[/] [or1k/] [branches/] [mp3_stable/] [mp3/] [lib/] [xilinx/] [unisims/] [RAMB16_S4.v] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	266	lampret	`// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/RAMB16_S4.v,v 1.1.1.1 2001-11-04 18:59:56 lampret Exp $`
2
3			`/*`
4
5			`FUNCTION : 16x4 Block RAM with synchronous write capability`
6
7			`*/`
8
9			`timescale 100 ps / 10 ps
10
11			`celldefine
12
13			`module RAMB16_S4 (DO, ADDR, DI, EN, CLK, WE, SSR);`
14
15			`parameter cds_action = "ignore";`
16			`parameter INIT = 4'h0;`
17			`parameter SRVAL = 4'h0;`
18			`parameter WRITE_MODE = "WRITE_FIRST";`
19
20			`parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
21			`parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
22			`parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
23			`parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
24			`parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
25			`parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
26			`parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
27			`parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
28			`parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
29			`parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
30			`parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
31			`parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
32			`parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
33			`parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
34			`parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
35			`parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
36			`parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
37			`parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
38			`parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
39			`parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
40			`parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
41			`parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
42			`parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
43			`parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
44			`parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
45			`parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
46			`parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
47			`parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
48			`parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
49			`parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
50			`parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
51			`parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
52			`parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
53			`parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
54			`parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
55			`parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
56			`parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
57			`parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
58			`parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
59			`parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
60			`parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
61			`parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
62			`parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
63			`parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
64			`parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
65			`parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
66			`parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
67			`parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
68			`parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
69			`parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
70			`parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
71			`parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
72			`parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
73			`parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
74			`parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
75			`parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
76			`parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
77			`parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
78			`parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
79			`parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
80			`parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
81			`parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
82			`parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
83			`parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;`
84
85			`output [3:0] DO;`
86			`reg do0_out, do1_out, do2_out, do3_out;`
87
88			`input [11:0] ADDR;`
89			`input [3:0] DI;`
90			`input EN, CLK, WE, SSR;`
91
92			`reg [18431:0] mem;`
93			`reg [8:0] count;`
94			`reg [1:0] wr_mode;`
95
96			`wire [11:0] addr_int;`
97			`wire [3:0] di_int;`
98			`wire en_int, clk_int, we_int, ssr_int;`
99
100			`tri0 GSR = glbl.GSR;`
101
102			`always @(GSR)`
103			`if (GSR) begin`
104			`assign do0_out = INIT[0];`
105			`assign do1_out = INIT[1];`
106			`assign do2_out = INIT[2];`
107			`assign do3_out = INIT[3];`
108			`end`
109			`else begin`
110			`deassign do0_out;`
111			`deassign do1_out;`
112			`deassign do2_out;`
113			`deassign do3_out;`
114			`end`
115
116			`buf b_do_out0 (DO[0], do0_out);`
117			`buf b_do_out1 (DO[1], do1_out);`
118			`buf b_do_out2 (DO[2], do2_out);`
119			`buf b_do_out3 (DO[3], do3_out);`
120			`buf b_addr_0 (addr_int[0], ADDR[0]);`
121			`buf b_addr_1 (addr_int[1], ADDR[1]);`
122			`buf b_addr_2 (addr_int[2], ADDR[2]);`
123			`buf b_addr_3 (addr_int[3], ADDR[3]);`
124			`buf b_addr_4 (addr_int[4], ADDR[4]);`
125			`buf b_addr_5 (addr_int[5], ADDR[5]);`
126			`buf b_addr_6 (addr_int[6], ADDR[6]);`
127			`buf b_addr_7 (addr_int[7], ADDR[7]);`
128			`buf b_addr_8 (addr_int[8], ADDR[8]);`
129			`buf b_addr_9 (addr_int[9], ADDR[9]);`
130			`buf b_addr_10 (addr_int[10], ADDR[10]);`
131			`buf b_addr_11 (addr_int[11], ADDR[11]);`
132			`buf b_di_0 (di_int[0], DI[0]);`
133			`buf b_di_1 (di_int[1], DI[1]);`
134			`buf b_di_2 (di_int[2], DI[2]);`
135			`buf b_di_3 (di_int[3], DI[3]);`
136			`buf b_en (en_int, EN);`
137			`buf b_clk (clk_int, CLK);`
138			`buf b_we (we_int, WE);`
139			`buf b_ssr (ssr_int, SSR);`
140
141			`initial begin`
142			`for (count = 0; count < 256; count = count + 1) begin`
143			`mem[count] <= INIT_00[count];`
144			`mem[256 * 1 + count] <= INIT_01[count];`
145			`mem[256 * 2 + count] <= INIT_02[count];`
146			`mem[256 * 3 + count] <= INIT_03[count];`
147			`mem[256 * 4 + count] <= INIT_04[count];`
148			`mem[256 * 5 + count] <= INIT_05[count];`
149			`mem[256 * 6 + count] <= INIT_06[count];`
150			`mem[256 * 7 + count] <= INIT_07[count];`
151			`mem[256 * 8 + count] <= INIT_08[count];`
152			`mem[256 * 9 + count] <= INIT_09[count];`
153			`mem[256 * 10 + count] <= INIT_0A[count];`
154			`mem[256 * 11 + count] <= INIT_0B[count];`
155			`mem[256 * 12 + count] <= INIT_0C[count];`
156			`mem[256 * 13 + count] <= INIT_0D[count];`
157			`mem[256 * 14 + count] <= INIT_0E[count];`
158			`mem[256 * 15 + count] <= INIT_0F[count];`
159			`mem[256 * 16 + count] <= INIT_10[count];`
160			`mem[256 * 17 + count] <= INIT_11[count];`
161			`mem[256 * 18 + count] <= INIT_12[count];`
162			`mem[256 * 19 + count] <= INIT_13[count];`
163			`mem[256 * 20 + count] <= INIT_14[count];`
164			`mem[256 * 21 + count] <= INIT_15[count];`
165			`mem[256 * 22 + count] <= INIT_16[count];`
166			`mem[256 * 23 + count] <= INIT_17[count];`
167			`mem[256 * 24 + count] <= INIT_18[count];`
168			`mem[256 * 25 + count] <= INIT_19[count];`
169			`mem[256 * 26 + count] <= INIT_1A[count];`
170			`mem[256 * 27 + count] <= INIT_1B[count];`
171			`mem[256 * 28 + count] <= INIT_1C[count];`
172			`mem[256 * 29 + count] <= INIT_1D[count];`
173			`mem[256 * 30 + count] <= INIT_1E[count];`
174			`mem[256 * 31 + count] <= INIT_1F[count];`
175			`mem[256 * 32 + count] <= INIT_20[count];`
176			`mem[256 * 33 + count] <= INIT_21[count];`
177			`mem[256 * 34 + count] <= INIT_22[count];`
178			`mem[256 * 35 + count] <= INIT_23[count];`
179			`mem[256 * 36 + count] <= INIT_24[count];`
180			`mem[256 * 37 + count] <= INIT_25[count];`
181			`mem[256 * 38 + count] <= INIT_26[count];`
182			`mem[256 * 39 + count] <= INIT_27[count];`
183			`mem[256 * 40 + count] <= INIT_28[count];`
184			`mem[256 * 41 + count] <= INIT_29[count];`
185			`mem[256 * 42 + count] <= INIT_2A[count];`
186			`mem[256 * 43 + count] <= INIT_2B[count];`
187			`mem[256 * 44 + count] <= INIT_2C[count];`
188			`mem[256 * 45 + count] <= INIT_2D[count];`
189			`mem[256 * 46 + count] <= INIT_2E[count];`
190			`mem[256 * 47 + count] <= INIT_2F[count];`
191			`mem[256 * 48 + count] <= INIT_30[count];`
192			`mem[256 * 49 + count] <= INIT_31[count];`
193			`mem[256 * 50 + count] <= INIT_32[count];`
194			`mem[256 * 51 + count] <= INIT_33[count];`
195			`mem[256 * 52 + count] <= INIT_34[count];`
196			`mem[256 * 53 + count] <= INIT_35[count];`
197			`mem[256 * 54 + count] <= INIT_36[count];`
198			`mem[256 * 55 + count] <= INIT_37[count];`
199			`mem[256 * 56 + count] <= INIT_38[count];`
200			`mem[256 * 57 + count] <= INIT_39[count];`
201			`mem[256 * 58 + count] <= INIT_3A[count];`
202			`mem[256 * 59 + count] <= INIT_3B[count];`
203			`mem[256 * 60 + count] <= INIT_3C[count];`
204			`mem[256 * 61 + count] <= INIT_3D[count];`
205			`mem[256 * 62 + count] <= INIT_3E[count];`
206			`mem[256 * 63 + count] <= INIT_3F[count];`
207			`end`
208			`end`
209
210			`initial begin`
211			`case (WRITE_MODE)`
212			`"WRITE_FIRST" : wr_mode <= 2'b00;`
213			`"READ_FIRST" : wr_mode <= 2'b01;`
214			`"NO_CHANGE" : wr_mode <= 2'b10;`
215			`default : begin`
216			`$display("Error : WRITE_MODE = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE);`
217			`$finish;`
218			`end`
219			`endcase`
220			`end`
221
222			`always @(posedge clk_int) begin`
223			`if (en_int == 1'b1) begin`
224			`if (ssr_int == 1'b1) begin`
225			`do0_out <= SRVAL[0];`
226			`do1_out <= SRVAL[1];`
227			`do2_out <= SRVAL[2];`
228			`do3_out <= SRVAL[3];`
229			`end`
230			`else begin`
231			`if (we_int == 1'b1) begin`
232			`if (wr_mode == 2'b00) begin`
233			`do0_out <= di_int[0];`
234			`do1_out <= di_int[1];`
235			`do2_out <= di_int[2];`
236			`do3_out <= di_int[3];`
237			`end`
238			`else if (wr_mode == 2'b01) begin`
239			`do0_out <= mem[addr_int * 4 + 0];`
240			`do1_out <= mem[addr_int * 4 + 1];`
241			`do2_out <= mem[addr_int * 4 + 2];`
242			`do3_out <= mem[addr_int * 4 + 3];`
243			`end`
244			`else begin`
245			`do0_out <= do0_out;`
246			`do1_out <= do1_out;`
247			`do2_out <= do2_out;`
248			`do3_out <= do3_out;`
249			`end`
250			`end`
251			`else begin`
252			`do0_out <= mem[addr_int * 4 + 0];`
253			`do1_out <= mem[addr_int * 4 + 1];`
254			`do2_out <= mem[addr_int * 4 + 2];`
255			`do3_out <= mem[addr_int * 4 + 3];`
256			`end`
257			`end`
258			`end`
259			`end`
260
261			`always @(posedge clk_int) begin`
262			`if (en_int == 1'b1 && we_int == 1'b1) begin`
263			`mem[addr_int * 4 + 0] <= di_int[0];`
264			`mem[addr_int * 4 + 1] <= di_int[1];`
265			`mem[addr_int * 4 + 2] <= di_int[2];`
266			`mem[addr_int * 4 + 3] <= di_int[3];`
267			`end`
268			`end`
269
270			`specify`
271			`(CLK *> DO) = (1, 1);`
272			`endspecify`
273
274			`endmodule`
275
276			`endcelldefine