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[/] [or1k/] [branches/] [mp3_stable/] [mp3/] [lib/] [xilinx/] [unisims/] [RAMB16_S4_S36.v] - Blame information for rev 1765

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1 266 lampret 
// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/RAMB16_S4_S36.v,v 1.1.1.1 2001-11-04 18:59:56 lampret Exp $
2 
 
3 
/*
4 
 
5 
FUNCTION        : 16x4x36 Block RAM with synchronous write capability
6 
 
7 
*/
8 
 
9 
`timescale  100 ps / 10 ps
10 
 
11 
`celldefine
12 
 
13 
module RAMB16_S4_S36 (DOA, DOB, DOPB, ADDRA, CLKA, DIA, ENA, SSRA, WEA, ADDRB, CLKB, DIB, DIPB, ENB, SSRB, WEB);
14 
    parameter cds_action = "ignore";
15 
    parameter INIT_A = 4'h0;
16 
    parameter INIT_B = 36'h0;
17 
    parameter SRVAL_A = 4'h0;
18 
    parameter SRVAL_B = 36'h0;
19 
    parameter WRITE_MODE_A = "WRITE_FIRST";
20 
    parameter WRITE_MODE_B = "WRITE_FIRST";
21 
 
22 
    parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
23 
    parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
24 
    parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
25 
    parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
26 
    parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
27 
    parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
28 
    parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
29 
    parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
30 
    parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
31 
    parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
32 
    parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
33 
    parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
34 
    parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
35 
    parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
36 
    parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
37 
    parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
38 
    parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
39 
    parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
40 
    parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
41 
    parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
42 
    parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
43 
    parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
44 
    parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
45 
    parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
46 
    parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
47 
    parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
48 
    parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
49 
    parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
50 
    parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
51 
    parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
52 
    parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
53 
    parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
54 
    parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
55 
    parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
56 
    parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
57 
    parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
58 
    parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
59 
    parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
60 
    parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
61 
    parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
62 
    parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
63 
    parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
64 
    parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
65 
    parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
66 
    parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
67 
    parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
68 
    parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
69 
    parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
70 
    parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
71 
    parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
72 
    parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
73 
    parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
74 
    parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
75 
    parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
76 
    parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
77 
    parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
78 
    parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
79 
    parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
80 
    parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
81 
    parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
82 
    parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
83 
    parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
84 
    parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
85 
    parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
86 
    parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
87 
    parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
88 
    parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
89 
    parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
90 
    parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
91 
    parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
92 
    parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
93 
    parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
94 
 
95 
    output [3:0] DOA;
96 
    reg [3:0] doa_out;
97 
    wire doa_out0, doa_out1, doa_out2, doa_out3;
98 
 
99 
    input [11:0] ADDRA;
100 
    input [3:0] DIA;
101 
    input ENA, CLKA, WEA, SSRA;
102 
 
103 
    output [31:0] DOB;
104 
    output [3:0] DOPB;
105 
    reg [31:0] dob_out;
106 
    reg [3:0] dopb_out;
107 
    wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7, dob_out8, dob_out9, dob_out10, dob_out11, dob_out12, dob_out13, dob_out14, dob_out15, dob_out16, dob_out17, dob_out18, dob_out19, dob_out20, dob_out21, dob_out22, dob_out23, dob_out24, dob_out25, dob_out26, dob_out27, dob_out28, dob_out29, dob_out30, dob_out31;
108 
    wire dopb0_out, dopb1_out, dopb2_out, dopb3_out;
109 
 
110 
    input [8:0] ADDRB;
111 
    input [31:0] DIB;
112 
    input [3:0] DIPB;
113 
    input ENB, CLKB, WEB, SSRB;
114 
 
115 
    reg [18431:0] mem;
116 
    reg [8:0] count;
117 
    reg [1:0] wr_mode_a, wr_mode_b;
118 
 
119 
    reg [5:0] ci, cj;
120 
    reg [5:0] dmi, dmj, dni, dnj, doi, doj, dai, daj, dbi, dbj, dci, dcj, ddi, ddj;
121 
    reg [5:0] pmi, pmj, pni, pnj, poi, poj, pai, paj, pbi, pbj, pci, pcj, pdi, pdj;
122 
 
123 
    wire [11:0] addra_int;
124 
    wire [3:0] dia_int;
125 
    wire ena_int, clka_int, wea_int, ssra_int;
126 
    wire [8:0] addrb_int;
127 
    wire [31:0] dib_int;
128 
    wire [3:0] dipb_int;
129 
    wire enb_int, clkb_int, web_int, ssrb_int;
130 
 
131 
    reg recovery_a, recovery_b;
132 
    reg address_collision;
133 
 
134 
    wire clka_enable = ena_int && wea_int && enb_int && address_collision;
135 
    wire clkb_enable = enb_int && web_int && ena_int && address_collision;
136 
    wire collision = clka_enable || clkb_enable;
137 
 
138 
    tri0 GSR = glbl.GSR;
139 
 
140 
    always @(GSR)
141 
        if (GSR) begin
142 
            assign doa_out = INIT_A[3:0];
143 
            assign dob_out = INIT_B[31:0];
144 
            assign dopb_out = INIT_B[35:32];
145 
        end
146 
        else begin
147 
            deassign doa_out;
148 
            deassign dob_out;
149 
            deassign dopb_out;
150 
        end
151 
 
152 
    buf b_doa_out0 (doa_out0, doa_out[0]);
153 
    buf b_doa_out1 (doa_out1, doa_out[1]);
154 
    buf b_doa_out2 (doa_out2, doa_out[2]);
155 
    buf b_doa_out3 (doa_out3, doa_out[3]);
156 
    buf b_dob_out0 (dob_out0, dob_out[0]);
157 
    buf b_dob_out1 (dob_out1, dob_out[1]);
158 
    buf b_dob_out2 (dob_out2, dob_out[2]);
159 
    buf b_dob_out3 (dob_out3, dob_out[3]);
160 
    buf b_dob_out4 (dob_out4, dob_out[4]);
161 
    buf b_dob_out5 (dob_out5, dob_out[5]);
162 
    buf b_dob_out6 (dob_out6, dob_out[6]);
163 
    buf b_dob_out7 (dob_out7, dob_out[7]);
164 
    buf b_dob_out8 (dob_out8, dob_out[8]);
165 
    buf b_dob_out9 (dob_out9, dob_out[9]);
166 
    buf b_dob_out10 (dob_out10, dob_out[10]);
167 
    buf b_dob_out11 (dob_out11, dob_out[11]);
168 
    buf b_dob_out12 (dob_out12, dob_out[12]);
169 
    buf b_dob_out13 (dob_out13, dob_out[13]);
170 
    buf b_dob_out14 (dob_out14, dob_out[14]);
171 
    buf b_dob_out15 (dob_out15, dob_out[15]);
172 
    buf b_dob_out16 (dob_out16, dob_out[16]);
173 
    buf b_dob_out17 (dob_out17, dob_out[17]);
174 
    buf b_dob_out18 (dob_out18, dob_out[18]);
175 
    buf b_dob_out19 (dob_out19, dob_out[19]);
176 
    buf b_dob_out20 (dob_out20, dob_out[20]);
177 
    buf b_dob_out21 (dob_out21, dob_out[21]);
178 
    buf b_dob_out22 (dob_out22, dob_out[22]);
179 
    buf b_dob_out23 (dob_out23, dob_out[23]);
180 
    buf b_dob_out24 (dob_out24, dob_out[24]);
181 
    buf b_dob_out25 (dob_out25, dob_out[25]);
182 
    buf b_dob_out26 (dob_out26, dob_out[26]);
183 
    buf b_dob_out27 (dob_out27, dob_out[27]);
184 
    buf b_dob_out28 (dob_out28, dob_out[28]);
185 
    buf b_dob_out29 (dob_out29, dob_out[29]);
186 
    buf b_dob_out30 (dob_out30, dob_out[30]);
187 
    buf b_dob_out31 (dob_out31, dob_out[31]);
188 
    buf b_dopb_out0 (dopb_out0, dopb_out[0]);
189 
    buf b_dopb_out1 (dopb_out1, dopb_out[1]);
190 
    buf b_dopb_out2 (dopb_out2, dopb_out[2]);
191 
    buf b_dopb_out3 (dopb_out3, dopb_out[3]);
192 
 
193 
    buf b_doa0 (DOA[0], doa_out0);
194 
    buf b_doa1 (DOA[1], doa_out1);
195 
    buf b_doa2 (DOA[2], doa_out2);
196 
    buf b_doa3 (DOA[3], doa_out3);
197 
    buf b_dob0 (DOB[0], dob_out0);
198 
    buf b_dob1 (DOB[1], dob_out1);
199 
    buf b_dob2 (DOB[2], dob_out2);
200 
    buf b_dob3 (DOB[3], dob_out3);
201 
    buf b_dob4 (DOB[4], dob_out4);
202 
    buf b_dob5 (DOB[5], dob_out5);
203 
    buf b_dob6 (DOB[6], dob_out6);
204 
    buf b_dob7 (DOB[7], dob_out7);
205 
    buf b_dob8 (DOB[8], dob_out8);
206 
    buf b_dob9 (DOB[9], dob_out9);
207 
    buf b_dob10 (DOB[10], dob_out10);
208 
    buf b_dob11 (DOB[11], dob_out11);
209 
    buf b_dob12 (DOB[12], dob_out12);
210 
    buf b_dob13 (DOB[13], dob_out13);
211 
    buf b_dob14 (DOB[14], dob_out14);
212 
    buf b_dob15 (DOB[15], dob_out15);
213 
    buf b_dob16 (DOB[16], dob_out16);
214 
    buf b_dob17 (DOB[17], dob_out17);
215 
    buf b_dob18 (DOB[18], dob_out18);
216 
    buf b_dob19 (DOB[19], dob_out19);
217 
    buf b_dob20 (DOB[20], dob_out20);
218 
    buf b_dob21 (DOB[21], dob_out21);
219 
    buf b_dob22 (DOB[22], dob_out22);
220 
    buf b_dob23 (DOB[23], dob_out23);
221 
    buf b_dob24 (DOB[24], dob_out24);
222 
    buf b_dob25 (DOB[25], dob_out25);
223 
    buf b_dob26 (DOB[26], dob_out26);
224 
    buf b_dob27 (DOB[27], dob_out27);
225 
    buf b_dob28 (DOB[28], dob_out28);
226 
    buf b_dob29 (DOB[29], dob_out29);
227 
    buf b_dob30 (DOB[30], dob_out30);
228 
    buf b_dob31 (DOB[31], dob_out31);
229 
    buf b_dopb0 (DOPB[0], dopb_out0);
230 
    buf b_dopb1 (DOPB[1], dopb_out1);
231 
    buf b_dopb2 (DOPB[2], dopb_out2);
232 
    buf b_dopb3 (DOPB[3], dopb_out3);
233 
 
234 
    buf b_addra_0 (addra_int[0], ADDRA[0]);
235 
    buf b_addra_1 (addra_int[1], ADDRA[1]);
236 
    buf b_addra_2 (addra_int[2], ADDRA[2]);
237 
    buf b_addra_3 (addra_int[3], ADDRA[3]);
238 
    buf b_addra_4 (addra_int[4], ADDRA[4]);
239 
    buf b_addra_5 (addra_int[5], ADDRA[5]);
240 
    buf b_addra_6 (addra_int[6], ADDRA[6]);
241 
    buf b_addra_7 (addra_int[7], ADDRA[7]);
242 
    buf b_addra_8 (addra_int[8], ADDRA[8]);
243 
    buf b_addra_9 (addra_int[9], ADDRA[9]);
244 
    buf b_addra_10 (addra_int[10], ADDRA[10]);
245 
    buf b_addra_11 (addra_int[11], ADDRA[11]);
246 
    buf b_dia_0 (dia_int[0], DIA[0]);
247 
    buf b_dia_1 (dia_int[1], DIA[1]);
248 
    buf b_dia_2 (dia_int[2], DIA[2]);
249 
    buf b_dia_3 (dia_int[3], DIA[3]);
250 
    buf b_ena (ena_int, ENA);
251 
    buf b_clka (clka_int, CLKA);
252 
    buf b_ssra (ssra_int, SSRA);
253 
    buf b_wea (wea_int, WEA);
254 
    buf b_addrb_0 (addrb_int[0], ADDRB[0]);
255 
    buf b_addrb_1 (addrb_int[1], ADDRB[1]);
256 
    buf b_addrb_2 (addrb_int[2], ADDRB[2]);
257 
    buf b_addrb_3 (addrb_int[3], ADDRB[3]);
258 
    buf b_addrb_4 (addrb_int[4], ADDRB[4]);
259 
    buf b_addrb_5 (addrb_int[5], ADDRB[5]);
260 
    buf b_addrb_6 (addrb_int[6], ADDRB[6]);
261 
    buf b_addrb_7 (addrb_int[7], ADDRB[7]);
262 
    buf b_addrb_8 (addrb_int[8], ADDRB[8]);
263 
    buf b_dib_0 (dib_int[0], DIB[0]);
264 
    buf b_dib_1 (dib_int[1], DIB[1]);
265 
    buf b_dib_2 (dib_int[2], DIB[2]);
266 
    buf b_dib_3 (dib_int[3], DIB[3]);
267 
    buf b_dib_4 (dib_int[4], DIB[4]);
268 
    buf b_dib_5 (dib_int[5], DIB[5]);
269 
    buf b_dib_6 (dib_int[6], DIB[6]);
270 
    buf b_dib_7 (dib_int[7], DIB[7]);
271 
    buf b_dib_8 (dib_int[8], DIB[8]);
272 
    buf b_dib_9 (dib_int[9], DIB[9]);
273 
    buf b_dib_10 (dib_int[10], DIB[10]);
274 
    buf b_dib_11 (dib_int[11], DIB[11]);
275 
    buf b_dib_12 (dib_int[12], DIB[12]);
276 
    buf b_dib_13 (dib_int[13], DIB[13]);
277 
    buf b_dib_14 (dib_int[14], DIB[14]);
278 
    buf b_dib_15 (dib_int[15], DIB[15]);
279 
    buf b_dib_16 (dib_int[16], DIB[16]);
280 
    buf b_dib_17 (dib_int[17], DIB[17]);
281 
    buf b_dib_18 (dib_int[18], DIB[18]);
282 
    buf b_dib_19 (dib_int[19], DIB[19]);
283 
    buf b_dib_20 (dib_int[20], DIB[20]);
284 
    buf b_dib_21 (dib_int[21], DIB[21]);
285 
    buf b_dib_22 (dib_int[22], DIB[22]);
286 
    buf b_dib_23 (dib_int[23], DIB[23]);
287 
    buf b_dib_24 (dib_int[24], DIB[24]);
288 
    buf b_dib_25 (dib_int[25], DIB[25]);
289 
    buf b_dib_26 (dib_int[26], DIB[26]);
290 
    buf b_dib_27 (dib_int[27], DIB[27]);
291 
    buf b_dib_28 (dib_int[28], DIB[28]);
292 
    buf b_dib_29 (dib_int[29], DIB[29]);
293 
    buf b_dib_30 (dib_int[30], DIB[30]);
294 
    buf b_dib_31 (dib_int[31], DIB[31]);
295 
    buf b_dipb_0 (dipb_int[0], DIPB[0]);
296 
    buf b_dipb_1 (dipb_int[1], DIPB[1]);
297 
    buf b_dipb_2 (dipb_int[2], DIPB[2]);
298 
    buf b_dipb_3 (dipb_int[3], DIPB[3]);
299 
    buf b_enb (enb_int, ENB);
300 
    buf b_clkb (clkb_int, CLKB);
301 
    buf b_ssrb (ssrb_int, SSRB);
302 
    buf b_web (web_int, WEB);
303 
 
304 
    initial begin
305 
        for (count = 0; count < 256; count = count + 1) begin
306 
            mem[count]            <= INIT_00[count];
307 
            mem[256 * 1 + count]  <= INIT_01[count];
308 
            mem[256 * 2 + count]  <= INIT_02[count];
309 
            mem[256 * 3 + count]  <= INIT_03[count];
310 
            mem[256 * 4 + count]  <= INIT_04[count];
311 
            mem[256 * 5 + count]  <= INIT_05[count];
312 
            mem[256 * 6 + count]  <= INIT_06[count];
313 
            mem[256 * 7 + count]  <= INIT_07[count];
314 
            mem[256 * 8 + count]  <= INIT_08[count];
315 
            mem[256 * 9 + count]  <= INIT_09[count];
316 
            mem[256 * 10 + count] <= INIT_0A[count];
317 
            mem[256 * 11 + count] <= INIT_0B[count];
318 
            mem[256 * 12 + count] <= INIT_0C[count];
319 
            mem[256 * 13 + count] <= INIT_0D[count];
320 
            mem[256 * 14 + count] <= INIT_0E[count];
321 
            mem[256 * 15 + count] <= INIT_0F[count];
322 
            mem[256 * 16 + count] <= INIT_10[count];
323 
            mem[256 * 17 + count] <= INIT_11[count];
324 
            mem[256 * 18 + count] <= INIT_12[count];
325 
            mem[256 * 19 + count] <= INIT_13[count];
326 
            mem[256 * 20 + count] <= INIT_14[count];
327 
            mem[256 * 21 + count] <= INIT_15[count];
328 
            mem[256 * 22 + count] <= INIT_16[count];
329 
            mem[256 * 23 + count] <= INIT_17[count];
330 
            mem[256 * 24 + count] <= INIT_18[count];
331 
            mem[256 * 25 + count] <= INIT_19[count];
332 
            mem[256 * 26 + count] <= INIT_1A[count];
333 
            mem[256 * 27 + count] <= INIT_1B[count];
334 
            mem[256 * 28 + count] <= INIT_1C[count];
335 
            mem[256 * 29 + count] <= INIT_1D[count];
336 
            mem[256 * 30 + count] <= INIT_1E[count];
337 
            mem[256 * 31 + count] <= INIT_1F[count];
338 
            mem[256 * 32 + count] <= INIT_20[count];
339 
            mem[256 * 33 + count] <= INIT_21[count];
340 
            mem[256 * 34 + count] <= INIT_22[count];
341 
            mem[256 * 35 + count] <= INIT_23[count];
342 
            mem[256 * 36 + count] <= INIT_24[count];
343 
            mem[256 * 37 + count] <= INIT_25[count];
344 
            mem[256 * 38 + count] <= INIT_26[count];
345 
            mem[256 * 39 + count] <= INIT_27[count];
346 
            mem[256 * 40 + count] <= INIT_28[count];
347 
            mem[256 * 41 + count] <= INIT_29[count];
348 
            mem[256 * 42 + count] <= INIT_2A[count];
349 
            mem[256 * 43 + count] <= INIT_2B[count];
350 
            mem[256 * 44 + count] <= INIT_2C[count];
351 
            mem[256 * 45 + count] <= INIT_2D[count];
352 
            mem[256 * 46 + count] <= INIT_2E[count];
353 
            mem[256 * 47 + count] <= INIT_2F[count];
354 
            mem[256 * 48 + count] <= INIT_30[count];
355 
            mem[256 * 49 + count] <= INIT_31[count];
356 
            mem[256 * 50 + count] <= INIT_32[count];
357 
            mem[256 * 51 + count] <= INIT_33[count];
358 
            mem[256 * 52 + count] <= INIT_34[count];
359 
            mem[256 * 53 + count] <= INIT_35[count];
360 
            mem[256 * 54 + count] <= INIT_36[count];
361 
            mem[256 * 55 + count] <= INIT_37[count];
362 
            mem[256 * 56 + count] <= INIT_38[count];
363 
            mem[256 * 57 + count] <= INIT_39[count];
364 
            mem[256 * 58 + count] <= INIT_3A[count];
365 
            mem[256 * 59 + count] <= INIT_3B[count];
366 
            mem[256 * 60 + count] <= INIT_3C[count];
367 
            mem[256 * 61 + count] <= INIT_3D[count];
368 
            mem[256 * 62 + count] <= INIT_3E[count];
369 
            mem[256 * 63 + count] <= INIT_3F[count];
370 
            mem[256 * 64 + count] <= INITP_00[count];
371 
            mem[256 * 65 + count] <= INITP_01[count];
372 
            mem[256 * 66 + count] <= INITP_02[count];
373 
            mem[256 * 67 + count] <= INITP_03[count];
374 
            mem[256 * 68 + count] <= INITP_04[count];
375 
            mem[256 * 69 + count] <= INITP_05[count];
376 
            mem[256 * 70 + count] <= INITP_06[count];
377 
            mem[256 * 71 + count] <= INITP_07[count];
378 
        end
379 
    end
380 
 
381 
    always @(addra_int or addrb_int) begin
382 
        address_collision <= 1'b0;
383 
        for (ci = 0; ci < 4; ci = ci + 1) begin
384 
            for (cj = 0; cj < 32; cj = cj + 1) begin
385 
                if ((addra_int * 4 + ci) == (addrb_int * 32 + cj)) begin
386 
                    address_collision <= 1'b1;
387 
                end
388 
            end
389 
        end
390 
    end
391 
 
392 
    // Data
393 
    always @(posedge recovery_a or posedge recovery_b) begin
394 
        if (((wr_mode_a == 2'b01) && (wr_mode_b == 2'b01)) ||
395 
            ((wr_mode_a != 2'b01) && (wr_mode_b != 2'b01))) begin
396 
            if (wea_int == 1 && web_int == 1) begin
397 
                for (dmi = 0; dmi < 4; dmi = dmi + 1) begin
398 
                    for (dmj = 0; dmj < 32; dmj = dmj + 1) begin
399 
                        if ((addra_int * 4 + dmi) == (addrb_int * 32 + dmj)) begin
400 
                            mem[addra_int * 4 + dmi] <= 1'bX;
401 
                        end
402 
                    end
403 
                end
404 
            end
405 
        end
406 
        recovery_a <= 0;
407 
        recovery_b <= 0;
408 
    end
409 
 
410 
    always @(posedge recovery_a or posedge recovery_b) begin
411 
        if ((wr_mode_a == 2'b01) && (wr_mode_b != 2'b01)) begin
412 
            if (wea_int == 1 && web_int == 1) begin
413 
                for (dni = 0; dni < 4; dni = dni + 1) begin
414 
                    for (dnj = 0; dnj < 32; dnj = dnj + 1) begin
415 
                        if ((addra_int * 4 + dni) == (addrb_int * 32 + dnj)) begin
416 
                            mem[addra_int * 4 + dni] <= dia_int[dni];
417 
                        end
418 
                    end
419 
                end
420 
            end
421 
        end
422 
    end
423 
 
424 
    always @(posedge recovery_a or posedge recovery_b) begin
425 
        if ((wr_mode_a != 2'b01) && (wr_mode_b == 2'b01)) begin
426 
            if (wea_int == 1 && web_int == 1) begin
427 
                for (doi = 0; doi < 4; doi = doi + 1) begin
428 
                    for (doj = 0; doj < 32; doj = doj + 1) begin
429 
                        if ((addra_int * 4 + doi) == (addrb_int * 32 + doj)) begin
430 
                            mem[addrb_int * 32 + doj] <= dib_int[doj];
431 
                        end
432 
                    end
433 
                end
434 
            end
435 
        end
436 
    end
437 
 
438 
    always @(posedge recovery_a or posedge recovery_b) begin
439 
        if ((wr_mode_b == 2'b00) || (wr_mode_b == 2'b10)) begin
440 
            if ((wea_int == 0) && (web_int == 1) && (ssra_int == 0)) begin
441 
                for (dai = 0; dai < 4; dai = dai + 1) begin
442 
                    for (daj = 0; daj < 32; daj = daj + 1) begin
443 
                        if ((addra_int * 4 + dai) == (addrb_int * 32 + daj)) begin
444 
                            doa_out[dai] <= 1'bX;
445 
                        end
446 
                    end
447 
                end
448 
            end
449 
        end
450 
    end
451 
 
452 
    always @(posedge recovery_a or posedge recovery_b) begin
453 
        if ((wr_mode_a == 2'b00) || (wr_mode_a == 2'b10)) begin
454 
            if ((wea_int == 1) && (web_int == 0) && (ssrb_int == 0)) begin
455 
                for (dbi = 0; dbi < 4; dbi = dbi + 1) begin
456 
                    for (dbj = 0; dbj < 32; dbj = dbj + 1) begin
457 
                        if ((addra_int * 4 + dbi) == (addrb_int * 32 + dbj)) begin
458 
                            dob_out[dbj] <= 1'bX;
459 
                        end
460 
                    end
461 
                end
462 
            end
463 
        end
464 
    end
465 
 
466 
    always @(posedge recovery_a or posedge recovery_b) begin
467 
        if (((wr_mode_a == 2'b00) && (wr_mode_b == 2'b00)) ||
468 
            (wr_mode_b == 2'b10) ||
469 
            ((wr_mode_a == 2'b01) && (wr_mode_b == 2'b00))) begin
470 
            if ((wea_int == 1) && (web_int == 1) && (ssra_int == 0)) begin
471 
                for (dci = 0; dci < 4; dci = dci + 1) begin
472 
                    for (dcj = 0; dcj < 32; dcj = dcj + 1) begin
473 
                        if ((addra_int * 4 + dci) == (addrb_int * 32 + dcj)) begin
474 
                            doa_out[dci] <= 1'bX;
475 
                        end
476 
                    end
477 
                end
478 
            end
479 
        end
480 
    end
481 
 
482 
    always @(posedge recovery_a or posedge recovery_b) begin
483 
        if (((wr_mode_a == 2'b00) && (wr_mode_b == 2'b00)) ||
484 
            (wr_mode_a == 2'b10) ||
485 
            ((wr_mode_a == 2'b00) && (wr_mode_b == 2'b01))) begin
486 
            if ((wea_int == 1) && (web_int == 1) && (ssrb_int == 0)) begin
487 
                for (ddi = 0; ddi < 4; ddi = ddi + 1) begin
488 
                    for (ddj = 0; ddj < 32; ddj = ddj + 1) begin
489 
                        if ((addra_int * 4 + ddi) == (addrb_int * 32 + ddj)) begin
490 
                            dob_out[ddj] <= 1'bX;
491 
                        end
492 
                    end
493 
                end
494 
            end
495 
        end
496 
    end
497 
 
498 
    initial begin
499 
        case (WRITE_MODE_A)
500 
            "WRITE_FIRST" : wr_mode_a <= 2'b00;
501 
            "READ_FIRST"  : wr_mode_a <= 2'b01;
502 
            "NO_CHANGE"   : wr_mode_a <= 2'b10;
503 
            default       : begin
504 
                                $display("Error : WRITE_MODE_A = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A);
505 
                                $finish;
506 
                            end
507 
        endcase
508 
    end
509 
 
510 
    initial begin
511 
        case (WRITE_MODE_B)
512 
            "WRITE_FIRST" : wr_mode_b <= 2'b00;
513 
            "READ_FIRST"  : wr_mode_b <= 2'b01;
514 
            "NO_CHANGE"   : wr_mode_b <= 2'b10;
515 
            default       : begin
516 
                                $display("Error : WRITE_MODE_B = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B);
517 
                                $finish;
518 
                            end
519 
        endcase
520 
    end
521 
 
522 
    // Port A
523 
    always @(posedge clka_int) begin
524 
        if (ena_int == 1'b1) begin
525 
            if (ssra_int == 1'b1) begin
526 
                doa_out[0] <= SRVAL_A[0];
527 
                doa_out[1] <= SRVAL_A[1];
528 
                doa_out[2] <= SRVAL_A[2];
529 
                doa_out[3] <= SRVAL_A[3];
530 
            end
531 
            else begin
532 
                if (wea_int == 1'b1) begin
533 
                    if (wr_mode_a == 2'b00) begin
534 
                        doa_out[0] <= dia_int[0];
535 
                        doa_out[1] <= dia_int[1];
536 
                        doa_out[2] <= dia_int[2];
537 
                        doa_out[3] <= dia_int[3];
538 
                    end
539 
                    else if (wr_mode_a == 2'b01) begin
540 
                        doa_out[0] <= mem[addra_int * 4 + 0];
541 
                        doa_out[1] <= mem[addra_int * 4 + 1];
542 
                        doa_out[2] <= mem[addra_int * 4 + 2];
543 
                        doa_out[3] <= mem[addra_int * 4 + 3];
544 
                    end
545 
                    else begin
546 
                        doa_out[0] <= doa_out[0];
547 
                        doa_out[1] <= doa_out[1];
548 
                        doa_out[2] <= doa_out[2];
549 
                        doa_out[3] <= doa_out[3];
550 
                    end
551 
                end
552 
                else begin
553 
                    doa_out[0] <= mem[addra_int * 4 + 0];
554 
                    doa_out[1] <= mem[addra_int * 4 + 1];
555 
                    doa_out[2] <= mem[addra_int * 4 + 2];
556 
                    doa_out[3] <= mem[addra_int * 4 + 3];
557 
                end
558 
            end
559 
        end
560 
    end
561 
 
562 
    always @(posedge clka_int) begin
563 
        if (ena_int == 1'b1 && wea_int == 1'b1) begin
564 
            mem[addra_int * 4 + 0] <= dia_int[0];
565 
            mem[addra_int * 4 + 1] <= dia_int[1];
566 
            mem[addra_int * 4 + 2] <= dia_int[2];
567 
            mem[addra_int * 4 + 3] <= dia_int[3];
568 
        end
569 
    end
570 
 
571 
    // Port B
572 
    always @(posedge clkb_int) begin
573 
        if (enb_int == 1'b1) begin
574 
            if (ssrb_int == 1'b1) begin
575 
                dob_out[0] <= SRVAL_B[0];
576 
                dob_out[1] <= SRVAL_B[1];
577 
                dob_out[2] <= SRVAL_B[2];
578 
                dob_out[3] <= SRVAL_B[3];
579 
                dob_out[4] <= SRVAL_B[4];
580 
                dob_out[5] <= SRVAL_B[5];
581 
                dob_out[6] <= SRVAL_B[6];
582 
                dob_out[7] <= SRVAL_B[7];
583 
                dob_out[8] <= SRVAL_B[8];
584 
                dob_out[9] <= SRVAL_B[9];
585 
                dob_out[10] <= SRVAL_B[10];
586 
                dob_out[11] <= SRVAL_B[11];
587 
                dob_out[12] <= SRVAL_B[12];
588 
                dob_out[13] <= SRVAL_B[13];
589 
                dob_out[14] <= SRVAL_B[14];
590 
                dob_out[15] <= SRVAL_B[15];
591 
                dob_out[16] <= SRVAL_B[16];
592 
                dob_out[17] <= SRVAL_B[17];
593 
                dob_out[18] <= SRVAL_B[18];
594 
                dob_out[19] <= SRVAL_B[19];
595 
                dob_out[20] <= SRVAL_B[20];
596 
                dob_out[21] <= SRVAL_B[21];
597 
                dob_out[22] <= SRVAL_B[22];
598 
                dob_out[23] <= SRVAL_B[23];
599 
                dob_out[24] <= SRVAL_B[24];
600 
                dob_out[25] <= SRVAL_B[25];
601 
                dob_out[26] <= SRVAL_B[26];
602 
                dob_out[27] <= SRVAL_B[27];
603 
                dob_out[28] <= SRVAL_B[28];
604 
                dob_out[29] <= SRVAL_B[29];
605 
                dob_out[30] <= SRVAL_B[30];
606 
                dob_out[31] <= SRVAL_B[31];
607 
                dopb_out[0] <= SRVAL_B[32];
608 
                dopb_out[1] <= SRVAL_B[33];
609 
                dopb_out[2] <= SRVAL_B[34];
610 
                dopb_out[3] <= SRVAL_B[35];
611 
            end
612 
            else begin
613 
                if (web_int == 1'b1) begin
614 
                    if (wr_mode_b == 2'b00) begin
615 
                        dob_out[0] <= dib_int[0];
616 
                        dob_out[1] <= dib_int[1];
617 
                        dob_out[2] <= dib_int[2];
618 
                        dob_out[3] <= dib_int[3];
619 
                        dob_out[4] <= dib_int[4];
620 
                        dob_out[5] <= dib_int[5];
621 
                        dob_out[6] <= dib_int[6];
622 
                        dob_out[7] <= dib_int[7];
623 
                        dob_out[8] <= dib_int[8];
624 
                        dob_out[9] <= dib_int[9];
625 
                        dob_out[10] <= dib_int[10];
626 
                        dob_out[11] <= dib_int[11];
627 
                        dob_out[12] <= dib_int[12];
628 
                        dob_out[13] <= dib_int[13];
629 
                        dob_out[14] <= dib_int[14];
630 
                        dob_out[15] <= dib_int[15];
631 
                        dob_out[16] <= dib_int[16];
632 
                        dob_out[17] <= dib_int[17];
633 
                        dob_out[18] <= dib_int[18];
634 
                        dob_out[19] <= dib_int[19];
635 
                        dob_out[20] <= dib_int[20];
636 
                        dob_out[21] <= dib_int[21];
637 
                        dob_out[22] <= dib_int[22];
638 
                        dob_out[23] <= dib_int[23];
639 
                        dob_out[24] <= dib_int[24];
640 
                        dob_out[25] <= dib_int[25];
641 
                        dob_out[26] <= dib_int[26];
642 
                        dob_out[27] <= dib_int[27];
643 
                        dob_out[28] <= dib_int[28];
644 
                        dob_out[29] <= dib_int[29];
645 
                        dob_out[30] <= dib_int[30];
646 
                        dob_out[31] <= dib_int[31];
647 
                        dopb_out[0] <= dipb_int[0];
648 
                        dopb_out[1] <= dipb_int[1];
649 
                        dopb_out[2] <= dipb_int[2];
650 
                        dopb_out[3] <= dipb_int[3];
651 
                    end
652 
                    else if (wr_mode_b == 2'b01) begin
653 
                        dob_out[0] <= mem[addrb_int * 32 + 0];
654 
                        dob_out[1] <= mem[addrb_int * 32 + 1];
655 
                        dob_out[2] <= mem[addrb_int * 32 + 2];
656 
                        dob_out[3] <= mem[addrb_int * 32 + 3];
657 
                        dob_out[4] <= mem[addrb_int * 32 + 4];
658 
                        dob_out[5] <= mem[addrb_int * 32 + 5];
659 
                        dob_out[6] <= mem[addrb_int * 32 + 6];
660 
                        dob_out[7] <= mem[addrb_int * 32 + 7];
661 
                        dob_out[8] <= mem[addrb_int * 32 + 8];
662 
                        dob_out[9] <= mem[addrb_int * 32 + 9];
663 
                        dob_out[10] <= mem[addrb_int * 32 + 10];
664 
                        dob_out[11] <= mem[addrb_int * 32 + 11];
665 
                        dob_out[12] <= mem[addrb_int * 32 + 12];
666 
                        dob_out[13] <= mem[addrb_int * 32 + 13];
667 
                        dob_out[14] <= mem[addrb_int * 32 + 14];
668 
                        dob_out[15] <= mem[addrb_int * 32 + 15];
669 
                        dob_out[16] <= mem[addrb_int * 32 + 16];
670 
                        dob_out[17] <= mem[addrb_int * 32 + 17];
671 
                        dob_out[18] <= mem[addrb_int * 32 + 18];
672 
                        dob_out[19] <= mem[addrb_int * 32 + 19];
673 
                        dob_out[20] <= mem[addrb_int * 32 + 20];
674 
                        dob_out[21] <= mem[addrb_int * 32 + 21];
675 
                        dob_out[22] <= mem[addrb_int * 32 + 22];
676 
                        dob_out[23] <= mem[addrb_int * 32 + 23];
677 
                        dob_out[24] <= mem[addrb_int * 32 + 24];
678 
                        dob_out[25] <= mem[addrb_int * 32 + 25];
679 
                        dob_out[26] <= mem[addrb_int * 32 + 26];
680 
                        dob_out[27] <= mem[addrb_int * 32 + 27];
681 
                        dob_out[28] <= mem[addrb_int * 32 + 28];
682 
                        dob_out[29] <= mem[addrb_int * 32 + 29];
683 
                        dob_out[30] <= mem[addrb_int * 32 + 30];
684 
                        dob_out[31] <= mem[addrb_int * 32 + 31];
685 
                        dopb_out[0] <= mem[16384 + addrb_int * 4 + 0];
686 
                        dopb_out[1] <= mem[16384 + addrb_int * 4 + 1];
687 
                        dopb_out[2] <= mem[16384 + addrb_int * 4 + 2];
688 
                        dopb_out[3] <= mem[16384 + addrb_int * 4 + 3];
689 
                    end
690 
                    else begin
691 
                        dob_out[0] <= dob_out[0];
692 
                        dob_out[1] <= dob_out[1];
693 
                        dob_out[2] <= dob_out[2];
694 
                        dob_out[3] <= dob_out[3];
695 
                        dob_out[4] <= dob_out[4];
696 
                        dob_out[5] <= dob_out[5];
697 
                        dob_out[6] <= dob_out[6];
698 
                        dob_out[7] <= dob_out[7];
699 
                        dob_out[8] <= dob_out[8];
700 
                        dob_out[9] <= dob_out[9];
701 
                        dob_out[10] <= dob_out[10];
702 
                        dob_out[11] <= dob_out[11];
703 
                        dob_out[12] <= dob_out[12];
704 
                        dob_out[13] <= dob_out[13];
705 
                        dob_out[14] <= dob_out[14];
706 
                        dob_out[15] <= dob_out[15];
707 
                        dob_out[16] <= dob_out[16];
708 
                        dob_out[17] <= dob_out[17];
709 
                        dob_out[18] <= dob_out[18];
710 
                        dob_out[19] <= dob_out[19];
711 
                        dob_out[20] <= dob_out[20];
712 
                        dob_out[21] <= dob_out[21];
713 
                        dob_out[22] <= dob_out[22];
714 
                        dob_out[23] <= dob_out[23];
715 
                        dob_out[24] <= dob_out[24];
716 
                        dob_out[25] <= dob_out[25];
717 
                        dob_out[26] <= dob_out[26];
718 
                        dob_out[27] <= dob_out[27];
719 
                        dob_out[28] <= dob_out[28];
720 
                        dob_out[29] <= dob_out[29];
721 
                        dob_out[30] <= dob_out[30];
722 
                        dob_out[31] <= dob_out[31];
723 
                        dopb_out[0] <= dopb_out[0];
724 
                        dopb_out[1] <= dopb_out[1];
725 
                        dopb_out[2] <= dopb_out[2];
726 
                        dopb_out[3] <= dopb_out[3];
727 
                    end
728 
                end
729 
                else begin
730 
                    dob_out[0] <= mem[addrb_int * 32 + 0];
731 
                    dob_out[1] <= mem[addrb_int * 32 + 1];
732 
                    dob_out[2] <= mem[addrb_int * 32 + 2];
733 
                    dob_out[3] <= mem[addrb_int * 32 + 3];
734 
                    dob_out[4] <= mem[addrb_int * 32 + 4];
735 
                    dob_out[5] <= mem[addrb_int * 32 + 5];
736 
                    dob_out[6] <= mem[addrb_int * 32 + 6];
737 
                    dob_out[7] <= mem[addrb_int * 32 + 7];
738 
                    dob_out[8] <= mem[addrb_int * 32 + 8];
739 
                    dob_out[9] <= mem[addrb_int * 32 + 9];
740 
                    dob_out[10] <= mem[addrb_int * 32 + 10];
741 
                    dob_out[11] <= mem[addrb_int * 32 + 11];
742 
                    dob_out[12] <= mem[addrb_int * 32 + 12];
743 
                    dob_out[13] <= mem[addrb_int * 32 + 13];
744 
                    dob_out[14] <= mem[addrb_int * 32 + 14];
745 
                    dob_out[15] <= mem[addrb_int * 32 + 15];
746 
                    dob_out[16] <= mem[addrb_int * 32 + 16];
747 
                    dob_out[17] <= mem[addrb_int * 32 + 17];
748 
                    dob_out[18] <= mem[addrb_int * 32 + 18];
749 
                    dob_out[19] <= mem[addrb_int * 32 + 19];
750 
                    dob_out[20] <= mem[addrb_int * 32 + 20];
751 
                    dob_out[21] <= mem[addrb_int * 32 + 21];
752 
                    dob_out[22] <= mem[addrb_int * 32 + 22];
753 
                    dob_out[23] <= mem[addrb_int * 32 + 23];
754 
                    dob_out[24] <= mem[addrb_int * 32 + 24];
755 
                    dob_out[25] <= mem[addrb_int * 32 + 25];
756 
                    dob_out[26] <= mem[addrb_int * 32 + 26];
757 
                    dob_out[27] <= mem[addrb_int * 32 + 27];
758 
                    dob_out[28] <= mem[addrb_int * 32 + 28];
759 
                    dob_out[29] <= mem[addrb_int * 32 + 29];
760 
                    dob_out[30] <= mem[addrb_int * 32 + 30];
761 
                    dob_out[31] <= mem[addrb_int * 32 + 31];
762 
                    dopb_out[0] <= mem[16384 + addrb_int * 4 + 0];
763 
                    dopb_out[1] <= mem[16384 + addrb_int * 4 + 1];
764 
                    dopb_out[2] <= mem[16384 + addrb_int * 4 + 2];
765 
                    dopb_out[3] <= mem[16384 + addrb_int * 4 + 3];
766 
                end
767 
            end
768 
        end
769 
    end
770 
 
771 
    always @(posedge clkb_int) begin
772 
        if (enb_int == 1'b1 && web_int == 1'b1) begin
773 
            mem[addrb_int * 32 + 0] <= dib_int[0];
774 
            mem[addrb_int * 32 + 1] <= dib_int[1];
775 
            mem[addrb_int * 32 + 2] <= dib_int[2];
776 
            mem[addrb_int * 32 + 3] <= dib_int[3];
777 
            mem[addrb_int * 32 + 4] <= dib_int[4];
778 
            mem[addrb_int * 32 + 5] <= dib_int[5];
779 
            mem[addrb_int * 32 + 6] <= dib_int[6];
780 
            mem[addrb_int * 32 + 7] <= dib_int[7];
781 
            mem[addrb_int * 32 + 8] <= dib_int[8];
782 
            mem[addrb_int * 32 + 9] <= dib_int[9];
783 
            mem[addrb_int * 32 + 10] <= dib_int[10];
784 
            mem[addrb_int * 32 + 11] <= dib_int[11];
785 
            mem[addrb_int * 32 + 12] <= dib_int[12];
786 
            mem[addrb_int * 32 + 13] <= dib_int[13];
787 
            mem[addrb_int * 32 + 14] <= dib_int[14];
788 
            mem[addrb_int * 32 + 15] <= dib_int[15];
789 
            mem[addrb_int * 32 + 16] <= dib_int[16];
790 
            mem[addrb_int * 32 + 17] <= dib_int[17];
791 
            mem[addrb_int * 32 + 18] <= dib_int[18];
792 
            mem[addrb_int * 32 + 19] <= dib_int[19];
793 
            mem[addrb_int * 32 + 20] <= dib_int[20];
794 
            mem[addrb_int * 32 + 21] <= dib_int[21];
795 
            mem[addrb_int * 32 + 22] <= dib_int[22];
796 
            mem[addrb_int * 32 + 23] <= dib_int[23];
797 
            mem[addrb_int * 32 + 24] <= dib_int[24];
798 
            mem[addrb_int * 32 + 25] <= dib_int[25];
799 
            mem[addrb_int * 32 + 26] <= dib_int[26];
800 
            mem[addrb_int * 32 + 27] <= dib_int[27];
801 
            mem[addrb_int * 32 + 28] <= dib_int[28];
802 
            mem[addrb_int * 32 + 29] <= dib_int[29];
803 
            mem[addrb_int * 32 + 30] <= dib_int[30];
804 
            mem[addrb_int * 32 + 31] <= dib_int[31];
805 
            mem[16384 + addrb_int * 4 + 0] <= dipb_int[0];
806 
            mem[16384 + addrb_int * 4 + 1] <= dipb_int[1];
807 
            mem[16384 + addrb_int * 4 + 2] <= dipb_int[2];
808 
            mem[16384 + addrb_int * 4 + 3] <= dipb_int[3];
809 
        end
810 
    end
811 
 
812 
    specify
813 
        (CLKA *> DOA) = (1, 1);
814 
        (CLKB *> DOB) = (1, 1);
815 
        (CLKB *> DOPB) = (1, 1);
816 
        $recovery (posedge CLKB, posedge CLKA &&& collision, 1, recovery_b);
817 
        $recovery (posedge CLKA, posedge CLKB &&& collision, 1, recovery_a);
818 
    endspecify
819 
 
820 
endmodule
821 
 
822 
`endcelldefine

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