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[/] [or1k/] [branches/] [mp3_stable/] [mp3/] [lib/] [xilinx/] [unisims/] [RAMB16_S9_S9.v] - Blame information for rev 1765

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1 266 lampret 
// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/RAMB16_S9_S9.v,v 1.1.1.1 2001-11-04 18:59:58 lampret Exp $
2 
 
3 
/*
4 
 
5 
FUNCTION        : 16x9x9 Block RAM with synchronous write capability
6 
 
7 
*/
8 
 
9 
`timescale  100 ps / 10 ps
10 
 
11 
`celldefine
12 
 
13 
module RAMB16_S9_S9 (DOA, DOPA, DOB, DOPB, ADDRA, CLKA, DIA, DIPA, ENA, SSRA, WEA, ADDRB, CLKB, DIB, DIPB, ENB, SSRB, WEB);
14 
    parameter cds_action = "ignore";
15 
    parameter INIT_A = 9'h0;
16 
    parameter INIT_B = 9'h0;
17 
    parameter SRVAL_A = 9'h0;
18 
    parameter SRVAL_B = 9'h0;
19 
    parameter WRITE_MODE_A = "WRITE_FIRST";
20 
    parameter WRITE_MODE_B = "WRITE_FIRST";
21 
 
22 
    parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
23 
    parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
24 
    parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
25 
    parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
26 
    parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
27 
    parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
28 
    parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
29 
    parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
30 
    parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
31 
    parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
32 
    parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
33 
    parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
40 
    parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
41 
    parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
42 
    parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
43 
    parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
44 
    parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
45 
    parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
46 
    parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
47 
    parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
48 
    parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
49 
    parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
50 
    parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
51 
    parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
52 
    parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
53 
    parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
54 
    parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
55 
    parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
56 
    parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
57 
    parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
58 
    parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
59 
    parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
60 
    parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
61 
    parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
62 
    parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
63 
    parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
64 
    parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
65 
    parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
66 
    parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
67 
    parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
68 
    parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
69 
    parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
70 
    parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
71 
    parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
72 
    parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
73 
    parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
74 
    parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
75 
    parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
76 
    parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
78 
    parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
79 
    parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
80 
    parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
81 
    parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
82 
    parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
83 
    parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
84 
    parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
85 
    parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
86 
    parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
87 
    parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
88 
    parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
89 
    parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
90 
    parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
91 
    parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
92 
    parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
93 
    parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
94 
 
95 
    output [7:0] DOA;
96 
    output [0:0] DOPA;
97 
    reg [7:0] doa_out;
98 
    reg [0:0] dopa_out;
99 
    wire doa_out0, doa_out1, doa_out2, doa_out3, doa_out4, doa_out5, doa_out6, doa_out7;
100 
    wire dopa0_out;
101 
 
102 
    input [10:0] ADDRA;
103 
    input [7:0] DIA;
104 
    input [0:0] DIPA;
105 
    input ENA, CLKA, WEA, SSRA;
106 
 
107 
    output [7:0] DOB;
108 
    output [0:0] DOPB;
109 
    reg [7:0] dob_out;
110 
    reg [0:0] dopb_out;
111 
    wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7;
112 
    wire dopb0_out;
113 
 
114 
    input [10:0] ADDRB;
115 
    input [7:0] DIB;
116 
    input [0:0] DIPB;
117 
    input ENB, CLKB, WEB, SSRB;
118 
 
119 
    reg [18431:0] mem;
120 
    reg [8:0] count;
121 
    reg [1:0] wr_mode_a, wr_mode_b;
122 
 
123 
    reg [5:0] ci, cj;
124 
    reg [5:0] dmi, dmj, dni, dnj, doi, doj, dai, daj, dbi, dbj, dci, dcj, ddi, ddj;
125 
    reg [5:0] pmi, pmj, pni, pnj, poi, poj, pai, paj, pbi, pbj, pci, pcj, pdi, pdj;
126 
 
127 
    wire [10:0] addra_int;
128 
    wire [7:0] dia_int;
129 
    wire [0:0] dipa_int;
130 
    wire ena_int, clka_int, wea_int, ssra_int;
131 
    wire [10:0] addrb_int;
132 
    wire [7:0] dib_int;
133 
    wire [0:0] dipb_int;
134 
    wire enb_int, clkb_int, web_int, ssrb_int;
135 
 
136 
    reg recovery_a, recovery_b;
137 
    reg address_collision;
138 
 
139 
    wire clka_enable = ena_int && wea_int && enb_int && address_collision;
140 
    wire clkb_enable = enb_int && web_int && ena_int && address_collision;
141 
    wire collision = clka_enable || clkb_enable;
142 
 
143 
    tri0 GSR = glbl.GSR;
144 
 
145 
    always @(GSR)
146 
        if (GSR) begin
147 
            assign doa_out = INIT_A[7:0];
148 
            assign dopa_out = INIT_A[8:8];
149 
            assign dob_out = INIT_B[7:0];
150 
            assign dopb_out = INIT_B[8:8];
151 
        end
152 
        else begin
153 
            deassign doa_out;
154 
            deassign dopa_out;
155 
            deassign dob_out;
156 
            deassign dopb_out;
157 
        end
158 
 
159 
    buf b_doa_out0 (doa_out0, doa_out[0]);
160 
    buf b_doa_out1 (doa_out1, doa_out[1]);
161 
    buf b_doa_out2 (doa_out2, doa_out[2]);
162 
    buf b_doa_out3 (doa_out3, doa_out[3]);
163 
    buf b_doa_out4 (doa_out4, doa_out[4]);
164 
    buf b_doa_out5 (doa_out5, doa_out[5]);
165 
    buf b_doa_out6 (doa_out6, doa_out[6]);
166 
    buf b_doa_out7 (doa_out7, doa_out[7]);
167 
    buf b_dopa_out0 (dopa_out0, dopa_out[0]);
168 
    buf b_dob_out0 (dob_out0, dob_out[0]);
169 
    buf b_dob_out1 (dob_out1, dob_out[1]);
170 
    buf b_dob_out2 (dob_out2, dob_out[2]);
171 
    buf b_dob_out3 (dob_out3, dob_out[3]);
172 
    buf b_dob_out4 (dob_out4, dob_out[4]);
173 
    buf b_dob_out5 (dob_out5, dob_out[5]);
174 
    buf b_dob_out6 (dob_out6, dob_out[6]);
175 
    buf b_dob_out7 (dob_out7, dob_out[7]);
176 
    buf b_dopb_out0 (dopb_out0, dopb_out[0]);
177 
 
178 
    buf b_doa0 (DOA[0], doa_out0);
179 
    buf b_doa1 (DOA[1], doa_out1);
180 
    buf b_doa2 (DOA[2], doa_out2);
181 
    buf b_doa3 (DOA[3], doa_out3);
182 
    buf b_doa4 (DOA[4], doa_out4);
183 
    buf b_doa5 (DOA[5], doa_out5);
184 
    buf b_doa6 (DOA[6], doa_out6);
185 
    buf b_doa7 (DOA[7], doa_out7);
186 
    buf b_dopa0 (DOPA[0], dopa_out0);
187 
    buf b_dob0 (DOB[0], dob_out0);
188 
    buf b_dob1 (DOB[1], dob_out1);
189 
    buf b_dob2 (DOB[2], dob_out2);
190 
    buf b_dob3 (DOB[3], dob_out3);
191 
    buf b_dob4 (DOB[4], dob_out4);
192 
    buf b_dob5 (DOB[5], dob_out5);
193 
    buf b_dob6 (DOB[6], dob_out6);
194 
    buf b_dob7 (DOB[7], dob_out7);
195 
    buf b_dopb0 (DOPB[0], dopb_out0);
196 
 
197 
    buf b_addra_0 (addra_int[0], ADDRA[0]);
198 
    buf b_addra_1 (addra_int[1], ADDRA[1]);
199 
    buf b_addra_2 (addra_int[2], ADDRA[2]);
200 
    buf b_addra_3 (addra_int[3], ADDRA[3]);
201 
    buf b_addra_4 (addra_int[4], ADDRA[4]);
202 
    buf b_addra_5 (addra_int[5], ADDRA[5]);
203 
    buf b_addra_6 (addra_int[6], ADDRA[6]);
204 
    buf b_addra_7 (addra_int[7], ADDRA[7]);
205 
    buf b_addra_8 (addra_int[8], ADDRA[8]);
206 
    buf b_addra_9 (addra_int[9], ADDRA[9]);
207 
    buf b_addra_10 (addra_int[10], ADDRA[10]);
208 
    buf b_dia_0 (dia_int[0], DIA[0]);
209 
    buf b_dia_1 (dia_int[1], DIA[1]);
210 
    buf b_dia_2 (dia_int[2], DIA[2]);
211 
    buf b_dia_3 (dia_int[3], DIA[3]);
212 
    buf b_dia_4 (dia_int[4], DIA[4]);
213 
    buf b_dia_5 (dia_int[5], DIA[5]);
214 
    buf b_dia_6 (dia_int[6], DIA[6]);
215 
    buf b_dia_7 (dia_int[7], DIA[7]);
216 
    buf b_dipa_0 (dipa_int[0], DIPA[0]);
217 
    buf b_ena (ena_int, ENA);
218 
    buf b_clka (clka_int, CLKA);
219 
    buf b_ssra (ssra_int, SSRA);
220 
    buf b_wea (wea_int, WEA);
221 
    buf b_addrb_0 (addrb_int[0], ADDRB[0]);
222 
    buf b_addrb_1 (addrb_int[1], ADDRB[1]);
223 
    buf b_addrb_2 (addrb_int[2], ADDRB[2]);
224 
    buf b_addrb_3 (addrb_int[3], ADDRB[3]);
225 
    buf b_addrb_4 (addrb_int[4], ADDRB[4]);
226 
    buf b_addrb_5 (addrb_int[5], ADDRB[5]);
227 
    buf b_addrb_6 (addrb_int[6], ADDRB[6]);
228 
    buf b_addrb_7 (addrb_int[7], ADDRB[7]);
229 
    buf b_addrb_8 (addrb_int[8], ADDRB[8]);
230 
    buf b_addrb_9 (addrb_int[9], ADDRB[9]);
231 
    buf b_addrb_10 (addrb_int[10], ADDRB[10]);
232 
    buf b_dib_0 (dib_int[0], DIB[0]);
233 
    buf b_dib_1 (dib_int[1], DIB[1]);
234 
    buf b_dib_2 (dib_int[2], DIB[2]);
235 
    buf b_dib_3 (dib_int[3], DIB[3]);
236 
    buf b_dib_4 (dib_int[4], DIB[4]);
237 
    buf b_dib_5 (dib_int[5], DIB[5]);
238 
    buf b_dib_6 (dib_int[6], DIB[6]);
239 
    buf b_dib_7 (dib_int[7], DIB[7]);
240 
    buf b_dipb_0 (dipb_int[0], DIPB[0]);
241 
    buf b_enb (enb_int, ENB);
242 
    buf b_clkb (clkb_int, CLKB);
243 
    buf b_ssrb (ssrb_int, SSRB);
244 
    buf b_web (web_int, WEB);
245 
 
246 
    initial begin
247 
        for (count = 0; count < 256; count = count + 1) begin
248 
            mem[count]            <= INIT_00[count];
249 
            mem[256 * 1 + count]  <= INIT_01[count];
250 
            mem[256 * 2 + count]  <= INIT_02[count];
251 
            mem[256 * 3 + count]  <= INIT_03[count];
252 
            mem[256 * 4 + count]  <= INIT_04[count];
253 
            mem[256 * 5 + count]  <= INIT_05[count];
254 
            mem[256 * 6 + count]  <= INIT_06[count];
255 
            mem[256 * 7 + count]  <= INIT_07[count];
256 
            mem[256 * 8 + count]  <= INIT_08[count];
257 
            mem[256 * 9 + count]  <= INIT_09[count];
258 
            mem[256 * 10 + count] <= INIT_0A[count];
259 
            mem[256 * 11 + count] <= INIT_0B[count];
260 
            mem[256 * 12 + count] <= INIT_0C[count];
261 
            mem[256 * 13 + count] <= INIT_0D[count];
262 
            mem[256 * 14 + count] <= INIT_0E[count];
263 
            mem[256 * 15 + count] <= INIT_0F[count];
264 
            mem[256 * 16 + count] <= INIT_10[count];
265 
            mem[256 * 17 + count] <= INIT_11[count];
266 
            mem[256 * 18 + count] <= INIT_12[count];
267 
            mem[256 * 19 + count] <= INIT_13[count];
268 
            mem[256 * 20 + count] <= INIT_14[count];
269 
            mem[256 * 21 + count] <= INIT_15[count];
270 
            mem[256 * 22 + count] <= INIT_16[count];
271 
            mem[256 * 23 + count] <= INIT_17[count];
272 
            mem[256 * 24 + count] <= INIT_18[count];
273 
            mem[256 * 25 + count] <= INIT_19[count];
274 
            mem[256 * 26 + count] <= INIT_1A[count];
275 
            mem[256 * 27 + count] <= INIT_1B[count];
276 
            mem[256 * 28 + count] <= INIT_1C[count];
277 
            mem[256 * 29 + count] <= INIT_1D[count];
278 
            mem[256 * 30 + count] <= INIT_1E[count];
279 
            mem[256 * 31 + count] <= INIT_1F[count];
280 
            mem[256 * 32 + count] <= INIT_20[count];
281 
            mem[256 * 33 + count] <= INIT_21[count];
282 
            mem[256 * 34 + count] <= INIT_22[count];
283 
            mem[256 * 35 + count] <= INIT_23[count];
284 
            mem[256 * 36 + count] <= INIT_24[count];
285 
            mem[256 * 37 + count] <= INIT_25[count];
286 
            mem[256 * 38 + count] <= INIT_26[count];
287 
            mem[256 * 39 + count] <= INIT_27[count];
288 
            mem[256 * 40 + count] <= INIT_28[count];
289 
            mem[256 * 41 + count] <= INIT_29[count];
290 
            mem[256 * 42 + count] <= INIT_2A[count];
291 
            mem[256 * 43 + count] <= INIT_2B[count];
292 
            mem[256 * 44 + count] <= INIT_2C[count];
293 
            mem[256 * 45 + count] <= INIT_2D[count];
294 
            mem[256 * 46 + count] <= INIT_2E[count];
295 
            mem[256 * 47 + count] <= INIT_2F[count];
296 
            mem[256 * 48 + count] <= INIT_30[count];
297 
            mem[256 * 49 + count] <= INIT_31[count];
298 
            mem[256 * 50 + count] <= INIT_32[count];
299 
            mem[256 * 51 + count] <= INIT_33[count];
300 
            mem[256 * 52 + count] <= INIT_34[count];
301 
            mem[256 * 53 + count] <= INIT_35[count];
302 
            mem[256 * 54 + count] <= INIT_36[count];
303 
            mem[256 * 55 + count] <= INIT_37[count];
304 
            mem[256 * 56 + count] <= INIT_38[count];
305 
            mem[256 * 57 + count] <= INIT_39[count];
306 
            mem[256 * 58 + count] <= INIT_3A[count];
307 
            mem[256 * 59 + count] <= INIT_3B[count];
308 
            mem[256 * 60 + count] <= INIT_3C[count];
309 
            mem[256 * 61 + count] <= INIT_3D[count];
310 
            mem[256 * 62 + count] <= INIT_3E[count];
311 
            mem[256 * 63 + count] <= INIT_3F[count];
312 
            mem[256 * 64 + count] <= INITP_00[count];
313 
            mem[256 * 65 + count] <= INITP_01[count];
314 
            mem[256 * 66 + count] <= INITP_02[count];
315 
            mem[256 * 67 + count] <= INITP_03[count];
316 
            mem[256 * 68 + count] <= INITP_04[count];
317 
            mem[256 * 69 + count] <= INITP_05[count];
318 
            mem[256 * 70 + count] <= INITP_06[count];
319 
            mem[256 * 71 + count] <= INITP_07[count];
320 
        end
321 
    end
322 
 
323 
    always @(addra_int or addrb_int) begin
324 
        address_collision <= 1'b0;
325 
        for (ci = 0; ci < 8; ci = ci + 1) begin
326 
            for (cj = 0; cj < 8; cj = cj + 1) begin
327 
                if ((addra_int * 8 + ci) == (addrb_int * 8 + cj)) begin
328 
                    address_collision <= 1'b1;
329 
                end
330 
            end
331 
        end
332 
    end
333 
 
334 
    // Data
335 
    always @(posedge recovery_a or posedge recovery_b) begin
336 
        if (((wr_mode_a == 2'b01) && (wr_mode_b == 2'b01)) ||
337 
            ((wr_mode_a != 2'b01) && (wr_mode_b != 2'b01))) begin
338 
            if (wea_int == 1 && web_int == 1) begin
339 
                for (dmi = 0; dmi < 8; dmi = dmi + 1) begin
340 
                    for (dmj = 0; dmj < 8; dmj = dmj + 1) begin
341 
                        if ((addra_int * 8 + dmi) == (addrb_int * 8 + dmj)) begin
342 
                            mem[addra_int * 8 + dmi] <= 1'bX;
343 
                        end
344 
                    end
345 
                end
346 
            end
347 
        end
348 
        recovery_a <= 0;
349 
        recovery_b <= 0;
350 
    end
351 
 
352 
    always @(posedge recovery_a or posedge recovery_b) begin
353 
        if ((wr_mode_a == 2'b01) && (wr_mode_b != 2'b01)) begin
354 
            if (wea_int == 1 && web_int == 1) begin
355 
                for (dni = 0; dni < 8; dni = dni + 1) begin
356 
                    for (dnj = 0; dnj < 8; dnj = dnj + 1) begin
357 
                        if ((addra_int * 8 + dni) == (addrb_int * 8 + dnj)) begin
358 
                            mem[addra_int * 8 + dni] <= dia_int[dni];
359 
                        end
360 
                    end
361 
                end
362 
            end
363 
        end
364 
    end
365 
 
366 
    always @(posedge recovery_a or posedge recovery_b) begin
367 
        if ((wr_mode_a != 2'b01) && (wr_mode_b == 2'b01)) begin
368 
            if (wea_int == 1 && web_int == 1) begin
369 
                for (doi = 0; doi < 8; doi = doi + 1) begin
370 
                    for (doj = 0; doj < 8; doj = doj + 1) begin
371 
                        if ((addra_int * 8 + doi) == (addrb_int * 8 + doj)) begin
372 
                            mem[addrb_int * 8 + doj] <= dib_int[doj];
373 
                        end
374 
                    end
375 
                end
376 
            end
377 
        end
378 
    end
379 
 
380 
    always @(posedge recovery_a or posedge recovery_b) begin
381 
        if ((wr_mode_b == 2'b00) || (wr_mode_b == 2'b10)) begin
382 
            if ((wea_int == 0) && (web_int == 1) && (ssra_int == 0)) begin
383 
                for (dai = 0; dai < 8; dai = dai + 1) begin
384 
                    for (daj = 0; daj < 8; daj = daj + 1) begin
385 
                        if ((addra_int * 8 + dai) == (addrb_int * 8 + daj)) begin
386 
                            doa_out[dai] <= 1'bX;
387 
                        end
388 
                    end
389 
                end
390 
            end
391 
        end
392 
    end
393 
 
394 
    always @(posedge recovery_a or posedge recovery_b) begin
395 
        if ((wr_mode_a == 2'b00) || (wr_mode_a == 2'b10)) begin
396 
            if ((wea_int == 1) && (web_int == 0) && (ssrb_int == 0)) begin
397 
                for (dbi = 0; dbi < 8; dbi = dbi + 1) begin
398 
                    for (dbj = 0; dbj < 8; dbj = dbj + 1) begin
399 
                        if ((addra_int * 8 + dbi) == (addrb_int * 8 + dbj)) begin
400 
                            dob_out[dbj] <= 1'bX;
401 
                        end
402 
                    end
403 
                end
404 
            end
405 
        end
406 
    end
407 
 
408 
    always @(posedge recovery_a or posedge recovery_b) begin
409 
        if (((wr_mode_a == 2'b00) && (wr_mode_b == 2'b00)) ||
410 
            (wr_mode_b == 2'b10) ||
411 
            ((wr_mode_a == 2'b01) && (wr_mode_b == 2'b00))) begin
412 
            if ((wea_int == 1) && (web_int == 1) && (ssra_int == 0)) begin
413 
                for (dci = 0; dci < 8; dci = dci + 1) begin
414 
                    for (dcj = 0; dcj < 8; dcj = dcj + 1) begin
415 
                        if ((addra_int * 8 + dci) == (addrb_int * 8 + dcj)) begin
416 
                            doa_out[dci] <= 1'bX;
417 
                        end
418 
                    end
419 
                end
420 
            end
421 
        end
422 
    end
423 
 
424 
    always @(posedge recovery_a or posedge recovery_b) begin
425 
        if (((wr_mode_a == 2'b00) && (wr_mode_b == 2'b00)) ||
426 
            (wr_mode_a == 2'b10) ||
427 
            ((wr_mode_a == 2'b00) && (wr_mode_b == 2'b01))) begin
428 
            if ((wea_int == 1) && (web_int == 1) && (ssrb_int == 0)) begin
429 
                for (ddi = 0; ddi < 8; ddi = ddi + 1) begin
430 
                    for (ddj = 0; ddj < 8; ddj = ddj + 1) begin
431 
                        if ((addra_int * 8 + ddi) == (addrb_int * 8 + ddj)) begin
432 
                            dob_out[ddj] <= 1'bX;
433 
                        end
434 
                    end
435 
                end
436 
            end
437 
        end
438 
    end
439 
 
440 
    // Parity
441 
    always @(posedge recovery_a or posedge recovery_b) begin
442 
        if (((wr_mode_a == 2'b01) && (wr_mode_b == 2'b01)) ||
443 
            ((wr_mode_a != 2'b01) && (wr_mode_b != 2'b01))) begin
444 
            if (wea_int == 1 && web_int == 1) begin
445 
                for (pmi = 0; pmi < 1; pmi = pmi + 1) begin
446 
                    for (pmj = 0; pmj < 1; pmj = pmj + 1) begin
447 
                        if ((addra_int * 1 + pmi) == (addrb_int * 1 + pmj)) begin
448 
                            mem[16384 + addra_int * 1 + pmi] <= 1'bX;
449 
                        end
450 
                    end
451 
                end
452 
            end
453 
        end
454 
        recovery_a <= 0;
455 
        recovery_b <= 0;
456 
    end
457 
 
458 
    always @(posedge recovery_a or posedge recovery_b) begin
459 
        if ((wr_mode_a == 2'b01) && (wr_mode_b != 2'b01)) begin
460 
            if (wea_int == 1 && web_int == 1) begin
461 
                for (pni = 0; pni < 1; pni = pni + 1) begin
462 
                    for (pnj = 0; pnj < 1; pnj = pnj + 1) begin
463 
                        if ((addra_int * 1 + pni) == (addrb_int * 1 + pnj)) begin
464 
                            mem[16384 + addra_int * 1 + pni] <= dipa_int[pni];
465 
                        end
466 
                    end
467 
                end
468 
            end
469 
        end
470 
    end
471 
 
472 
    always @(posedge recovery_a or posedge recovery_b) begin
473 
        if ((wr_mode_a != 2'b01) && (wr_mode_b == 2'b01)) begin
474 
            if (wea_int == 1 && web_int == 1) begin
475 
                for (poi = 0; poi < 1; poi = poi + 1) begin
476 
                    for (poj = 0; poj < 1; poj = poj + 1) begin
477 
                        if ((addra_int * 1 + poi) == (addrb_int * 1 + poj)) begin
478 
                            mem[16384 + addrb_int * 1 + poj] <= dipb_int[poj];
479 
                        end
480 
                    end
481 
                end
482 
            end
483 
        end
484 
    end
485 
 
486 
    always @(posedge recovery_a or posedge recovery_b) begin
487 
        if ((wr_mode_b == 2'b00) || (wr_mode_b == 2'b10)) begin
488 
            if ((wea_int == 0) && (web_int == 1) && (ssra_int == 0)) begin
489 
                for (pai = 0; pai < 1; pai = pai + 1) begin
490 
                    for (paj = 0; paj < 1; paj = paj + 1) begin
491 
                        if ((addra_int * 1 + pai) == (addrb_int * 1 + paj)) begin
492 
                            dopa_out[pai] <= 1'bX;
493 
                        end
494 
                    end
495 
                end
496 
            end
497 
        end
498 
    end
499 
 
500 
    always @(posedge recovery_a or posedge recovery_b) begin
501 
        if ((wr_mode_a == 2'b00) || (wr_mode_a == 2'b10)) begin
502 
            if ((wea_int == 1) && (web_int == 0) && (ssrb_int == 0)) begin
503 
                for (pbi = 0; pbi < 1; pbi = pbi + 1) begin
504 
                    for (pbj = 0; pbj < 1; pbj = pbj + 1) begin
505 
                        if ((addra_int * 1 + pbi) == (addrb_int * 1 + pbj)) begin
506 
                            dopb_out[pbj] <= 1'bX;
507 
                        end
508 
                    end
509 
                end
510 
            end
511 
        end
512 
    end
513 
 
514 
    always @(posedge recovery_a or posedge recovery_b) begin
515 
        if (((wr_mode_a == 2'b00) && (wr_mode_b == 2'b00)) ||
516 
            (wr_mode_b == 2'b10) ||
517 
            ((wr_mode_a == 2'b01) && (wr_mode_b == 2'b00))) begin
518 
            if ((wea_int == 1) && (web_int == 1) && (ssra_int == 0)) begin
519 
                for (pci = 0; pci < 1; pci = pci + 1) begin
520 
                    for (pcj = 0; pcj < 1; pcj = pcj + 1) begin
521 
                        if ((addra_int * 1 + pci) == (addrb_int * 1 + pcj)) begin
522 
                            dopa_out[pci] <= 1'bX;
523 
                        end
524 
                    end
525 
                end
526 
            end
527 
        end
528 
    end
529 
 
530 
    always @(posedge recovery_a or posedge recovery_b) begin
531 
        if (((wr_mode_a == 2'b00) && (wr_mode_b == 2'b00)) ||
532 
            (wr_mode_a == 2'b10) ||
533 
            ((wr_mode_a == 2'b00) && (wr_mode_b == 2'b01))) begin
534 
            if ((wea_int == 1) && (web_int == 1) && (ssrb_int == 0)) begin
535 
                for (pdi = 0; pdi < 1; pdi = pdi + 1) begin
536 
                    for (pdj = 0; pdj < 1; pdj = pdj + 1) begin
537 
                        if ((addra_int * 1 + pdi) == (addrb_int * 1 + pdj)) begin
538 
                            dopb_out[pdj] <= 1'bX;
539 
                        end
540 
                    end
541 
                end
542 
            end
543 
        end
544 
    end
545 
 
546 
    initial begin
547 
        case (WRITE_MODE_A)
548 
            "WRITE_FIRST" : wr_mode_a <= 2'b00;
549 
            "READ_FIRST"  : wr_mode_a <= 2'b01;
550 
            "NO_CHANGE"   : wr_mode_a <= 2'b10;
551 
            default       : begin
552 
                                $display("Error : WRITE_MODE_A = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A);
553 
                                $finish;
554 
                            end
555 
        endcase
556 
    end
557 
 
558 
    initial begin
559 
        case (WRITE_MODE_B)
560 
            "WRITE_FIRST" : wr_mode_b <= 2'b00;
561 
            "READ_FIRST"  : wr_mode_b <= 2'b01;
562 
            "NO_CHANGE"   : wr_mode_b <= 2'b10;
563 
            default       : begin
564 
                                $display("Error : WRITE_MODE_B = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B);
565 
                                $finish;
566 
                            end
567 
        endcase
568 
    end
569 
 
570 
    // Port A
571 
    always @(posedge clka_int) begin
572 
        if (ena_int == 1'b1) begin
573 
            if (ssra_int == 1'b1) begin
574 
                doa_out[0] <= SRVAL_A[0];
575 
                doa_out[1] <= SRVAL_A[1];
576 
                doa_out[2] <= SRVAL_A[2];
577 
                doa_out[3] <= SRVAL_A[3];
578 
                doa_out[4] <= SRVAL_A[4];
579 
                doa_out[5] <= SRVAL_A[5];
580 
                doa_out[6] <= SRVAL_A[6];
581 
                doa_out[7] <= SRVAL_A[7];
582 
                dopa_out[0] <= SRVAL_A[8];
583 
            end
584 
            else begin
585 
                if (wea_int == 1'b1) begin
586 
                    if (wr_mode_a == 2'b00) begin
587 
                        doa_out[0] <= dia_int[0];
588 
                        doa_out[1] <= dia_int[1];
589 
                        doa_out[2] <= dia_int[2];
590 
                        doa_out[3] <= dia_int[3];
591 
                        doa_out[4] <= dia_int[4];
592 
                        doa_out[5] <= dia_int[5];
593 
                        doa_out[6] <= dia_int[6];
594 
                        doa_out[7] <= dia_int[7];
595 
                        dopa_out[0] <= dipa_int[0];
596 
                    end
597 
                    else if (wr_mode_a == 2'b01) begin
598 
                        doa_out[0] <= mem[addra_int * 8 + 0];
599 
                        doa_out[1] <= mem[addra_int * 8 + 1];
600 
                        doa_out[2] <= mem[addra_int * 8 + 2];
601 
                        doa_out[3] <= mem[addra_int * 8 + 3];
602 
                        doa_out[4] <= mem[addra_int * 8 + 4];
603 
                        doa_out[5] <= mem[addra_int * 8 + 5];
604 
                        doa_out[6] <= mem[addra_int * 8 + 6];
605 
                        doa_out[7] <= mem[addra_int * 8 + 7];
606 
                        dopa_out[0] <= mem[16384 + addra_int * 1 + 0];
607 
                    end
608 
                    else begin
609 
                        doa_out[0] <= doa_out[0];
610 
                        doa_out[1] <= doa_out[1];
611 
                        doa_out[2] <= doa_out[2];
612 
                        doa_out[3] <= doa_out[3];
613 
                        doa_out[4] <= doa_out[4];
614 
                        doa_out[5] <= doa_out[5];
615 
                        doa_out[6] <= doa_out[6];
616 
                        doa_out[7] <= doa_out[7];
617 
                        dopa_out[0] <= dopa_out[0];
618 
                    end
619 
                end
620 
                else begin
621 
                    doa_out[0] <= mem[addra_int * 8 + 0];
622 
                    doa_out[1] <= mem[addra_int * 8 + 1];
623 
                    doa_out[2] <= mem[addra_int * 8 + 2];
624 
                    doa_out[3] <= mem[addra_int * 8 + 3];
625 
                    doa_out[4] <= mem[addra_int * 8 + 4];
626 
                    doa_out[5] <= mem[addra_int * 8 + 5];
627 
                    doa_out[6] <= mem[addra_int * 8 + 6];
628 
                    doa_out[7] <= mem[addra_int * 8 + 7];
629 
                    dopa_out[0] <= mem[16384 + addra_int * 1 + 0];
630 
                end
631 
            end
632 
        end
633 
    end
634 
 
635 
    always @(posedge clka_int) begin
636 
        if (ena_int == 1'b1 && wea_int == 1'b1) begin
637 
            mem[addra_int * 8 + 0] <= dia_int[0];
638 
            mem[addra_int * 8 + 1] <= dia_int[1];
639 
            mem[addra_int * 8 + 2] <= dia_int[2];
640 
            mem[addra_int * 8 + 3] <= dia_int[3];
641 
            mem[addra_int * 8 + 4] <= dia_int[4];
642 
            mem[addra_int * 8 + 5] <= dia_int[5];
643 
            mem[addra_int * 8 + 6] <= dia_int[6];
644 
            mem[addra_int * 8 + 7] <= dia_int[7];
645 
            mem[16384 + addra_int * 1 + 0] <= dipa_int[0];
646 
        end
647 
    end
648 
 
649 
    // Port B
650 
    always @(posedge clkb_int) begin
651 
        if (enb_int == 1'b1) begin
652 
            if (ssrb_int == 1'b1) begin
653 
                dob_out[0] <= SRVAL_B[0];
654 
                dob_out[1] <= SRVAL_B[1];
655 
                dob_out[2] <= SRVAL_B[2];
656 
                dob_out[3] <= SRVAL_B[3];
657 
                dob_out[4] <= SRVAL_B[4];
658 
                dob_out[5] <= SRVAL_B[5];
659 
                dob_out[6] <= SRVAL_B[6];
660 
                dob_out[7] <= SRVAL_B[7];
661 
                dopb_out[0] <= SRVAL_B[8];
662 
            end
663 
            else begin
664 
                if (web_int == 1'b1) begin
665 
                    if (wr_mode_b == 2'b00) begin
666 
                        dob_out[0] <= dib_int[0];
667 
                        dob_out[1] <= dib_int[1];
668 
                        dob_out[2] <= dib_int[2];
669 
                        dob_out[3] <= dib_int[3];
670 
                        dob_out[4] <= dib_int[4];
671 
                        dob_out[5] <= dib_int[5];
672 
                        dob_out[6] <= dib_int[6];
673 
                        dob_out[7] <= dib_int[7];
674 
                        dopb_out[0] <= dipb_int[0];
675 
                    end
676 
                    else if (wr_mode_b == 2'b01) begin
677 
                        dob_out[0] <= mem[addrb_int * 8 + 0];
678 
                        dob_out[1] <= mem[addrb_int * 8 + 1];
679 
                        dob_out[2] <= mem[addrb_int * 8 + 2];
680 
                        dob_out[3] <= mem[addrb_int * 8 + 3];
681 
                        dob_out[4] <= mem[addrb_int * 8 + 4];
682 
                        dob_out[5] <= mem[addrb_int * 8 + 5];
683 
                        dob_out[6] <= mem[addrb_int * 8 + 6];
684 
                        dob_out[7] <= mem[addrb_int * 8 + 7];
685 
                        dopb_out[0] <= mem[16384 + addrb_int * 1 + 0];
686 
                    end
687 
                    else begin
688 
                        dob_out[0] <= dob_out[0];
689 
                        dob_out[1] <= dob_out[1];
690 
                        dob_out[2] <= dob_out[2];
691 
                        dob_out[3] <= dob_out[3];
692 
                        dob_out[4] <= dob_out[4];
693 
                        dob_out[5] <= dob_out[5];
694 
                        dob_out[6] <= dob_out[6];
695 
                        dob_out[7] <= dob_out[7];
696 
                        dopb_out[0] <= dopb_out[0];
697 
                    end
698 
                end
699 
                else begin
700 
                    dob_out[0] <= mem[addrb_int * 8 + 0];
701 
                    dob_out[1] <= mem[addrb_int * 8 + 1];
702 
                    dob_out[2] <= mem[addrb_int * 8 + 2];
703 
                    dob_out[3] <= mem[addrb_int * 8 + 3];
704 
                    dob_out[4] <= mem[addrb_int * 8 + 4];
705 
                    dob_out[5] <= mem[addrb_int * 8 + 5];
706 
                    dob_out[6] <= mem[addrb_int * 8 + 6];
707 
                    dob_out[7] <= mem[addrb_int * 8 + 7];
708 
                    dopb_out[0] <= mem[16384 + addrb_int * 1 + 0];
709 
                end
710 
            end
711 
        end
712 
    end
713 
 
714 
    always @(posedge clkb_int) begin
715 
        if (enb_int == 1'b1 && web_int == 1'b1) begin
716 
            mem[addrb_int * 8 + 0] <= dib_int[0];
717 
            mem[addrb_int * 8 + 1] <= dib_int[1];
718 
            mem[addrb_int * 8 + 2] <= dib_int[2];
719 
            mem[addrb_int * 8 + 3] <= dib_int[3];
720 
            mem[addrb_int * 8 + 4] <= dib_int[4];
721 
            mem[addrb_int * 8 + 5] <= dib_int[5];
722 
            mem[addrb_int * 8 + 6] <= dib_int[6];
723 
            mem[addrb_int * 8 + 7] <= dib_int[7];
724 
            mem[16384 + addrb_int * 1 + 0] <= dipb_int[0];
725 
        end
726 
    end
727 
 
728 
    specify
729 
        (CLKA *> DOA) = (1, 1);
730 
        (CLKA *> DOPA) = (1, 1);
731 
        (CLKB *> DOB) = (1, 1);
732 
        (CLKB *> DOPB) = (1, 1);
733 
        $recovery (posedge CLKB, posedge CLKA &&& collision, 1, recovery_b);
734 
        $recovery (posedge CLKA, posedge CLKB &&& collision, 1, recovery_a);
735 
    endspecify
736 
 
737 
endmodule
738 
 
739 
`endcelldefine

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