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[/] [or1k/] [branches/] [mp3_stable/] [mp3/] [lib/] [xilinx/] [unisims/] [RAMB4_S8.v] - Blame information for rev 1765

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1 266 lampret 
// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/RAMB4_S8.v,v 1.1.1.1 2001-11-04 19:00:00 lampret Exp $
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/*
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FUNCTION        : 4x8 Block RAM with synchronous write capability
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*/
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`timescale  100 ps / 10 ps
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`celldefine
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module RAMB4_S8 (DO, ADDR, DI, EN, CLK, WE, RST);
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    parameter cds_action = "ignore";
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    parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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    output [7:0] DO;
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    reg d0_out, d1_out, d2_out, d3_out, d4_out, d5_out, d6_out, d7_out;
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    input [8:0] ADDR;
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    input [7:0] DI;
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    input EN, CLK, WE, RST;
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    reg [4095:0] mem;
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    reg [8:0] count;
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    wire [8:0] addr_int;
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    wire [7:0] di_int;
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    wire en_int, clk_int, we_int, rst_int;
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    tri0 GSR = glbl.GSR;
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    always @(GSR)
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        if (GSR)
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            begin
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                assign d0_out = 0;
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                assign d1_out = 0;
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                assign d2_out = 0;
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                assign d3_out = 0;
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                assign d4_out = 0;
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                assign d5_out = 0;
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                assign d6_out = 0;
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                assign d7_out = 0;
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            end
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        else
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            begin
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                deassign d0_out;
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                deassign d1_out;
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                deassign d2_out;
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                deassign d3_out;
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                deassign d4_out;
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                deassign d5_out;
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                deassign d6_out;
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                deassign d7_out;
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            end
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    buf b_do_out0 (DO[0], d0_out);
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    buf b_do_out1 (DO[1], d1_out);
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    buf b_do_out2 (DO[2], d2_out);
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    buf b_do_out3 (DO[3], d3_out);
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    buf b_do_out4 (DO[4], d4_out);
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    buf b_do_out5 (DO[5], d5_out);
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    buf b_do_out6 (DO[6], d6_out);
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    buf b_do_out7 (DO[7], d7_out);
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    buf b_addr_0 (addr_int[0], ADDR[0]);
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    buf b_addr_1 (addr_int[1], ADDR[1]);
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    buf b_addr_2 (addr_int[2], ADDR[2]);
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    buf b_addr_3 (addr_int[3], ADDR[3]);
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    buf b_addr_4 (addr_int[4], ADDR[4]);
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    buf b_addr_5 (addr_int[5], ADDR[5]);
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    buf b_addr_6 (addr_int[6], ADDR[6]);
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    buf b_addr_7 (addr_int[7], ADDR[7]);
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    buf b_addr_8 (addr_int[8], ADDR[8]);
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    buf b_di_0 (di_int[0], DI[0]);
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    buf b_di_1 (di_int[1], DI[1]);
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    buf b_di_2 (di_int[2], DI[2]);
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    buf b_di_3 (di_int[3], DI[3]);
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    buf b_di_4 (di_int[4], DI[4]);
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    buf b_di_5 (di_int[5], DI[5]);
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    buf b_di_6 (di_int[6], DI[6]);
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    buf b_di_7 (di_int[7], DI[7]);
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    buf b_en (en_int, EN);
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    buf b_clk (clk_int, CLK);
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    buf b_we (we_int, WE);
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    buf b_rst (rst_int, RST);
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    initial
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    begin
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        for (count = 0; count < 256; count = count + 1)
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        begin
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            mem[count]            <= INIT_00[count];
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            mem[256 * 1 + count]  <= INIT_01[count];
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            mem[256 * 2 + count]  <= INIT_02[count];
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            mem[256 * 3 + count]  <= INIT_03[count];
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            mem[256 * 4 + count]  <= INIT_04[count];
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            mem[256 * 5 + count]  <= INIT_05[count];
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            mem[256 * 6 + count]  <= INIT_06[count];
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            mem[256 * 7 + count]  <= INIT_07[count];
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            mem[256 * 8 + count]  <= INIT_08[count];
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            mem[256 * 9 + count]  <= INIT_09[count];
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            mem[256 * 10 + count] <= INIT_0A[count];
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            mem[256 * 11 + count] <= INIT_0B[count];
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            mem[256 * 12 + count] <= INIT_0C[count];
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            mem[256 * 13 + count] <= INIT_0D[count];
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            mem[256 * 14 + count] <= INIT_0E[count];
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            mem[256 * 15 + count] <= INIT_0F[count];
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        end
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    end
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    always @(posedge clk_int)
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    begin
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        if (en_int == 1'b1)
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            if (rst_int == 1'b1)
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                begin
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                    d0_out <= 0;
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                    d1_out <= 0;
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                    d2_out <= 0;
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                    d3_out <= 0;
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                    d4_out <= 0;
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                    d5_out <= 0;
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                    d6_out <= 0;
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                    d7_out <= 0;
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                end
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            else
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                if (we_int == 1'b1)
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                    begin
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                        d0_out <= di_int[0];
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                        d1_out <= di_int[1];
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                        d2_out <= di_int[2];
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                        d3_out <= di_int[3];
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                        d4_out <= di_int[4];
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                        d5_out <= di_int[5];
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                        d6_out <= di_int[6];
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                        d7_out <= di_int[7];
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                    end
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                else
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                    begin
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                        d0_out <= mem[addr_int * 8];
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                        d1_out <= mem[addr_int * 8 + 1];
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                        d2_out <= mem[addr_int * 8 + 2];
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                        d3_out <= mem[addr_int * 8 + 3];
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                        d4_out <= mem[addr_int * 8 + 4];
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                        d5_out <= mem[addr_int * 8 + 5];
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                        d6_out <= mem[addr_int * 8 + 6];
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                        d7_out <= mem[addr_int * 8 + 7];
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                    end
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    end
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    always @(posedge clk_int)
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    begin
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        if (en_int == 1'b1 && we_int == 1'b1)
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            begin
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                mem[addr_int * 8] <= di_int[0];
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                mem[addr_int * 8 + 1] <= di_int[1];
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                mem[addr_int * 8 + 2] <= di_int[2];
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                mem[addr_int * 8 + 3] <= di_int[3];
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                mem[addr_int * 8 + 4] <= di_int[4];
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                mem[addr_int * 8 + 5] <= di_int[5];
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                mem[addr_int * 8 + 6] <= di_int[6];
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                mem[addr_int * 8 + 7] <= di_int[7];
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            end
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    end
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    specify
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        (CLK => DO) = (1, 1);
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    endspecify
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endmodule
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`endcelldefine

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