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[/] [or1k/] [branches/] [mp3_stable/] [mp3/] [rtl/] [verilog/] [audio/] [audio_top.v] - Blame information for rev 1765

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1 266 lampret
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  MP3 demo Audio Interface Top Level                          ////
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////                                                              ////
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////  This file is part of the MP3 demo application               ////
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////  http://www.opencores.org/cores/or1k/mp3/                    ////
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////                                                              ////
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////  Description                                                 ////
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////  Audio interface top level for XSV board instantiating       ////
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////  FIFOs, WISHBONE interface and XSV CODEC interface.          ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - nothing really                                           ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Lior Shtram, lior.shtram@flextronicssemi.com          ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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module audio_top (
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        clk, rstn,
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        wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
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        wb_stb_i, wb_ack_o, wb_err_o,
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        mclk, lrclk, sclk, sdin, sdout,
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        audio_dreq,
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        igor, simon, USB_VPO, USB_VMO
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);
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input           clk;
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input           rstn;
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input [31:0]     wb_dat_i;
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output [31:0]    wb_dat_o;
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input [31:0]     wb_adr_i;
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input [3:0]      wb_sel_i;
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input           wb_we_i;
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input           wb_cyc_i;
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input           wb_stb_i;
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output          wb_ack_o;
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output          wb_err_o;
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output          mclk;
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output          lrclk;
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output          sclk;
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output          sdin;
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input           sdout;
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output          audio_dreq;
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input   igor;
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input   simon;
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output   USB_VPO;
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output   USB_VMO;
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parameter fifo_width = 16;
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wire [fifo_width-1:0]    fifo_data_i;
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wire [fifo_width-1:0]    fifo_data_o;
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wire            fifo_clk_wr;
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wire            fifo_clk_rd;
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wire            fifo_full;
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wire            fifo_empty;
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wire            fifo_almost_full;
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wire            fifo_almost_empty;
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wire            fifo_rd_en;
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wire            fifo_wr_en;
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assign audio_dreq = fifo_almost_empty;
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assign USB_VPO = fifo_almost_full;
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assign USB_VMO = fifo_almost_empty;
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audio_wb_if     i_audio_wb_if(
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                .rstn( rstn ),
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                .clk( clk ),
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                .wb_dat_i( wb_dat_i ),
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                .wb_dat_o( wb_dat_o ),
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                .wb_adr_i( wb_adr_i ),
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                .wb_sel_i( wb_sel_i ),
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                .wb_we_i( wb_we_i ),
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                .wb_cyc_i( wb_cyc_i ),
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                .wb_stb_i( wb_stb_i ),
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                .wb_ack_o( wb_ack_o ),
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                .wb_err_o( wb_err_o ),
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                .fifo_dat_o( fifo_data_i ),
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                .fifo_clk_o( fifo_clk_wr ),
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                .fifo_wr_en( fifo_wr_en ),
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                .fifo_full( fifo_full ),
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                .fifo_empty( fifo_empty ),
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                .fifo_almost_full( fifo_almost_full ),
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                .fifo_almost_empty( fifo_almost_empty ),
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                .simon(igor),
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                .igor(simon)
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                );
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`ifdef AUDIO_NO_FIFO
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fifo_empty_16   i_audio_fifo (
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                .AINIT( !rstn ),
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                .DIN( fifo_data_i ),
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                .DOUT( fifo_data_o ),
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//              .WR_CLK( fifo_clk_rd ),
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//              .RD_CLK( fifo_clk_wr ),
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                .WR_CLK( fifo_clk_wr ),
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                .RD_CLK( fifo_clk_rd ),
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                .RD_EN( fifo_rd_en ),
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                .WR_EN( fifo_wr_en ),
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                .EMPTY( fifo_empty ),
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                .FULL( fifo_full ),
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                .ALMOST_EMPTY( fifo_almost_empty ),
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                .ALMOST_FULL( fifo_almost_full )
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                );
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`else
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/*
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fifo8kx16 i_audio_fifo (
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                .AINIT( !rstn ),
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                .DIN( fifo_data_i ),
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                .DOUT( fifo_data_o ),
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//              .WR_CLK( fifo_clk_rd ),
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//              .RD_CLK( fifo_clk_wr ),
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                .WR_CLK( fifo_clk_wr ),
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                .RD_CLK( fifo_clk_rd ),
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                .RD_EN( fifo_rd_en ),
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                .WR_EN( fifo_wr_en ),
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                .EMPTY( fifo_empty ),
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                .FULL( fifo_full ),
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                .ALMOST_EMPTY( fifo_almost_empty ),
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                .ALMOST_FULL( fifo_almost_full )
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                );
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*/
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fifo_4095_16    i_audio_fifo (
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                .AINIT( !rstn ),
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                .DIN( fifo_data_i ),
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                .DOUT( fifo_data_o ),
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//              .WR_CLK( fifo_clk_rd ),
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//              .RD_CLK( fifo_clk_wr ),
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                .WR_CLK( fifo_clk_wr ),
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                .RD_CLK( fifo_clk_rd ),
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                .RD_EN( fifo_rd_en ),
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                .WR_EN( fifo_wr_en ),
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                .EMPTY( fifo_empty ),
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                .FULL( fifo_full ),
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                .ALMOST_EMPTY( fifo_almost_empty ),
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                .ALMOST_FULL( fifo_almost_full )
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                );
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`endif
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/*
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fifo_1023_16 i_audio_fifo (
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                .AINIT( !rstn ),
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                .DIN( fifo_data_i ),
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                .DOUT( fifo_data_o ),
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                .WR_CLK( clk ),
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                .RD_CLK( clk ),
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                .RD_EN( fifo_rd_en ),
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                .WR_EN( fifo_wr_en ),
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                .EMPTY( fifo_empty ),
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                .FULL( fifo_full ),
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                .ALMOST_EMPTY( fifo_almost_empty ),
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                .ALMOST_FULL( fifo_almost_full )
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                ); // synthesis black_box
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*/
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`ifdef UNUSED
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assign fifo_data_o = fifo_data_i;
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assign fifo_full = 1'b0;
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assign fifo_empty = 1'b0;
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assign fifo_almost_full = 1'b0;
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assign fifo_almost_empty = 1'b0;
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`endif
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audio_codec_if  i_audio_codec_if (
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                .rstn( rstn ),
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                .clk( clk ),
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                .fifo_clk( fifo_clk_rd ),
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                .fifo_data( fifo_data_o ),
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                .fifo_rd_en( fifo_rd_en ),
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                .sclk( sclk ),
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                .mclk( mclk ),
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                .lrclk( lrclk ),
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                .sdout( sdout ),
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                .sdin( sdin )
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                );
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endmodule

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