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//////////////////////////////////////////////////////////////////////
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//// ////
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//// dbg_trace.v ////
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//// ////
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//// ////
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//// This file is part of the SoC/OpenRISC Development Interface ////
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//// http://www.opencores.org/cores/DebugInterface/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Igor Mohor ////
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//// igorm@opencores.org ////
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//// ////
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//// ////
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//// All additional information is avaliable in the README.txt ////
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//// file. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000,2001 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1 2001/10/06 10:19:09 igorm
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// no message
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//
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// Revision 1.4 2001/09/20 10:11:25 mohor
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// Working version. Few bugs fixed, comments added.
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//
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// Revision 1.3 2001/09/19 11:55:13 mohor
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// Asynchronous set/reset not used in trace any more.
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//
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// Revision 1.2 2001/09/18 14:13:47 mohor
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// Trace fixed. Some registers changed, trace simplified.
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//
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// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
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// Initial official release.
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//
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// Revision 1.3 2001/06/01 22:22:35 mohor
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// This is a backup. It is not a fully working version. Not for use, yet.
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//
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// Revision 1.2 2001/05/18 13:10:00 mohor
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// Headers changed. All additional information is now avaliable in the README.txt file.
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//
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// Revision 1.1.1.1 2001/05/18 06:35:06 mohor
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// Initial release
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//
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//
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`include "dbg_timescale.v"
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`include "dbg_defines.v"
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// module Trace
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module dbg_trace (Wp, Bp, DataIn, OpSelect, LsStatus, IStatus, RiscStall_O,
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Mclk, Reset, TraceChain, ContinMode, TraceEnable_reg,
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WpTrigger, BpTrigger, LSSTrigger, ITrigger, TriggerOper, WpQualif,
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BpQualif, LSSQualif, IQualif, QualifOper, RecordPC, RecordLSEA,
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RecordLDATA, RecordSDATA, RecordReadSPR, RecordWriteSPR,
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RecordINSTR,
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WpTriggerValid, BpTriggerValid, LSSTriggerValid, ITriggerValid,
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WpQualifValid, BpQualifValid, LSSQualifValid, IQualifValid, ReadBuffer,
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WpStop, BpStop, LSSStop, IStop, StopOper, WpStopValid, BpStopValid,
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LSSStopValid, IStopValid
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);
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parameter Tp = 1;
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input [10:0] Wp; // Watchpoints
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input Bp; // Breakpoint
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input [31:0] DataIn; // Data from the RISC
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input [3:0] LsStatus; // Load/Store status
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input [1:0] IStatus; // Instruction status
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input Mclk; // Master clock (RISC clock)
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input Reset; // Reset
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input ReadBuffer; // Instruction for reading a sample from the Buffer
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// from registers
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input ContinMode; // Continous mode of the trace
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input TraceEnable_reg; // Trace is enabled (enabled by writing a bit in the register)
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input [10:0] WpTrigger; // Signals that come from registers to set the trigger
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input BpTrigger; // Signals that come from registers to set the trigger
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input [3:0] LSSTrigger; // Signals that come from registers to set the trigger
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input [1:0] ITrigger; // Signals that come from registers to set the trigger
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input [1:0] TriggerOper; // Signals that come from registers to set the trigger
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input [10:0] WpQualif; // Signals that come from registers to set the qualifier
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input BpQualif; // Signals that come from registers to set the qualifier
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input [3:0] LSSQualif; // Signals that come from registers to set the qualifier
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input [1:0] IQualif; // Signals that come from registers to set the qualifier
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input [1:0] QualifOper; // Signals that come from registers to set the qualifier
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input [10:0] WpStop; // Signals that come from registers to set the stop condition
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input BpStop; // Signals that come from registers to set the stop condition
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input [3:0] LSSStop; // Signals that come from registers to set the stop condition
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input [1:0] IStop; // Signals that come from registers to set the stop condition
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input [1:0] StopOper; // Signals that come from registers to set the stop condition
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input RecordPC; // Signals that come from registers for defining the sample for recording
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input RecordLSEA; // Signals that come from registers for defining the sample for recording
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input RecordLDATA; // Signals that come from registers for defining the sample for recording
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input RecordSDATA; // Signals that come from registers for defining the sample for recording
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input RecordReadSPR; // Signals that come from registers for defining the sample for recording
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input RecordWriteSPR; // Signals that come from registers for defining the sample for recording
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input RecordINSTR; // Signals that come from registers for defining the sample for recording
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input WpTriggerValid; // Signals that come from registers and indicate which trigger conditions are valid
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input BpTriggerValid; // Signals that come from registers and indicate which trigger conditions are valid
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input LSSTriggerValid; // Signals that come from registers and indicate which trigger conditions are valid
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input ITriggerValid; // Signals that come from registers and indicate which trigger conditions are valid
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input WpQualifValid; // Signals that come from registers and indicate which qualifier conditions are valid
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input BpQualifValid; // Signals that come from registers and indicate which qualifier conditions are valid
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input LSSQualifValid; // Signals that come from registers and indicate which qualifier conditions are valid
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input IQualifValid; // Signals that come from registers and indicate which qualifier conditions are valid
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input WpStopValid; // Signals that come from registers and indicate which stop conditions are valid
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input BpStopValid; // Signals that come from registers and indicate which stop conditions are valid
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input LSSStopValid; // Signals that come from registers and indicate which stop conditions are valid
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input IStopValid; // Signals that come from registers and indicate which stop conditions are valid
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// end: from registers
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output [`OPSELECTWIDTH-1:0] OpSelect; // Operation select (what kind of information is avaliable on the DataIn)
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output RiscStall_O; // CPU stall (stalls the RISC)
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output [39:0] TraceChain; // Scan shain from the trace module
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reg TraceEnable_d;
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reg TraceEnable;
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reg [`TRACECOUNTERWIDTH:0] Counter;
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reg [`TRACECOUNTERWIDTH-1:0] WritePointer;
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reg [`TRACECOUNTERWIDTH-1:0] ReadPointer;
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reg RiscStall;
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reg RiscStall_q;
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reg [`OPSELECTWIDTH-1:0] StallCounter;
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reg [`TRACESAMPLEWIDTH-1:0] Buffer[0:`TRACEBUFFERLENGTH-1];
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reg TriggerLatch;
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/**********************************************************************************
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* *
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* Generation of the trigger *
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* *
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**********************************************************************************/
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wire TempWpTrigger = |(Wp[10:0] & WpTrigger[10:0]);
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wire TempBpTrigger = Bp & BpTrigger;
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wire TempLSSTrigger = LsStatus[3:0] == LSSTrigger[3:0];
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wire TempITrigger = IStatus[1:0] == ITrigger[1:0];
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wire TempTriggerAND = ( (TempWpTrigger | ~WpTriggerValid)
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& (TempBpTrigger | ~BpTriggerValid)
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& (TempLSSTrigger | ~LSSTriggerValid)
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& (TempITrigger | ~ITriggerValid)
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)
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& (WpTriggerValid | BpTriggerValid | LSSTriggerValid | ITriggerValid);
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wire TempTriggerOR = ( (TempWpTrigger & WpTriggerValid)
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| (TempBpTrigger & BpTriggerValid)
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| (TempLSSTrigger & LSSTriggerValid)
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| (TempITrigger & ITriggerValid)
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);
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wire Trigger = TraceEnable & (~TriggerOper[1]? 1 : // any
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TriggerOper[0]? TempTriggerAND : TempTriggerOR // AND : OR
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);
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/**********************************************************************************
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* *
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* Generation of the qualifier *
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* *
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**********************************************************************************/
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wire TempWpQualifier = |(Wp[10:0] & WpQualif[10:0]);
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wire TempBpQualifier = Bp & BpQualif;
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wire TempLSSQualifier = LsStatus[3:0] == LSSQualif[3:0];
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wire TempIQualifier = IStatus[1:0] == IQualif[1:0];
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wire TempQualifierAND = ( (TempWpQualifier | ~WpQualifValid)
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& (TempBpQualifier | ~BpQualifValid)
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& (TempLSSQualifier | ~LSSQualifValid)
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& (TempIQualifier | ~IQualifValid)
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)
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& (WpQualifValid | BpQualifValid | LSSQualifValid | IQualifValid);
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wire TempQualifierOR = ( (TempWpQualifier & WpQualifValid)
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| (TempBpQualifier & BpQualifValid)
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| (TempLSSQualifier & LSSQualifValid)
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| (TempIQualifier & IQualifValid)
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);
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wire Stop;
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wire Qualifier = TraceEnable & ~Stop & (~QualifOper[1]? 1 : // any
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QualifOper[0]? TempQualifierAND : TempQualifierOR // AND : OR
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);
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/**********************************************************************************
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* *
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* Generation of the stop signal *
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* *
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**********************************************************************************/
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wire TempWpStop = |(Wp[10:0] & WpStop[10:0]);
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wire TempBpStop = Bp & BpStop;
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wire TempLSSStop = LsStatus[3:0] == LSSStop[3:0];
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wire TempIStop = IStatus[1:0] == IStop[1:0];
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wire TempStopAND = ( (TempWpStop | ~WpStopValid)
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& (TempBpStop | ~BpStopValid)
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& (TempLSSStop | ~LSSStopValid)
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& (TempIStop | ~IStopValid)
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)
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& (WpStopValid | BpStopValid | LSSStopValid | IStopValid);
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wire TempStopOR = ( (TempWpStop & WpStopValid)
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| (TempBpStop & BpStopValid)
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| (TempLSSStop & LSSStopValid)
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| (TempIStop & IStopValid)
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);
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assign Stop = TraceEnable & (~StopOper[1]? 0 : // nothing
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StopOper[0]? TempStopAND : TempStopOR // AND : OR
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);
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/**********************************************************************************
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* *
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* Generation of the TriggerLatch *
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* *
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**********************************************************************************/
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always @(posedge Mclk or posedge Reset)
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begin
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if(Reset)
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TriggerLatch<=#Tp 0;
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else
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if(TriggerLatch & ~TraceEnable)
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TriggerLatch<=#Tp 0;
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else
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if(Trigger)
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TriggerLatch<=#Tp 1;
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end
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/**********************************************************************************
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* *
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* TraceEnable Synchronization *
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* *
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**********************************************************************************/
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always @(posedge Mclk or posedge Reset)
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begin
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285 |
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if(Reset)
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begin
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287 |
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TraceEnable_d<=#Tp 0;
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TraceEnable<=#Tp 0;
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end
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else
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begin
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TraceEnable_d<=#Tp TraceEnable_reg;
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TraceEnable<=#Tp TraceEnable_d;
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end
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end
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/**********************************************************************************
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301 |
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* *
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* RiscStall, counter and pointers generation *
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303 |
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* *
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**********************************************************************************/
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reg BufferFullDetected;
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wire [`OPSELECTIONCOUNTER-1:0] RecEnable;
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308 |
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wire BufferFull = Counter[`TRACECOUNTERWIDTH:0]==`TRACEBUFFERLENGTH;
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wire BufferEmpty = Counter[`TRACECOUNTERWIDTH:0]==0;
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wire IncrementCounter = RiscStall_q & ~(BufferFull | BufferFullDetected) & Qualifier & RecEnable[StallCounter];
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wire IncrementPointer = RiscStall_q & (~BufferFull | ContinMode) & Qualifier & RecEnable[StallCounter];
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wire WriteSample = IncrementPointer;
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wire Decrement = ReadBuffer & ~BufferEmpty & (~ContinMode | ContinMode & ~TraceEnable);
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wire CounterEn = IncrementCounter ^ Decrement;
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318 |
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wire SyncResetCpuStall;
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wire ResetStallCounter;
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reg BufferFull_q;
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reg BufferFull_2q;
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reg Qualifier_mclk;
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always @(posedge Mclk)
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begin
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327 |
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Qualifier_mclk<=#Tp Qualifier;
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328 |
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BufferFull_q<=#Tp BufferFull;
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BufferFull_2q<=#Tp BufferFull_q;
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RiscStall_q <=#Tp RiscStall_O;
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end
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332 |
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334 |
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wire FirstCpuStall = Qualifier & ~Qualifier_mclk & TriggerLatch |
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335 |
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Qualifier_mclk & Trigger & ~TriggerLatch |
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336 |
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Qualifier & Trigger & ~Qualifier_mclk & ~TriggerLatch ;
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337 |
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338 |
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339 |
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//wire SyncSetCpuStall = Qualifier_mclk & TriggerLatch &
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340 |
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341 |
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wire SyncSetCpuStall = RiscStall_O & ~RiscStall_q |
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342 |
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Qualifier_mclk & TriggerLatch &
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343 |
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(
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344 |
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(~ContinMode & ~BufferFull & ~BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-1) |
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345 |
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(~ContinMode & ~BufferFull_q & BufferFull_2q & StallCounter==0) |
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346 |
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( ContinMode & StallCounter==`OPSELECTIONCOUNTER-1)
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347 |
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);
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348 |
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|
349 |
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assign SyncResetCpuStall = (
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350 |
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(~ContinMode & ~BufferFull & ~BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-2) |
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351 |
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(~ContinMode & ~BufferFull & BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-1) |
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352 |
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( ContinMode & StallCounter==`OPSELECTIONCOUNTER-2)
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353 |
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);
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354 |
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|
355 |
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assign RiscStall_O = FirstCpuStall | RiscStall;
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356 |
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|
357 |
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|
358 |
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always @(posedge Mclk or posedge Reset)
|
359 |
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begin
|
360 |
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if(Reset)
|
361 |
|
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Counter<=#Tp 0;
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362 |
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else
|
363 |
|
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if(CounterEn)
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364 |
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if(IncrementCounter)
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365 |
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Counter[`TRACECOUNTERWIDTH:0]<=#Tp Counter[`TRACECOUNTERWIDTH:0] + 1;
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366 |
|
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else
|
367 |
|
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Counter[`TRACECOUNTERWIDTH:0]<=#Tp Counter[`TRACECOUNTERWIDTH:0] - 1;
|
368 |
|
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end
|
369 |
|
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|
370 |
|
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|
371 |
|
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always @(posedge Mclk or posedge Reset)
|
372 |
|
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begin
|
373 |
|
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if(Reset)
|
374 |
|
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WritePointer<=#Tp 0;
|
375 |
|
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else
|
376 |
|
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if(IncrementPointer)
|
377 |
|
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WritePointer[`TRACECOUNTERWIDTH-1:0]<=#Tp WritePointer[`TRACECOUNTERWIDTH-1:0] + 1;
|
378 |
|
|
end
|
379 |
|
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|
380 |
|
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always @(posedge Mclk or posedge Reset)
|
381 |
|
|
begin
|
382 |
|
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if(Reset)
|
383 |
|
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ReadPointer<=#Tp 0;
|
384 |
|
|
else
|
385 |
|
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if(Decrement & ~ContinMode | Decrement & ContinMode & ~TraceEnable)
|
386 |
|
|
ReadPointer[`TRACECOUNTERWIDTH-1:0]<=#Tp ReadPointer[`TRACECOUNTERWIDTH-1:0] + 1;
|
387 |
|
|
else
|
388 |
|
|
if(ContinMode & IncrementPointer & (BufferFull | BufferFullDetected))
|
389 |
|
|
ReadPointer[`TRACECOUNTERWIDTH-1:0]<=#Tp WritePointer[`TRACECOUNTERWIDTH-1:0] + 1;
|
390 |
|
|
end
|
391 |
|
|
|
392 |
|
|
always @(posedge Mclk)
|
393 |
|
|
begin
|
394 |
|
|
if(~TraceEnable)
|
395 |
|
|
BufferFullDetected<=#Tp 0;
|
396 |
|
|
else
|
397 |
|
|
if(ContinMode & BufferFull)
|
398 |
|
|
BufferFullDetected<=#Tp 1;
|
399 |
|
|
end
|
400 |
|
|
|
401 |
|
|
|
402 |
|
|
always @(posedge Mclk or posedge Reset)
|
403 |
|
|
begin
|
404 |
|
|
if(Reset)
|
405 |
|
|
RiscStall<=#Tp 0;
|
406 |
|
|
else
|
407 |
|
|
if(SyncResetCpuStall)
|
408 |
|
|
RiscStall<=#Tp 0;
|
409 |
|
|
else
|
410 |
|
|
if(SyncSetCpuStall)
|
411 |
|
|
RiscStall<=#Tp 1;
|
412 |
|
|
end
|
413 |
|
|
|
414 |
|
|
|
415 |
|
|
always @(posedge Mclk)
|
416 |
|
|
begin
|
417 |
|
|
if(ResetStallCounter)
|
418 |
|
|
StallCounter<=#Tp 0;
|
419 |
|
|
else
|
420 |
|
|
if(RiscStall_q & (~BufferFull | ContinMode))
|
421 |
|
|
StallCounter<=#Tp StallCounter+1;
|
422 |
|
|
end
|
423 |
|
|
|
424 |
|
|
assign ResetStallCounter = StallCounter==(`OPSELECTIONCOUNTER-1) & ~BufferFull | Reset;
|
425 |
|
|
|
426 |
|
|
|
427 |
|
|
/**********************************************************************************
|
428 |
|
|
* *
|
429 |
|
|
* Valid status *
|
430 |
|
|
* *
|
431 |
|
|
**********************************************************************************/
|
432 |
|
|
wire Valid = ~BufferEmpty;
|
433 |
|
|
|
434 |
|
|
|
435 |
|
|
/**********************************************************************************
|
436 |
|
|
* *
|
437 |
|
|
* Writing and reading the sample to/from the buffer *
|
438 |
|
|
* *
|
439 |
|
|
**********************************************************************************/
|
440 |
|
|
always @ (posedge Mclk)
|
441 |
|
|
begin
|
442 |
|
|
if(WriteSample)
|
443 |
|
|
Buffer[WritePointer[`TRACECOUNTERWIDTH-1:0]]<={DataIn, 1'b0, OpSelect[`OPSELECTWIDTH-1:0]};
|
444 |
|
|
end
|
445 |
|
|
|
446 |
|
|
assign TraceChain = {Buffer[ReadPointer], 3'h0, Valid};
|
447 |
|
|
|
448 |
|
|
|
449 |
|
|
|
450 |
|
|
/**********************************************************************************
|
451 |
|
|
* *
|
452 |
|
|
* Operation select (to select which kind of data appears on the DATAIN lines) *
|
453 |
|
|
* *
|
454 |
|
|
**********************************************************************************/
|
455 |
|
|
assign OpSelect[`OPSELECTWIDTH-1:0] = StallCounter[`OPSELECTWIDTH-1:0];
|
456 |
|
|
|
457 |
|
|
|
458 |
|
|
|
459 |
|
|
/**********************************************************************************
|
460 |
|
|
* *
|
461 |
|
|
* Selecting which parts are going to be recorded as part of the sample *
|
462 |
|
|
* *
|
463 |
|
|
**********************************************************************************/
|
464 |
|
|
assign RecEnable = {1'b0, RecordINSTR, RecordWriteSPR, RecordReadSPR, RecordSDATA, RecordLDATA, RecordLSEA, RecordPC};
|
465 |
|
|
|
466 |
|
|
|
467 |
|
|
endmodule
|