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[/] [or1k/] [branches/] [mp3_stable/] [mp3/] [rtl/] [verilog/] [or1200.xcv/] [alu.v] - Blame information for rev 1765

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1 266 lampret
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's ALU                                                ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/cores/or1k/                        ////
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////                                                              ////
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////  Description                                                 ////
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////  ALU                                                         ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - make it smaller and faster                               ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
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// no message
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//
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// Revision 1.2  2001/08/09 13:39:33  lampret
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// Major clean-up.
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//
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// Revision 1.1  2001/07/20 00:46:03  lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "defines.v"
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module alu(clk, rst, a, b, mult_mac_result, macrc_op, alu_op, shrot_op, comp_op, result, flag);
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parameter width = `OPERAND_WIDTH;
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//
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// I/O
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//
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input                           clk;
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input                           rst;
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input   [width-1:0]              a;
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input   [width-1:0]              b;
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input   [width-1:0]              mult_mac_result;
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input                           macrc_op;
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input   [`ALUOP_WIDTH-1:0]       alu_op;
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input   [`SHROTOP_WIDTH-1:0]     shrot_op;
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input   [`COMPOP_WIDTH-1:0]      comp_op;
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output  [width-1:0]              result;
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output                          flag;
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//
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// Internal wires and regs
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//
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reg     [width-1:0]              result;
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reg     [width-1:0]              shifted_rotated;
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reg                             flagforw;
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reg                             flag_we;
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reg                             flag;
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integer                         d1;
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integer                         d2;
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wire    [width-1:0]              comp_a;
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wire    [width-1:0]              comp_b;
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wire                            a_eq_b;
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wire                            a_lt_b;
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//
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// Combinatorial logic
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//
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assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
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assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
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assign a_eq_b = (comp_a == comp_b);
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assign a_lt_b = (comp_a < comp_b);
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//
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// Simulation check for bad ALU behavior
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//
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`ifdef OR1200_WARNINGS
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// synopsys translate_off
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always @(result) begin
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        if (result === 32'bx)
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                $display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);
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end
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// synopsys translate_on
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`endif
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//
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// Central part of the ALU
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//
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always @(alu_op or a or b or macrc_op or shifted_rotated or mult_mac_result) begin
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        casex (alu_op)          // synopsys parallel_case full_case
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                `ALUOP_SHROT : begin
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                                result = shifted_rotated;
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                                flag_we = 1'b0;
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                end
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                `ALUOP_ADD : begin
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                                result = a + b;
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                                flag_we = 1'b0;
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                end
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                `ALUOP_SUB : begin
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                                result = a - b;
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                                flag_we = 1'b0;
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                end
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                `ALUOP_XOR : begin
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                                result = a ^ b;
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                                flag_we = 1'b0;
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                end
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                `ALUOP_OR  : begin
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                                result = a | b;
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                                flag_we = 1'b0;
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                end
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                `ALUOP_AND : begin
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                                result = a & b;
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                                flag_we = 1'b0;
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                end
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                `ALUOP_IMM : begin
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                                result = b;
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                                flag_we = 1'b0;
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                end
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                `ALUOP_MOVHI : begin
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                                if (macrc_op) begin
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                                        result = mult_mac_result;
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                                        flag_we = 1'b0;
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                                end
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                                else begin
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                                        result = b << 16;
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                                        flag_we = 1'b0;
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                                end
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                end
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                `ALUOP_MUL : begin
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                                result = mult_mac_result;
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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                                $display("%t: MUL operation: %h * %h = %h", $time, a, b, mult_mac_result);
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// synopsys translate_on
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`endif
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                                flag_we = 1'b0;
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                end
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// synopsys translate_off
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`ifdef SIM_ALU_DIV
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                `ALUOP_DIV : begin
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                                d1 = a;
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                                d2 = b;
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                                $display("DIV operation: %d / %d = %d", d1, d2, d1/d2);
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                                if (d2)
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                                        result = d1 / d2;
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                                else
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                                        result = 32'h00000000;
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                                flag_we = 1'b0;
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                end
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`endif
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`ifdef SIM_ALU_DIVU
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                `ALUOP_DIVU : begin
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                                if (b)
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                                        result = a / b;
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                                else
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                                        result = 32'h00000000;
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                                flag_we = 1'b0;
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                end
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`endif
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// synopsys translate_on
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                `ALUOP_COMP: begin
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                                flag_we = 1'b1;
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                                result = 32'd0;
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                end
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        endcase
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end
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//
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// Shifts and rotation
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//
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always @(shrot_op or a or b) begin
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        case (shrot_op)         // synopsys parallel_case full_case
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                `SHROTOP_SLL :
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                                shifted_rotated = (a << b[4:0]);
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                `SHROTOP_SRL :
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                                shifted_rotated = (a >> b[4:0]);
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`ifdef IMPL_ALU_ROTATE
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                `SHROTOP_ROR :
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                                shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) | (a >> b[4:0]);
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`endif
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                default:
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                                shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) | a >> b[4:0];
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        endcase
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end
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//
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// First type of compare implementation
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//
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`ifdef IMPL_ALU_COMP1
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always @(comp_op or a_eq_b or a_lt_b) begin
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        case(comp_op[2:0])       // synopsys parallel_case full_case
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                `COP_SFEQ:
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                        flagforw = a_eq_b;
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                `COP_SFNE:
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                        flagforw = ~a_eq_b;
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                `COP_SFGT:
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                        flagforw = ~(a_eq_b | a_lt_b);
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                `COP_SFGE:
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                        flagforw = ~a_lt_b;
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                `COP_SFLT:
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                        flagforw = a_lt_b;
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                `COP_SFLE:
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                        flagforw = a_eq_b | a_lt_b;
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// synopsys translate_off
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                default:
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                        flagforw = 1'bx;
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// synopsys translate_on
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        endcase
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end
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`endif
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//
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// Second type of compare implementation
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//
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`ifdef IMPL_ALU_COMP2
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always @(comp_op or a_eq_b or a_lt_b or comp_a or comp_b) begin
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        case(comp_op[2:0])       // synopsys parallel_case full_case
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                `COP_SFEQ:
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                        flagforw = (comp_a == comp_b);
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                `COP_SFNE:
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                        flagforw = (comp_a != comp_b);
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                `COP_SFGT:
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                        flagforw = (comp_a > comp_b);
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                `COP_SFGE:
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                        flagforw = (comp_a >= comp_b);
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                `COP_SFLT:
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                        flagforw = (comp_a < comp_b);
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                `COP_SFLE:
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                        flagforw = (comp_a <= comp_b);
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// synopsys translate_off
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                default:
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                        flagforw = 1'bx;
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// synopsys translate_on
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        endcase
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end
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`endif
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//
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// Flag bit
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//
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always @(posedge clk or posedge rst) begin
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        if (rst)
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                flag <= #1 1'b0;
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        else if (flag_we) begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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                $display("COMPARE: comp_a:%h comp_b:%h a_eq_b=%b a_lt_b=%b", comp_a, comp_b, a_eq_b, a_lt_b);
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// synopsys translate_on
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`endif
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                flag <= #1 flagforw;
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        end
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end
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endmodule

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