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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's ALU                                                ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  ALU                                                         ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
module alu(clk, rst, a, b, mult_mac_result, macrc_op, alu_op, shrot_op, comp_op, result, flag);
 
parameter width = `OPERAND_WIDTH;
 
//
// I/O
//
input                           clk;
input                           rst;
input   [width-1:0]              a;
input   [width-1:0]              b;
input   [width-1:0]              mult_mac_result;
input                           macrc_op;
input   [`ALUOP_WIDTH-1:0]       alu_op;
input   [`SHROTOP_WIDTH-1:0]     shrot_op;
input   [`COMPOP_WIDTH-1:0]      comp_op;
output  [width-1:0]              result;
output                          flag;
 
//
// Internal wires and regs
//
reg     [width-1:0]              result;
reg     [width-1:0]              shifted_rotated;
reg                             flagforw;
reg                             flag_we;
reg                             flag;
integer                         d1;
integer                         d2;
wire    [width-1:0]              comp_a;
wire    [width-1:0]              comp_b;
wire                            a_eq_b;
wire                            a_lt_b;
 
//
// Combinatorial logic
//
assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
assign a_eq_b = (comp_a == comp_b);
assign a_lt_b = (comp_a < comp_b);
 
//
// Simulation check for bad ALU behavior
//
`ifdef OR1200_WARNINGS
// synopsys translate_off
always @(result) begin
        if (result === 32'bx)
                $display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);
end
// synopsys translate_on
`endif
 
//
// Central part of the ALU
//
always @(alu_op or a or b or macrc_op or shifted_rotated or mult_mac_result) begin
        casex (alu_op)          // synopsys parallel_case full_case
                `ALUOP_SHROT : begin
                                result = shifted_rotated;
                                flag_we = 1'b0;
                end
                `ALUOP_ADD : begin
                                result = a + b;
                                flag_we = 1'b0;
                end
                `ALUOP_SUB : begin
                                result = a - b;
                                flag_we = 1'b0;
                end
                `ALUOP_XOR : begin
                                result = a ^ b;
                                flag_we = 1'b0;
                end
                `ALUOP_OR  : begin
                                result = a | b;
                                flag_we = 1'b0;
                end
                `ALUOP_AND : begin
                                result = a & b;
                                flag_we = 1'b0;
                end
                `ALUOP_IMM : begin
                                result = b;
                                flag_we = 1'b0;
                end
                `ALUOP_MOVHI : begin
                                if (macrc_op) begin
                                        result = mult_mac_result;
                                        flag_we = 1'b0;
                                end
                                else begin
                                        result = b << 16;
                                        flag_we = 1'b0;
                                end
                end
                `ALUOP_MUL : begin
                                result = mult_mac_result;
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: MUL operation: %h * %h = %h", $time, a, b, mult_mac_result);
// synopsys translate_on
`endif
                                flag_we = 1'b0;
                end
// synopsys translate_off
`ifdef SIM_ALU_DIV
                `ALUOP_DIV : begin
                                d1 = a;
                                d2 = b;
                                $display("DIV operation: %d / %d = %d", d1, d2, d1/d2);
                                if (d2)
                                        result = d1 / d2;
                                else
                                        result = 32'h00000000;
                                flag_we = 1'b0;
                end
`endif
`ifdef SIM_ALU_DIVU
                `ALUOP_DIVU : begin
                                if (b)
                                        result = a / b;
                                else
                                        result = 32'h00000000;
                                flag_we = 1'b0;
                end
`endif
// synopsys translate_on
                `ALUOP_COMP: begin
                                flag_we = 1'b1;
                                result = 32'd0;
                end
        endcase
end
 
//
// Shifts and rotation
//
always @(shrot_op or a or b) begin
        case (shrot_op)         // synopsys parallel_case full_case
                `SHROTOP_SLL :
                                shifted_rotated = (a << b[4:0]);
                `SHROTOP_SRL :
                                shifted_rotated = (a >> b[4:0]);
`ifdef IMPL_ALU_ROTATE
                `SHROTOP_ROR :
                                shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) | (a >> b[4:0]);
`endif
                default:
                                shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) | a >> b[4:0];
        endcase
end
 
//
// First type of compare implementation
//
`ifdef IMPL_ALU_COMP1
always @(comp_op or a_eq_b or a_lt_b) begin
        case(comp_op[2:0])       // synopsys parallel_case full_case
                `COP_SFEQ:
                        flagforw = a_eq_b;
                `COP_SFNE:
                        flagforw = ~a_eq_b;
                `COP_SFGT:
                        flagforw = ~(a_eq_b | a_lt_b);
                `COP_SFGE:
                        flagforw = ~a_lt_b;
                `COP_SFLT:
                        flagforw = a_lt_b;
                `COP_SFLE:
                        flagforw = a_eq_b | a_lt_b;
// synopsys translate_off
                default:
                        flagforw = 1'bx;
// synopsys translate_on
        endcase
end
`endif
 
//
// Second type of compare implementation
//
`ifdef IMPL_ALU_COMP2
always @(comp_op or a_eq_b or a_lt_b or comp_a or comp_b) begin
        case(comp_op[2:0])       // synopsys parallel_case full_case
                `COP_SFEQ:
                        flagforw = (comp_a == comp_b);
                `COP_SFNE:
                        flagforw = (comp_a != comp_b);
                `COP_SFGT:
                        flagforw = (comp_a > comp_b);
                `COP_SFGE:
                        flagforw = (comp_a >= comp_b);
                `COP_SFLT:
                        flagforw = (comp_a < comp_b);
                `COP_SFLE:
                        flagforw = (comp_a <= comp_b);
// synopsys translate_off
                default:
                        flagforw = 1'bx;
// synopsys translate_on
        endcase
end
`endif
 
//
// Flag bit
//
always @(posedge clk or posedge rst) begin
        if (rst)
                flag <= #1 1'b0;
        else if (flag_we) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                $display("COMPARE: comp_a:%h comp_b:%h a_eq_b=%b a_lt_b=%b", comp_a, comp_b, a_eq_b, a_lt_b);
// synopsys translate_on
`endif
                flag <= #1 flagforw;
        end
end
 
endmodule

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[/] [or1k/] [branches/] [mp3_stable/] [mp3/] [rtl/] [verilog/] [or1200.xcv/] [alu.v] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	266	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's ALU ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// ALU ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.1.1.1 2001/10/06 10:18:35 igorm`
48			`// no message`
49			`//`
50			`// Revision 1.2 2001/08/09 13:39:33 lampret`
51			`// Major clean-up.`
52			`//`
53			`// Revision 1.1 2001/07/20 00:46:03 lampret`
54			`// Development version of RTL. Libraries are missing.`
55			`//`
56			`//`
57
58			`// synopsys translate_off`
59			`include "timescale.v"
60			`// synopsys translate_on`
61			`include "defines.v"
62
63			`module alu(clk, rst, a, b, mult_mac_result, macrc_op, alu_op, shrot_op, comp_op, result, flag);`
64
65			parameter width = `OPERAND_WIDTH;
66
67			`//`
68			`// I/O`
69			`//`
70			`input clk;`
71			`input rst;`
72			`input [width-1:0] a;`
73			`input [width-1:0] b;`
74			`input [width-1:0] mult_mac_result;`
75			`input macrc_op;`
76			input [`ALUOP_WIDTH-1:0] alu_op;
77			input [`SHROTOP_WIDTH-1:0] shrot_op;
78			input [`COMPOP_WIDTH-1:0] comp_op;
79			`output [width-1:0] result;`
80			`output flag;`
81
82			`//`
83			`// Internal wires and regs`
84			`//`
85			`reg [width-1:0] result;`
86			`reg [width-1:0] shifted_rotated;`
87			`reg flagforw;`
88			`reg flag_we;`
89			`reg flag;`
90			`integer d1;`
91			`integer d2;`
92			`wire [width-1:0] comp_a;`
93			`wire [width-1:0] comp_b;`
94			`wire a_eq_b;`
95			`wire a_lt_b;`
96
97			`//`
98			`// Combinatorial logic`
99			`//`
100			`assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};`
101			`assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};`
102			`assign a_eq_b = (comp_a == comp_b);`
103			`assign a_lt_b = (comp_a < comp_b);`
104
105			`//`
106			`// Simulation check for bad ALU behavior`
107			`//`
108			`ifdef OR1200_WARNINGS
109			`// synopsys translate_off`
110			`always @(result) begin`
111			`if (result === 32'bx)`
112			`$display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);`
113			`end`
114			`// synopsys translate_on`
115			`endif
116
117			`//`
118			`// Central part of the ALU`
119			`//`
120			`always @(alu_op or a or b or macrc_op or shifted_rotated or mult_mac_result) begin`
121			`casex (alu_op) // synopsys parallel_case full_case`
122			`ALUOP_SHROT : begin
123			`result = shifted_rotated;`
124			`flag_we = 1'b0;`
125			`end`
126			`ALUOP_ADD : begin
127			`result = a + b;`
128			`flag_we = 1'b0;`
129			`end`
130			`ALUOP_SUB : begin
131			`result = a - b;`
132			`flag_we = 1'b0;`
133			`end`
134			`ALUOP_XOR : begin
135			`result = a ^ b;`
136			`flag_we = 1'b0;`
137			`end`
138			`ALUOP_OR : begin
139			`result = a \| b;`
140			`flag_we = 1'b0;`
141			`end`
142			`ALUOP_AND : begin
143			`result = a & b;`
144			`flag_we = 1'b0;`
145			`end`
146			`ALUOP_IMM : begin
147			`result = b;`
148			`flag_we = 1'b0;`
149			`end`
150			`ALUOP_MOVHI : begin
151			`if (macrc_op) begin`
152			`result = mult_mac_result;`
153			`flag_we = 1'b0;`
154			`end`
155			`else begin`
156			`result = b << 16;`
157			`flag_we = 1'b0;`
158			`end`
159			`end`
160			`ALUOP_MUL : begin
161			`result = mult_mac_result;`
162			`ifdef OR1200_VERBOSE
163			`// synopsys translate_off`
164			`$display("%t: MUL operation: %h * %h = %h", $time, a, b, mult_mac_result);`
165			`// synopsys translate_on`
166			`endif
167			`flag_we = 1'b0;`
168			`end`
169			`// synopsys translate_off`
170			`ifdef SIM_ALU_DIV
171			`ALUOP_DIV : begin
172			`d1 = a;`
173			`d2 = b;`
174			`$display("DIV operation: %d / %d = %d", d1, d2, d1/d2);`
175			`if (d2)`
176			`result = d1 / d2;`
177			`else`
178			`result = 32'h00000000;`
179			`flag_we = 1'b0;`
180			`end`
181			`endif
182			`ifdef SIM_ALU_DIVU
183			`ALUOP_DIVU : begin
184			`if (b)`
185			`result = a / b;`
186			`else`
187			`result = 32'h00000000;`
188			`flag_we = 1'b0;`
189			`end`
190			`endif
191			`// synopsys translate_on`
192			`ALUOP_COMP: begin
193			`flag_we = 1'b1;`
194			`result = 32'd0;`
195			`end`
196			`endcase`
197			`end`
198
199			`//`
200			`// Shifts and rotation`
201			`//`
202			`always @(shrot_op or a or b) begin`
203			`case (shrot_op) // synopsys parallel_case full_case`
204			`SHROTOP_SLL :
205			`shifted_rotated = (a << b[4:0]);`
206			`SHROTOP_SRL :
207			`shifted_rotated = (a >> b[4:0]);`
208			`ifdef IMPL_ALU_ROTATE
209			`SHROTOP_ROR :
210			`shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) \| (a >> b[4:0]);`
211			`endif
212			`default:`
213			`shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) \| a >> b[4:0];`
214			`endcase`
215			`end`
216
217			`//`
218			`// First type of compare implementation`
219			`//`
220			`ifdef IMPL_ALU_COMP1
221			`always @(comp_op or a_eq_b or a_lt_b) begin`
222			`case(comp_op[2:0]) // synopsys parallel_case full_case`
223			`COP_SFEQ:
224			`flagforw = a_eq_b;`
225			`COP_SFNE:
226			`flagforw = ~a_eq_b;`
227			`COP_SFGT:
228			`flagforw = ~(a_eq_b \| a_lt_b);`
229			`COP_SFGE:
230			`flagforw = ~a_lt_b;`
231			`COP_SFLT:
232			`flagforw = a_lt_b;`
233			`COP_SFLE:
234			`flagforw = a_eq_b \| a_lt_b;`
235			`// synopsys translate_off`
236			`default:`
237			`flagforw = 1'bx;`
238			`// synopsys translate_on`
239			`endcase`
240			`end`
241			`endif
242
243			`//`
244			`// Second type of compare implementation`
245			`//`
246			`ifdef IMPL_ALU_COMP2
247			`always @(comp_op or a_eq_b or a_lt_b or comp_a or comp_b) begin`
248			`case(comp_op[2:0]) // synopsys parallel_case full_case`
249			`COP_SFEQ:
250			`flagforw = (comp_a == comp_b);`
251			`COP_SFNE:
252			`flagforw = (comp_a != comp_b);`
253			`COP_SFGT:
254			`flagforw = (comp_a > comp_b);`
255			`COP_SFGE:
256			`flagforw = (comp_a >= comp_b);`
257			`COP_SFLT:
258			`flagforw = (comp_a < comp_b);`
259			`COP_SFLE:
260			`flagforw = (comp_a <= comp_b);`
261			`// synopsys translate_off`
262			`default:`
263			`flagforw = 1'bx;`
264			`// synopsys translate_on`
265			`endcase`
266			`end`
267			`endif
268
269			`//`
270			`// Flag bit`
271			`//`
272			`always @(posedge clk or posedge rst) begin`
273			`if (rst)`
274			`flag <= #1 1'b0;`
275			`else if (flag_we) begin`
276			`ifdef OR1200_VERBOSE
277			`// synopsys translate_off`
278			`$display("COMPARE: comp_a:%h comp_b:%h a_eq_b=%b a_lt_b=%b", comp_a, comp_b, a_eq_b, a_lt_b);`
279			`// synopsys translate_on`
280			`endif
281			`flag <= #1 flagforw;`
282			`end`
283			`end`
284
285			`endmodule`