| 1 |
266 |
lampret |
//////////////////////////////////////////////////////////////////////
|
| 2 |
|
|
//// ////
|
| 3 |
|
|
//// OR1200's VR, UPR and Configuration Registers ////
|
| 4 |
|
|
//// ////
|
| 5 |
|
|
//// This file is part of the OpenRISC 1200 project ////
|
| 6 |
|
|
//// http://www.opencores.org/cores/or1k/ ////
|
| 7 |
|
|
//// ////
|
| 8 |
|
|
//// Description ////
|
| 9 |
|
|
//// According to OR1K architectural and OR1200 specifications. ////
|
| 10 |
|
|
//// ////
|
| 11 |
|
|
//// To Do: ////
|
| 12 |
|
|
//// - done ////
|
| 13 |
|
|
//// ////
|
| 14 |
|
|
//// Author(s): ////
|
| 15 |
|
|
//// - Damjan Lampret, lampret@opencores.org ////
|
| 16 |
|
|
//// ////
|
| 17 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 18 |
|
|
//// ////
|
| 19 |
|
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
| 20 |
|
|
//// ////
|
| 21 |
|
|
//// This source file may be used and distributed without ////
|
| 22 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 23 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 24 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 25 |
|
|
//// ////
|
| 26 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 27 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 28 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 29 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 30 |
|
|
//// later version. ////
|
| 31 |
|
|
//// ////
|
| 32 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 33 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 34 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 35 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 36 |
|
|
//// details. ////
|
| 37 |
|
|
//// ////
|
| 38 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 39 |
|
|
//// Public License along with this source; if not, download it ////
|
| 40 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 41 |
|
|
//// ////
|
| 42 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 43 |
|
|
//
|
| 44 |
|
|
// CVS Revision History
|
| 45 |
|
|
//
|
| 46 |
|
|
// $Log: not supported by cvs2svn $
|
| 47 |
|
|
// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
|
| 48 |
|
|
// no message
|
| 49 |
|
|
//
|
| 50 |
|
|
// Revision 1.1 2001/08/09 13:39:33 lampret
|
| 51 |
|
|
// Major clean-up.
|
| 52 |
|
|
//
|
| 53 |
|
|
// Revision 1.1 2001/07/20 00:46:21 lampret
|
| 54 |
|
|
// Development version of RTL. Libraries are missing.
|
| 55 |
|
|
//
|
| 56 |
|
|
//
|
| 57 |
|
|
|
| 58 |
|
|
// synopsys translate_off
|
| 59 |
|
|
`include "timescale.v"
|
| 60 |
|
|
// synopsys translate_on
|
| 61 |
|
|
`include "defines.v"
|
| 62 |
|
|
|
| 63 |
|
|
module cfgr(
|
| 64 |
|
|
// RISC Internal Interface
|
| 65 |
|
|
clk, rst, spr_addr, spr_dat_o
|
| 66 |
|
|
);
|
| 67 |
|
|
|
| 68 |
|
|
//
|
| 69 |
|
|
// RISC Internal Interface
|
| 70 |
|
|
//
|
| 71 |
|
|
input clk; // Clock
|
| 72 |
|
|
input rst; // Reset
|
| 73 |
|
|
input [31:0] spr_addr; // SPR Address
|
| 74 |
|
|
output [31:0] spr_dat_o; // SPR Read Data
|
| 75 |
|
|
|
| 76 |
|
|
//
|
| 77 |
|
|
// Internal wires & registers
|
| 78 |
|
|
//
|
| 79 |
|
|
reg [31:0] spr_dat_o; // SPR Read Data
|
| 80 |
|
|
|
| 81 |
|
|
`ifdef CFGR_IMPLEMENTED
|
| 82 |
|
|
|
| 83 |
|
|
//
|
| 84 |
|
|
// Implementation of VR, UPR and configuration registers
|
| 85 |
|
|
//
|
| 86 |
|
|
always @(spr_addr)
|
| 87 |
|
|
`ifdef SYS_FULL_DECODE
|
| 88 |
|
|
if (!spr_addr[31:4])
|
| 89 |
|
|
`endif
|
| 90 |
|
|
case(spr_addr[3:0])
|
| 91 |
|
|
`SPRGRP_SYS_VR: begin
|
| 92 |
|
|
spr_dat_o[`VR_REV_BITS] = `VR_REV;
|
| 93 |
|
|
spr_dat_o[`VR_RES1_BITS] = `VR_RES1;
|
| 94 |
|
|
spr_dat_o[`VR_CFG_BITS] = `VR_CFG;
|
| 95 |
|
|
spr_dat_o[`VR_VER_BITS] = `VR_VER;
|
| 96 |
|
|
end
|
| 97 |
|
|
`SPRGRP_SYS_UPR: begin
|
| 98 |
|
|
spr_dat_o[`UPR_UP_BITS] = `UPR_UP;
|
| 99 |
|
|
spr_dat_o[`UPR_DCP_BITS] = `UPR_DCP;
|
| 100 |
|
|
spr_dat_o[`UPR_ICP_BITS] = `UPR_ICP;
|
| 101 |
|
|
spr_dat_o[`UPR_DMP_BITS] = `UPR_DMP;
|
| 102 |
|
|
spr_dat_o[`UPR_IMP_BITS] = `UPR_IMP;
|
| 103 |
|
|
spr_dat_o[`UPR_MP_BITS] = `UPR_MP;
|
| 104 |
|
|
spr_dat_o[`UPR_DUP_BITS] = `UPR_DUP;
|
| 105 |
|
|
spr_dat_o[`UPR_PCUP_BITS] = `UPR_PCUP;
|
| 106 |
|
|
spr_dat_o[`UPR_PMP_BITS] = `UPR_PMP;
|
| 107 |
|
|
spr_dat_o[`UPR_PICP_BITS] = `UPR_PICP;
|
| 108 |
|
|
spr_dat_o[`UPR_TTP_BITS] = `UPR_TTP;
|
| 109 |
|
|
spr_dat_o[`UPR_RES1_BITS] = `UPR_RES1;
|
| 110 |
|
|
spr_dat_o[`UPR_CUP_BITS] = `UPR_CUP;
|
| 111 |
|
|
end
|
| 112 |
|
|
`SPRGRP_SYS_CPUCFGR: begin
|
| 113 |
|
|
spr_dat_o[`CPUCFGR_NSGF_BITS] = `CPUCFGR_NSGF;
|
| 114 |
|
|
spr_dat_o[`CPUCFGR_HGF_BITS] = `CPUCFGR_HGF;
|
| 115 |
|
|
spr_dat_o[`CPUCFGR_OB32S_BITS] = `CPUCFGR_OB32S;
|
| 116 |
|
|
spr_dat_o[`CPUCFGR_OB64S_BITS] = `CPUCFGR_OB64S;
|
| 117 |
|
|
spr_dat_o[`CPUCFGR_OF32S_BITS] = `CPUCFGR_OF32S;
|
| 118 |
|
|
spr_dat_o[`CPUCFGR_OF64S_BITS] = `CPUCFGR_OF64S;
|
| 119 |
|
|
spr_dat_o[`CPUCFGR_OV64S_BITS] = `CPUCFGR_OV64S;
|
| 120 |
|
|
spr_dat_o[`CPUCFGR_RES1_BITS] = `CPUCFGR_RES1;
|
| 121 |
|
|
end
|
| 122 |
|
|
`SPRGRP_SYS_DMMUCFGR: begin
|
| 123 |
|
|
spr_dat_o[`DMMUCFGR_NTW_BITS] = `DMMUCFGR_NTW;
|
| 124 |
|
|
spr_dat_o[`DMMUCFGR_NTS_BITS] = `DMMUCFGR_NTS;
|
| 125 |
|
|
spr_dat_o[`DMMUCFGR_NAE_BITS] = `DMMUCFGR_NAE;
|
| 126 |
|
|
spr_dat_o[`DMMUCFGR_CRI_BITS] = `DMMUCFGR_CRI;
|
| 127 |
|
|
spr_dat_o[`DMMUCFGR_PRI_BITS] = `DMMUCFGR_PRI;
|
| 128 |
|
|
spr_dat_o[`DMMUCFGR_TEIRI_BITS] = `DMMUCFGR_TEIRI;
|
| 129 |
|
|
spr_dat_o[`DMMUCFGR_HTR_BITS] = `DMMUCFGR_HTR;
|
| 130 |
|
|
spr_dat_o[`DMMUCFGR_RES1_BITS] = `DMMUCFGR_RES1;
|
| 131 |
|
|
end
|
| 132 |
|
|
`SPRGRP_SYS_IMMUCFGR: begin
|
| 133 |
|
|
spr_dat_o[`IMMUCFGR_NTW_BITS] = `IMMUCFGR_NTW;
|
| 134 |
|
|
spr_dat_o[`IMMUCFGR_NTS_BITS] = `IMMUCFGR_NTS;
|
| 135 |
|
|
spr_dat_o[`IMMUCFGR_NAE_BITS] = `IMMUCFGR_NAE;
|
| 136 |
|
|
spr_dat_o[`IMMUCFGR_CRI_BITS] = `IMMUCFGR_CRI;
|
| 137 |
|
|
spr_dat_o[`IMMUCFGR_PRI_BITS] = `IMMUCFGR_PRI;
|
| 138 |
|
|
spr_dat_o[`IMMUCFGR_TEIRI_BITS] = `IMMUCFGR_TEIRI;
|
| 139 |
|
|
spr_dat_o[`IMMUCFGR_HTR_BITS] = `IMMUCFGR_HTR;
|
| 140 |
|
|
spr_dat_o[`IMMUCFGR_RES1_BITS] = `IMMUCFGR_RES1;
|
| 141 |
|
|
end
|
| 142 |
|
|
`SPRGRP_SYS_DCCFGR: begin
|
| 143 |
|
|
spr_dat_o[`DCCFGR_NCW_BITS] = `DCCFGR_NCW;
|
| 144 |
|
|
spr_dat_o[`DCCFGR_NCS_BITS] = `DCCFGR_NCS;
|
| 145 |
|
|
spr_dat_o[`DCCFGR_CBS_BITS] = `DCCFGR_CBS;
|
| 146 |
|
|
spr_dat_o[`DCCFGR_CWS_BITS] = `DCCFGR_CWS;
|
| 147 |
|
|
spr_dat_o[`DCCFGR_CCRI_BITS] = `DCCFGR_CCRI;
|
| 148 |
|
|
spr_dat_o[`DCCFGR_CBIRI_BITS] = `DCCFGR_CBIRI;
|
| 149 |
|
|
spr_dat_o[`DCCFGR_CBPRI_BITS] = `DCCFGR_CBPRI;
|
| 150 |
|
|
spr_dat_o[`DCCFGR_CBLRI_BITS] = `DCCFGR_CBLRI;
|
| 151 |
|
|
spr_dat_o[`DCCFGR_CBFRI_BITS] = `DCCFGR_CBFRI;
|
| 152 |
|
|
spr_dat_o[`DCCFGR_CBWBRI_BITS] = `DCCFGR_CBWBRI;
|
| 153 |
|
|
spr_dat_o[`DCCFGR_RES1_BITS] = `DCCFGR_RES1;
|
| 154 |
|
|
end
|
| 155 |
|
|
`SPRGRP_SYS_ICCFGR: begin
|
| 156 |
|
|
spr_dat_o[`ICCFGR_NCW_BITS] = `ICCFGR_NCW;
|
| 157 |
|
|
spr_dat_o[`ICCFGR_NCS_BITS] = `ICCFGR_NCS;
|
| 158 |
|
|
spr_dat_o[`ICCFGR_CBS_BITS] = `ICCFGR_CBS;
|
| 159 |
|
|
spr_dat_o[`ICCFGR_CWS_BITS] = `ICCFGR_CWS;
|
| 160 |
|
|
spr_dat_o[`ICCFGR_CCRI_BITS] = `ICCFGR_CCRI;
|
| 161 |
|
|
spr_dat_o[`ICCFGR_CBIRI_BITS] = `ICCFGR_CBIRI;
|
| 162 |
|
|
spr_dat_o[`ICCFGR_CBPRI_BITS] = `ICCFGR_CBPRI;
|
| 163 |
|
|
spr_dat_o[`ICCFGR_CBLRI_BITS] = `ICCFGR_CBLRI;
|
| 164 |
|
|
spr_dat_o[`ICCFGR_CBFRI_BITS] = `ICCFGR_CBFRI;
|
| 165 |
|
|
spr_dat_o[`ICCFGR_CBWBRI_BITS] = `ICCFGR_CBWBRI;
|
| 166 |
|
|
spr_dat_o[`ICCFGR_RES1_BITS] = `ICCFGR_RES1;
|
| 167 |
|
|
end
|
| 168 |
|
|
`SPRGRP_SYS_DCFGR: begin
|
| 169 |
|
|
spr_dat_o[`DCFGR_NDP_BITS] = `DCFGR_NDP;
|
| 170 |
|
|
spr_dat_o[`DCFGR_WPCI_BITS] = `DCFGR_WPCI;
|
| 171 |
|
|
spr_dat_o[`DCFGR_RES1_BITS] = `DCFGR_RES1;
|
| 172 |
|
|
end
|
| 173 |
|
|
default: spr_dat_o = 32'h0000_0000;
|
| 174 |
|
|
endcase
|
| 175 |
|
|
`ifdef SYS_FULL_DECODE
|
| 176 |
|
|
else
|
| 177 |
|
|
spr_dat_o = 32'h0000_0000;
|
| 178 |
|
|
`endif
|
| 179 |
|
|
|
| 180 |
|
|
`else
|
| 181 |
|
|
|
| 182 |
|
|
//
|
| 183 |
|
|
// When configuration registers are not implemented, only
|
| 184 |
|
|
// implement VR and UPR
|
| 185 |
|
|
//
|
| 186 |
|
|
always @(spr_addr)
|
| 187 |
|
|
`ifdef SYS_FULL_DECODE
|
| 188 |
|
|
if (!spr_addr[31:4])
|
| 189 |
|
|
`endif
|
| 190 |
|
|
case(spr_addr[3:0])
|
| 191 |
|
|
`SPRGRP_SYS_VR: begin
|
| 192 |
|
|
spr_dat_o[`VR_REV_BITS] = `VR_REV;
|
| 193 |
|
|
spr_dat_o[`VR_RES1_BITS] = `VR_RES1;
|
| 194 |
|
|
spr_dat_o[`VR_CFG_BITS] = `VR_CFG;
|
| 195 |
|
|
spr_dat_o[`VR_VER_BITS] = `VR_VER;
|
| 196 |
|
|
end
|
| 197 |
|
|
`SPRGRP_SYS_UPR: begin
|
| 198 |
|
|
spr_dat_o[`UPR_UP_BITS] = `UPR_UP;
|
| 199 |
|
|
spr_dat_o[`UPR_DCP_BITS] = `UPR_DCP;
|
| 200 |
|
|
spr_dat_o[`UPR_ICP_BITS] = `UPR_ICP;
|
| 201 |
|
|
spr_dat_o[`UPR_DMP_BITS] = `UPR_DMP;
|
| 202 |
|
|
spr_dat_o[`UPR_IMP_BITS] = `UPR_IMP;
|
| 203 |
|
|
spr_dat_o[`UPR_MP_BITS] = `UPR_MP;
|
| 204 |
|
|
spr_dat_o[`UPR_DUP_BITS] = `UPR_DUP;
|
| 205 |
|
|
spr_dat_o[`UPR_PCUP_BITS] = `UPR_PCUP;
|
| 206 |
|
|
spr_dat_o[`UPR_PMP_BITS] = `UPR_PMP;
|
| 207 |
|
|
spr_dat_o[`UPR_PICP_BITS] = `UPR_PICP;
|
| 208 |
|
|
spr_dat_o[`UPR_TTP_BITS] = `UPR_TTP;
|
| 209 |
|
|
spr_dat_o[`UPR_RES1_BITS] = `UPR_RES1;
|
| 210 |
|
|
spr_dat_o[`UPR_CUP_BITS] = `UPR_CUP;
|
| 211 |
|
|
end
|
| 212 |
|
|
default: spr_dat_o = 32'h0000_0000;
|
| 213 |
|
|
endcase
|
| 214 |
|
|
`ifdef SYS_FULL_DECODE
|
| 215 |
|
|
else
|
| 216 |
|
|
spr_dat_o = 32'h0000_0000;
|
| 217 |
|
|
`endif
|
| 218 |
|
|
|
| 219 |
|
|
`endif
|
| 220 |
|
|
|
| 221 |
|
|
endmodule
|
