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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's definitions                                        ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Parameters of the OR1200 core                               ////
////                                                              ////
////  To Do:                                                      ////
////   - add parameters that are missing                          ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.3  2001/08/17 08:01:19  lampret
// IC enable/disable.
//
// Revision 1.2  2001/08/13 03:36:20  lampret
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/22 03:31:54  lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
`define XILINX_RAMB4
//`define XILINX_RAM32X1D
//`define ARTISAN_SSP
//`define ARTISAN_SDP
//`define ARTISAN_STP
 
// Dump VCD
`define VCD_DUMP
 
// Verbose
//`define OR1200_VERBOSE
 
//
// Data cache not implemented
//
`define OR1200_NO_DC
 
//
// Insn cache not implemented
//
`define OR1200_NO_IC
 
//
// Data MMU not implemented
//
`define OR1200_NO_DMMU
 
//
// Insn MMU not implemented
//
`define OR1200_NO_IMMU
 
//
// Register OR1200 outputs
//
//`define OR1200_REGISTERED_OUTPUTS
 
//
// Implement rotate in the ALU
//
`define IMPL_ALU_ROTATE
 
//
// Which type of compare to implement
//
//`define IMPL_ALU_COMP1
`define IMPL_ALU_COMP2
 
//
// Simulate l.div and l.divu
//
`define SIM_ALU_DIV
`define SIM_ALU_DIVU
 
`define ALUOP_NOP       4'd0
 
/* Order defined by arith insns that have two source operands both in regs
   (see binutils/include/opcode/or32.h) */
`define ALUOP_ADD       4'd0
`define ALUOP_ADDC      4'd1
`define ALUOP_SUB       4'd2
`define ALUOP_AND       4'd3
`define ALUOP_OR        4'd4
`define ALUOP_XOR       4'd5
`define ALUOP_MUL       4'd6
`define ALUOP_MAC       4'd7
`define ALUOP_SHROT     4'd8
`define ALUOP_DIV       4'd9
`define ALUOP_DIVU      4'd10
 
/* Order not specifically defined. */
`define ALUOP_IMM       4'd11
`define ALUOP_MOVHI     4'd12
`define ALUOP_COMP      4'd13
`define ALUOP_MTSR      4'd14
`define ALUOP_MFSR      4'd15
 
`define ALUOP_WIDTH     4
 
/* Shift/rotate macros. */
`define SHROTOP_NOP     2'd0
`define SHROTOP_SLL     2'd0
`define SHROTOP_SRL     2'd1
`define SHROTOP_SRA     2'd2
`define SHROTOP_ROR     2'd3
 
`define SHROTOP_WIDTH   2
 
 
// 3 for 8 bytes, 4 for 16 bytes etc
`define IC_LINESIZE             4
 
// Insn cache specific
`define ICSIZE                  13              // 8192
`define ICINDX                  `ICSIZE-2       // 11
`define ICINDXH                 `ICSIZE-1       // 12
`define ICTAGL                  `ICINDXH+1      // 13
 
`define OPERAND_WIDTH           32
`define REGFILE_ADDR_WIDTH      5
`define off     1'b0
`define on      1'b1
 
// Use fast (and bigger) version of mem2reg aligner
`define MEM2REG_FAST
 
// SHROT_OP position in machine word
`define SHROTOP_POS             7:6
 
// ALU instructions multicycle field in machine word
`define ALUMCYC_POS             9:8
 
// Execution cycles per instruction
`define MULTICYCLE_WIDTH        2
`define ONE_CYCLE               2'd0
`define TWO_CYCLES              2'd1
 
// Operand MUX selects
`define SEL_WIDTH               2
`define SEL_RF                  2'd0
`define SEL_IMM                 2'd1
`define SEL_EX_FORW             2'd2
`define SEL_WB_FORW             2'd3
 
// Branch ops
`define BRANCHOP_WIDTH          3
`define BRANCHOP_NOP            3'd0
`define BRANCHOP_J              3'd1
`define BRANCHOP_JR             3'd2
`define BRANCHOP_BAL            3'd3
`define BRANCHOP_BF             3'd4
`define BRANCHOP_BNF            3'd5
`define BRANCHOP_RFE            3'd6
 
// Bit 0: sign extend
// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword
// Bit 3: 0 load, 1 store
`define LSUOP_WIDTH             4
`define LSUOP_NOP               4'b0000
`define LSUOP_LBZ               4'b0010
`define LSUOP_LBS               4'b0011
`define LSUOP_LHZ               4'b0100
`define LSUOP_LHS               4'b0101
`define LSUOP_LWZ               4'b0110
`define LSUOP_LWS               4'b0111
`define LSUOP_LD                4'b0001
`define LSUOP_SD                4'b1000
`define LSUOP_SB                4'b1010
`define LSUOP_SH                4'b1100
`define LSUOP_SW                4'b1110
 
// Fetch ops
`define FETCHOP_WIDTH           1
`define FETCHOP_NOP             1'b0
`define FETCHOP_LW              1'b1
 
// Bit 0: register file write enable
// Bits 2-1: write-back mux selects
`define RFWBOP_WIDTH            3
`define RFWBOP_NOP              3'b000
`define RFWBOP_ALU              3'b001
`define RFWBOP_LSU              3'b011
`define RFWBOP_SPRS             3'b101
`define RFWBOP_LR               3'b111
 
// Compare instructions
`define COP_SFEQ       3'b000
`define COP_SFNE       3'b001
`define COP_SFGT       3'b010
`define COP_SFGE       3'b011
`define COP_SFLT       3'b100
`define COP_SFLE       3'b101
`define COP_X          3'b0111
`define SIGNED_COMPARE 'd3
`define COMPOP_WIDTH    4
 
`define PAGEINDX_WIDTH          13
`define ITLBADDR_WIDTH          7
 
// Exceptions
`define EXCEPT_WIDTH 4
 
`define EXCEPT_UNUSED           `EXCEPT_WIDTH'hf
`define EXCEPT_TRAP             `EXCEPT_WIDTH'he
`define EXCEPT_BREAK            `EXCEPT_WIDTH'hd
`define EXCEPT_SYSCALL          `EXCEPT_WIDTH'hc
`define EXCEPT_RANGE            `EXCEPT_WIDTH'hb
`define EXCEPT_ITLBMISS         `EXCEPT_WIDTH'ha
`define EXCEPT_DTLBMISS         `EXCEPT_WIDTH'h9
`define EXCEPT_HPINT            `EXCEPT_WIDTH'h8
`define EXCEPT_ILLEGAL          `EXCEPT_WIDTH'h7
`define EXCEPT_ALIGN            `EXCEPT_WIDTH'h6
`define EXCEPT_LPINT            `EXCEPT_WIDTH'h5
`define EXCEPT_IPF              `EXCEPT_WIDTH'h4
`define EXCEPT_DPF              `EXCEPT_WIDTH'h3
`define EXCEPT_BUSERR           `EXCEPT_WIDTH'h2
`define EXCEPT_RESET            `EXCEPT_WIDTH'h1
`define EXCEPT_NONE             `EXCEPT_WIDTH'h0
 
`define SR_WIDTH 9
// SR bits (no CID)
`define SR_SUPV 0
`define SR_EXR  1
`define SR_EIR  2
`define SR_DCE  3
`define SR_ICE  4
`define SR_DME  5
`define SR_IME  6
`define SR_LEE  7
`define SR_CF   8
 
// Access types
`define ACCESS_WIDTH            2
`define ACCESS_USER_READ        2'b00
`define ACCESS_USER_WRITE       2'b01
`define ACCESS_SUPV_READ        2'b10
`define ACCESS_SUPV_WRITE       2'b11
 
// SPRS
// SIMON
//`define SPR_GROUP_BITS        31:27
`define SPR_GROUP_BITS  15:11
`define SPR_GROUP_WIDTH 5
`define SPR_GROUP_SYS   5'd00
`define SPR_GROUP_IMMU  5'd01
`define SPR_GROUP_DMMU  5'd02
`define SPR_GROUP_DC    5'd03
`define SPR_GROUP_IC    5'd04
`define SPR_GROUP_DU    5'd06
`define SPR_GROUP_PM    5'd08
`define SPR_GROUP_PIC   5'd09
`define SPR_GROUP_TT    5'd10
`define SPR_GROUP_MODA  5'd29
`define SPR_GROUP_MODD  5'd30
 
`define SPR_CFGR        7'd0
`define SPR_RF          6'd32   // 1024 >> 5
`define SPR_PC          11'd16
`define SPR_SR          11'd17
`define SPR_EPCR        11'd32
`define SPR_EEAR        11'd48
`define SPR_ESR         11'd64
 
 
// Bits that define the group
`define SPRGRP_BITS 15:11
 
// Bits that define offset inside the group
`define SPROFS_BITS 10:0
 
//
// Power Management
//
 
// Define it if you want PM implemented
`define PM_IMPLEMENTED
 
// Bit positions inside PMR (don't change)
`define PM_PMR_SDF 3:0
`define PM_PMR_DME 4
`define PM_PMR_SME 5
`define PM_PMR_DCGE 6
`define PM_PMR_UNUSED 31:7
 
// PMR offset inside PM group of registers
`define PM_OFS_PMR 11'b0
 
// PM group
`define SPRGRP_PM 5'd8
 
// Define if PMR can be read/written at any address inside PM group
`define PM_PARTIAL_DECODING
 
// Define if reading PMR is allowed
`define PM_READREGS
 
// Define if unused PMR bits should be zero
`define PM_UNUSED_ZERO
 
//
// Debug Unit
//
 
// Define it if you want DU implemented
`define DU_IMPLEMENTED
 
// Address offsets of DU registers inside DU group
`define DU_OFS_DMR1 5'd16
`define DU_OFS_DMR2 5'd17
`define DU_OFS_DSR 5'd20
`define DU_OFS_DRR 5'd21
 
// Position of offset bits inside SPR address
`define DUOFS_BITS 4:0
 
// Define if you want these DU registers to be implemented
`define DU_DMR1
`define DU_DMR2
`define DU_DSR
`define DU_DRR
 
// SIMON
`define DU_DMR1_ST 22
 
// Define if reading DU regs is allowed
`define DU_READREGS
 
// Define if unused DU registers bits should be zero
`define DU_UNUSED_ZERO
 
// DU operation commands
`define DU_OP_READSPR 3'd4
`define DU_OP_WRITESPR 3'd5
 
//
// Programmable Interrupt Controller
//
 
// Define it if you want PIC implemented
`define PIC_IMPLEMENTED
 
// Define number of interrupt inputs (2-31)
`define PIC_INTS 20
 
// Address offsets of PIC registers inside PIC group
`define PIC_OFS_PICMR 2'd0
`define PIC_OFS_PICPR 2'd1
`define PIC_OFS_PICSR 2'd2
 
// Position of offset bits inside SPR address
`define PICOFS_BITS 1:0
 
// Define if you want these PIC registers to be implemented
`define PIC_PICMR
`define PIC_PICPR
`define PIC_PICSR
 
// Define if reading PIC registers is allowed
`define PIC_READREGS
 
// Define if unused PIC register bits should be zero
`define PIC_UNUSED_ZERO
 
//
// Tick Timer
//
 
// Define it if you want TT implemented
`define TT_IMPLEMENTED
 
// Address offsets of TT registers inside TT group
`define TT_OFS_TTMR 1'd0
`define TT_OFS_TTCR 1'd1
 
// Position of offset bits inside SPR group
`define TTOFS_BITS 0
 
// Define if you want these TT registers to be implemented
`define TT_TTMR
`define TT_TTCR
 
// TTMR bits
`define TT_TTMR_TP 27:0
`define TT_TTMR_IP 28
`define TT_TTMR_IE 29
`define TT_TTMR_M 31:30
 
// Define if reading TT registers is allowed
`define TT_READREGS
 
 
//
// VR, UPR and Configuration Registers
//
 
// Define if you want configuration registers implemented
`define CFGR_IMPLEMENTED
 
// Define if you want full address decode inside SYS group
`define SYS_FULL_DECODE
 
// Offsets of VR, UPR and CFGR registers
`define SPRGRP_SYS_VR           4'h0
`define SPRGRP_SYS_UPR          4'h1
`define SPRGRP_SYS_CPUCFGR      4'h2
`define SPRGRP_SYS_DMMUCFGR     4'h3
`define SPRGRP_SYS_IMMUCFGR     4'h4
`define SPRGRP_SYS_DCCFGR       4'h5
`define SPRGRP_SYS_ICCFGR       4'h6
`define SPRGRP_SYS_DCFGR        4'h7
 
// VR fields
`define VR_REV_BITS             5:0
`define VR_RES1_BITS            15:6
`define VR_CFG_BITS             23:16
`define VR_VER_BITS             31:24
 
// VR values
`define VR_REV                  6'h00
`define VR_RES1                 10'h000
`define VR_CFG                  8'h00
`define VR_VER                  8'h12
 
// UPR fields
`define UPR_UP_BITS             0
`define UPR_DCP_BITS            1
`define UPR_ICP_BITS            2
`define UPR_DMP_BITS            3
`define UPR_IMP_BITS            4
`define UPR_MP_BITS             5
`define UPR_DUP_BITS            6
`define UPR_PCUP_BITS           7
`define UPR_PMP_BITS            8
`define UPR_PICP_BITS           9
`define UPR_TTP_BITS            10
`define UPR_RES1_BITS           23:11
`define UPR_CUP_BITS            31:24
 
// UPR values
`define UPR_UP                  1'b1
`define UPR_DCP                 1'b1
`define UPR_ICP                 1'b1
`define UPR_DMP                 1'b1
`define UPR_IMP                 1'b1
`define UPR_MP                  1'b1
`define UPR_DUP                 1'b1
`define UPR_PCUP                1'b0
`define UPR_PMP                 1'b1
`define UPR_PICP                1'b1
`define UPR_TTP                 1'b1
`define UPR_RES1                13'h0000
`define UPR_CUP                 8'h00
 
// CPUCFGR fields
`define CPUCFGR_NSGF_BITS       3:0
`define CPUCFGR_HGF_BITS        4
`define CPUCFGR_OB32S_BITS      5
`define CPUCFGR_OB64S_BITS      6
`define CPUCFGR_OF32S_BITS      7
`define CPUCFGR_OF64S_BITS      8
`define CPUCFGR_OV64S_BITS      9
`define CPUCFGR_RES1_BITS       31:10
 
// CPUCFGR values
`define CPUCFGR_NSGF            4'h0
`define CPUCFGR_HGF             1'b0
`define CPUCFGR_OB32S           1'b1
`define CPUCFGR_OB64S           1'b0
`define CPUCFGR_OF32S           1'b0
`define CPUCFGR_OF64S           1'b0
`define CPUCFGR_OV64S           1'b0
`define CPUCFGR_RES1            22'h000000
 
// DMMUCFGR fields
`define DMMUCFGR_NTW_BITS       1:0
`define DMMUCFGR_NTS_BITS       4:2
`define DMMUCFGR_NAE_BITS       7:5
`define DMMUCFGR_CRI_BITS       8
`define DMMUCFGR_PRI_BITS       9
`define DMMUCFGR_TEIRI_BITS     10
`define DMMUCFGR_HTR_BITS       11
`define DMMUCFGR_RES1_BITS      31:12
 
// DMMUCFGR values
`define DMMUCFGR_NTW            2'h0
`define DMMUCFGR_NTS            3'h5
`define DMMUCFGR_NAE            3'h0
`define DMMUCFGR_CRI            1'b0
`define DMMUCFGR_PRI            1'b0
`define DMMUCFGR_TEIRI          1'b1
`define DMMUCFGR_HTR            1'b0
`define DMMUCFGR_RES1           20'h00000
 
// IMMUCFGR fields
`define IMMUCFGR_NTW_BITS       1:0
`define IMMUCFGR_NTS_BITS       4:2
`define IMMUCFGR_NAE_BITS       7:5
`define IMMUCFGR_CRI_BITS       8
`define IMMUCFGR_PRI_BITS       9
`define IMMUCFGR_TEIRI_BITS     10
`define IMMUCFGR_HTR_BITS       11
`define IMMUCFGR_RES1_BITS      31:12
 
// IMMUCFGR values
`define IMMUCFGR_NTW            2'h0
`define IMMUCFGR_NTS            3'h5
`define IMMUCFGR_NAE            3'h0
`define IMMUCFGR_CRI            1'b0
`define IMMUCFGR_PRI            1'b0
`define IMMUCFGR_TEIRI          1'b1
`define IMMUCFGR_HTR            1'b0
`define IMMUCFGR_RES1           20'h00000
 
// DCCFGR fields
`define DCCFGR_NCW_BITS         2:0
`define DCCFGR_NCS_BITS         6:3
`define DCCFGR_CBS_BITS         7
`define DCCFGR_CWS_BITS         8
`define DCCFGR_CCRI_BITS        9
`define DCCFGR_CBIRI_BITS       10
`define DCCFGR_CBPRI_BITS       11
`define DCCFGR_CBLRI_BITS       12
`define DCCFGR_CBFRI_BITS       13
`define DCCFGR_CBWBRI_BITS      14
`define DCCFGR_RES1_BITS        31:15
 
// DCCFGR values
`define DCCFGR_NCW              3'h0
`define DCCFGR_NCS              4'h5
`define DCCFGR_CBS              1'b0
`define DCCFGR_CWS              1'b0
`define DCCFGR_CCRI             1'b1
`define DCCFGR_CBIRI            1'b1
`define DCCFGR_CBPRI            1'b0
`define DCCFGR_CBLRI            1'b0
`define DCCFGR_CBFRI            1'b0
`define DCCFGR_CBWBRI           1'b1
`define DCCFGR_RES1             17'h00000
 
// ICCFGR fields
`define ICCFGR_NCW_BITS         2:0
`define ICCFGR_NCS_BITS         6:3
`define ICCFGR_CBS_BITS         7
`define ICCFGR_CWS_BITS         8
`define ICCFGR_CCRI_BITS        9
`define ICCFGR_CBIRI_BITS       10
`define ICCFGR_CBPRI_BITS       11
`define ICCFGR_CBLRI_BITS       12
`define ICCFGR_CBFRI_BITS       13
`define ICCFGR_CBWBRI_BITS      14
`define ICCFGR_RES1_BITS        31:15
 
// ICCFGR values
`define ICCFGR_NCW              3'h0
`define ICCFGR_NCS              4'h5
`define ICCFGR_CBS              1'b0
`define ICCFGR_CWS              1'b0
`define ICCFGR_CCRI             1'b1
`define ICCFGR_CBIRI            1'b1
`define ICCFGR_CBPRI            1'b0
`define ICCFGR_CBLRI            1'b0
`define ICCFGR_CBFRI            1'b0
`define ICCFGR_CBWBRI           1'b1
`define ICCFGR_RES1             17'h00000
 
// DCFGR fields
`define DCFGR_NDP_BITS          2:0
`define DCFGR_WPCI_BITS         3
`define DCFGR_RES1_BITS         31:4
 
// DCFGR values
`define DCFGR_NDP               3'h0
`define DCFGR_WPCI              1'b0
`define DCFGR_RES1              28'h0000000
 
 
// Instruction opcode groups (basic)
`define OR32_J                 6'b000000
`define OR32_JAL               6'b000001
`define OR32_BNF               6'b000011
`define OR32_BF                6'b000100
`define OR32_NOP               6'b000101
`define OR32_MOVHI             6'b000110
`define OR32_MFSPR             6'b000111
`define OR32_XSYNC             6'b001000
`define OR32_RFE               6'b001001
 
`define OR32_MTSPR             6'b010000
`define OR32_JR                6'b010001
`define OR32_JALR              6'b010010
 
`define OR32_LWZ               6'b100001
`define OR32_LBZ               6'b100011
`define OR32_LBS               6'b100100
`define OR32_LHZ               6'b100101
`define OR32_LHS               6'b100110
`define OR32_ADDI              6'b100111
`define OR32_ADDIC             6'b101000
`define OR32_ANDI              6'b101001
`define OR32_ORI               6'b101010
`define OR32_XORI              6'b101011
`define OR32_MULI              6'b101100
`define OR32_MACI              6'b101101
`define OR32_SH_ROTI           6'b101110
`define OR32_SFXXI             6'b101111
 
`define OR32_SW                6'b110101
`define OR32_SB                6'b110110
`define OR32_SH                6'b110111
`define OR32_ALU               6'b111000
`define OR32_SFXX              6'b111001
 

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[/] [or1k/] [branches/] [mp3_stable/] [mp3/] [rtl/] [verilog/] [or1200.xcv/] [defines.v] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	266	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's definitions ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Parameters of the OR1200 core ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - add parameters that are missing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
48			`// no message`
49			`//`
50			`// Revision 1.3 2001/08/17 08:01:19 lampret`
51			`// IC enable/disable.`
52			`//`
53			`// Revision 1.2 2001/08/13 03:36:20 lampret`
54			`// Added cfg regs. Moved all defines into one defines.v file. More cleanup.`
55			`//`
56			`// Revision 1.1 2001/08/09 13:39:33 lampret`
57			`// Major clean-up.`
58			`//`
59			`// Revision 1.2 2001/07/22 03:31:54 lampret`
60			`// Fixed RAM's oen bug. Cache bypass under development.`
61			`//`
62			`// Revision 1.1 2001/07/20 00:46:03 lampret`
63			`// Development version of RTL. Libraries are missing.`
64			`//`
65			`//`
66
67			`define XILINX_RAMB4
68			//`define XILINX_RAM32X1D
69			//`define ARTISAN_SSP
70			//`define ARTISAN_SDP
71			//`define ARTISAN_STP
72
73			`// Dump VCD`
74			`define VCD_DUMP
75
76			`// Verbose`
77			//`define OR1200_VERBOSE
78
79			`//`
80			`// Data cache not implemented`
81			`//`
82			`define OR1200_NO_DC
83
84			`//`
85			`// Insn cache not implemented`
86			`//`
87			`define OR1200_NO_IC
88
89			`//`
90			`// Data MMU not implemented`
91			`//`
92			`define OR1200_NO_DMMU
93
94			`//`
95			`// Insn MMU not implemented`
96			`//`
97			`define OR1200_NO_IMMU
98
99			`//`
100			`// Register OR1200 outputs`
101			`//`
102			//`define OR1200_REGISTERED_OUTPUTS
103
104			`//`
105			`// Implement rotate in the ALU`
106			`//`
107			`define IMPL_ALU_ROTATE
108
109			`//`
110			`// Which type of compare to implement`
111			`//`
112			//`define IMPL_ALU_COMP1
113			`define IMPL_ALU_COMP2
114
115			`//`
116			`// Simulate l.div and l.divu`
117			`//`
118			`define SIM_ALU_DIV
119			`define SIM_ALU_DIVU
120
121			`define ALUOP_NOP 4'd0
122
123			`/* Order defined by arith insns that have two source operands both in regs`
124			`(see binutils/include/opcode/or32.h) */`
125			`define ALUOP_ADD 4'd0
126			`define ALUOP_ADDC 4'd1
127			`define ALUOP_SUB 4'd2
128			`define ALUOP_AND 4'd3
129			`define ALUOP_OR 4'd4
130			`define ALUOP_XOR 4'd5
131			`define ALUOP_MUL 4'd6
132			`define ALUOP_MAC 4'd7
133			`define ALUOP_SHROT 4'd8
134			`define ALUOP_DIV 4'd9
135			`define ALUOP_DIVU 4'd10
136
137			`/* Order not specifically defined. */`
138			`define ALUOP_IMM 4'd11
139			`define ALUOP_MOVHI 4'd12
140			`define ALUOP_COMP 4'd13
141			`define ALUOP_MTSR 4'd14
142			`define ALUOP_MFSR 4'd15
143
144			`define ALUOP_WIDTH 4
145
146			`/* Shift/rotate macros. */`
147			`define SHROTOP_NOP 2'd0
148			`define SHROTOP_SLL 2'd0
149			`define SHROTOP_SRL 2'd1
150			`define SHROTOP_SRA 2'd2
151			`define SHROTOP_ROR 2'd3
152
153			`define SHROTOP_WIDTH 2
154
155
156			`// 3 for 8 bytes, 4 for 16 bytes etc`
157			`define IC_LINESIZE 4
158
159			`// Insn cache specific`
160			`define ICSIZE 13 // 8192
161			`define ICINDX `ICSIZE-2 // 11
162			`define ICINDXH `ICSIZE-1 // 12
163			`define ICTAGL `ICINDXH+1 // 13
164
165			`define OPERAND_WIDTH 32
166			`define REGFILE_ADDR_WIDTH 5
167			`define off 1'b0
168			`define on 1'b1
169
170			`// Use fast (and bigger) version of mem2reg aligner`
171			`define MEM2REG_FAST
172
173			`// SHROT_OP position in machine word`
174			`define SHROTOP_POS 7:6
175
176			`// ALU instructions multicycle field in machine word`
177			`define ALUMCYC_POS 9:8
178
179			`// Execution cycles per instruction`
180			`define MULTICYCLE_WIDTH 2
181			`define ONE_CYCLE 2'd0
182			`define TWO_CYCLES 2'd1
183
184			`// Operand MUX selects`
185			`define SEL_WIDTH 2
186			`define SEL_RF 2'd0
187			`define SEL_IMM 2'd1
188			`define SEL_EX_FORW 2'd2
189			`define SEL_WB_FORW 2'd3
190
191			`// Branch ops`
192			`define BRANCHOP_WIDTH 3
193			`define BRANCHOP_NOP 3'd0
194			`define BRANCHOP_J 3'd1
195			`define BRANCHOP_JR 3'd2
196			`define BRANCHOP_BAL 3'd3
197			`define BRANCHOP_BF 3'd4
198			`define BRANCHOP_BNF 3'd5
199			`define BRANCHOP_RFE 3'd6
200
201			`// Bit 0: sign extend`
202			`// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword`
203			`// Bit 3: 0 load, 1 store`
204			`define LSUOP_WIDTH 4
205			`define LSUOP_NOP 4'b0000
206			`define LSUOP_LBZ 4'b0010
207			`define LSUOP_LBS 4'b0011
208			`define LSUOP_LHZ 4'b0100
209			`define LSUOP_LHS 4'b0101
210			`define LSUOP_LWZ 4'b0110
211			`define LSUOP_LWS 4'b0111
212			`define LSUOP_LD 4'b0001
213			`define LSUOP_SD 4'b1000
214			`define LSUOP_SB 4'b1010
215			`define LSUOP_SH 4'b1100
216			`define LSUOP_SW 4'b1110
217
218			`// Fetch ops`
219			`define FETCHOP_WIDTH 1
220			`define FETCHOP_NOP 1'b0
221			`define FETCHOP_LW 1'b1
222
223			`// Bit 0: register file write enable`
224			`// Bits 2-1: write-back mux selects`
225			`define RFWBOP_WIDTH 3
226			`define RFWBOP_NOP 3'b000
227			`define RFWBOP_ALU 3'b001
228			`define RFWBOP_LSU 3'b011
229			`define RFWBOP_SPRS 3'b101
230			`define RFWBOP_LR 3'b111
231
232			`// Compare instructions`
233			`define COP_SFEQ 3'b000
234			`define COP_SFNE 3'b001
235			`define COP_SFGT 3'b010
236			`define COP_SFGE 3'b011
237			`define COP_SFLT 3'b100
238			`define COP_SFLE 3'b101
239			`define COP_X 3'b0111
240			`define SIGNED_COMPARE 'd3
241			`define COMPOP_WIDTH 4
242
243			`define PAGEINDX_WIDTH 13
244			`define ITLBADDR_WIDTH 7
245
246			`// Exceptions`
247			`define EXCEPT_WIDTH 4
248
249			`define EXCEPT_UNUSED `EXCEPT_WIDTH'hf
250			`define EXCEPT_TRAP `EXCEPT_WIDTH'he
251			`define EXCEPT_BREAK `EXCEPT_WIDTH'hd
252			`define EXCEPT_SYSCALL `EXCEPT_WIDTH'hc
253			`define EXCEPT_RANGE `EXCEPT_WIDTH'hb
254			`define EXCEPT_ITLBMISS `EXCEPT_WIDTH'ha
255			`define EXCEPT_DTLBMISS `EXCEPT_WIDTH'h9
256			`define EXCEPT_HPINT `EXCEPT_WIDTH'h8
257			`define EXCEPT_ILLEGAL `EXCEPT_WIDTH'h7
258			`define EXCEPT_ALIGN `EXCEPT_WIDTH'h6
259			`define EXCEPT_LPINT `EXCEPT_WIDTH'h5
260			`define EXCEPT_IPF `EXCEPT_WIDTH'h4
261			`define EXCEPT_DPF `EXCEPT_WIDTH'h3
262			`define EXCEPT_BUSERR `EXCEPT_WIDTH'h2
263			`define EXCEPT_RESET `EXCEPT_WIDTH'h1
264			`define EXCEPT_NONE `EXCEPT_WIDTH'h0
265
266			`define SR_WIDTH 9
267			`// SR bits (no CID)`
268			`define SR_SUPV 0
269			`define SR_EXR 1
270			`define SR_EIR 2
271			`define SR_DCE 3
272			`define SR_ICE 4
273			`define SR_DME 5
274			`define SR_IME 6
275			`define SR_LEE 7
276			`define SR_CF 8
277
278			`// Access types`
279			`define ACCESS_WIDTH 2
280			`define ACCESS_USER_READ 2'b00
281			`define ACCESS_USER_WRITE 2'b01
282			`define ACCESS_SUPV_READ 2'b10
283			`define ACCESS_SUPV_WRITE 2'b11
284
285			`// SPRS`
286			`// SIMON`
287			//`define SPR_GROUP_BITS 31:27
288			`define SPR_GROUP_BITS 15:11
289			`define SPR_GROUP_WIDTH 5
290			`define SPR_GROUP_SYS 5'd00
291			`define SPR_GROUP_IMMU 5'd01
292			`define SPR_GROUP_DMMU 5'd02
293			`define SPR_GROUP_DC 5'd03
294			`define SPR_GROUP_IC 5'd04
295			`define SPR_GROUP_DU 5'd06
296			`define SPR_GROUP_PM 5'd08
297			`define SPR_GROUP_PIC 5'd09
298			`define SPR_GROUP_TT 5'd10
299			`define SPR_GROUP_MODA 5'd29
300			`define SPR_GROUP_MODD 5'd30
301
302			`define SPR_CFGR 7'd0
303			`define SPR_RF 6'd32 // 1024 >> 5
304			`define SPR_PC 11'd16
305			`define SPR_SR 11'd17
306			`define SPR_EPCR 11'd32
307			`define SPR_EEAR 11'd48
308			`define SPR_ESR 11'd64
309
310
311			`// Bits that define the group`
312			`define SPRGRP_BITS 15:11
313
314			`// Bits that define offset inside the group`
315			`define SPROFS_BITS 10:0
316
317			`//`
318			`// Power Management`
319			`//`
320
321			`// Define it if you want PM implemented`
322			`define PM_IMPLEMENTED
323
324			`// Bit positions inside PMR (don't change)`
325			`define PM_PMR_SDF 3:0
326			`define PM_PMR_DME 4
327			`define PM_PMR_SME 5
328			`define PM_PMR_DCGE 6
329			`define PM_PMR_UNUSED 31:7
330
331			`// PMR offset inside PM group of registers`
332			`define PM_OFS_PMR 11'b0
333
334			`// PM group`
335			`define SPRGRP_PM 5'd8
336
337			`// Define if PMR can be read/written at any address inside PM group`
338			`define PM_PARTIAL_DECODING
339
340			`// Define if reading PMR is allowed`
341			`define PM_READREGS
342
343			`// Define if unused PMR bits should be zero`
344			`define PM_UNUSED_ZERO
345
346			`//`
347			`// Debug Unit`
348			`//`
349
350			`// Define it if you want DU implemented`
351			`define DU_IMPLEMENTED
352
353			`// Address offsets of DU registers inside DU group`
354			`define DU_OFS_DMR1 5'd16
355			`define DU_OFS_DMR2 5'd17
356			`define DU_OFS_DSR 5'd20
357			`define DU_OFS_DRR 5'd21
358
359			`// Position of offset bits inside SPR address`
360			`define DUOFS_BITS 4:0
361
362			`// Define if you want these DU registers to be implemented`
363			`define DU_DMR1
364			`define DU_DMR2
365			`define DU_DSR
366			`define DU_DRR
367
368			`// SIMON`
369			`define DU_DMR1_ST 22
370
371			`// Define if reading DU regs is allowed`
372			`define DU_READREGS
373
374			`// Define if unused DU registers bits should be zero`
375			`define DU_UNUSED_ZERO
376
377			`// DU operation commands`
378			`define DU_OP_READSPR 3'd4
379			`define DU_OP_WRITESPR 3'd5
380
381			`//`
382			`// Programmable Interrupt Controller`
383			`//`
384
385			`// Define it if you want PIC implemented`
386			`define PIC_IMPLEMENTED
387
388			`// Define number of interrupt inputs (2-31)`
389			`define PIC_INTS 20
390
391			`// Address offsets of PIC registers inside PIC group`
392			`define PIC_OFS_PICMR 2'd0
393			`define PIC_OFS_PICPR 2'd1
394			`define PIC_OFS_PICSR 2'd2
395
396			`// Position of offset bits inside SPR address`
397			`define PICOFS_BITS 1:0
398
399			`// Define if you want these PIC registers to be implemented`
400			`define PIC_PICMR
401			`define PIC_PICPR
402			`define PIC_PICSR
403
404			`// Define if reading PIC registers is allowed`
405			`define PIC_READREGS
406
407			`// Define if unused PIC register bits should be zero`
408			`define PIC_UNUSED_ZERO
409
410			`//`
411			`// Tick Timer`
412			`//`
413
414			`// Define it if you want TT implemented`
415			`define TT_IMPLEMENTED
416
417			`// Address offsets of TT registers inside TT group`
418			`define TT_OFS_TTMR 1'd0
419			`define TT_OFS_TTCR 1'd1
420
421			`// Position of offset bits inside SPR group`
422			`define TTOFS_BITS 0
423
424			`// Define if you want these TT registers to be implemented`
425			`define TT_TTMR
426			`define TT_TTCR
427
428			`// TTMR bits`
429			`define TT_TTMR_TP 27:0
430			`define TT_TTMR_IP 28
431			`define TT_TTMR_IE 29
432			`define TT_TTMR_M 31:30
433
434			`// Define if reading TT registers is allowed`
435			`define TT_READREGS
436
437
438			`//`
439			`// VR, UPR and Configuration Registers`
440			`//`
441
442			`// Define if you want configuration registers implemented`
443			`define CFGR_IMPLEMENTED
444
445			`// Define if you want full address decode inside SYS group`
446			`define SYS_FULL_DECODE
447
448			`// Offsets of VR, UPR and CFGR registers`
449			`define SPRGRP_SYS_VR 4'h0
450			`define SPRGRP_SYS_UPR 4'h1
451			`define SPRGRP_SYS_CPUCFGR 4'h2
452			`define SPRGRP_SYS_DMMUCFGR 4'h3
453			`define SPRGRP_SYS_IMMUCFGR 4'h4
454			`define SPRGRP_SYS_DCCFGR 4'h5
455			`define SPRGRP_SYS_ICCFGR 4'h6
456			`define SPRGRP_SYS_DCFGR 4'h7
457
458			`// VR fields`
459			`define VR_REV_BITS 5:0
460			`define VR_RES1_BITS 15:6
461			`define VR_CFG_BITS 23:16
462			`define VR_VER_BITS 31:24
463
464			`// VR values`
465			`define VR_REV 6'h00
466			`define VR_RES1 10'h000
467			`define VR_CFG 8'h00
468			`define VR_VER 8'h12
469
470			`// UPR fields`
471			`define UPR_UP_BITS 0
472			`define UPR_DCP_BITS 1
473			`define UPR_ICP_BITS 2
474			`define UPR_DMP_BITS 3
475			`define UPR_IMP_BITS 4
476			`define UPR_MP_BITS 5
477			`define UPR_DUP_BITS 6
478			`define UPR_PCUP_BITS 7
479			`define UPR_PMP_BITS 8
480			`define UPR_PICP_BITS 9
481			`define UPR_TTP_BITS 10
482			`define UPR_RES1_BITS 23:11
483			`define UPR_CUP_BITS 31:24
484
485			`// UPR values`
486			`define UPR_UP 1'b1
487			`define UPR_DCP 1'b1
488			`define UPR_ICP 1'b1
489			`define UPR_DMP 1'b1
490			`define UPR_IMP 1'b1
491			`define UPR_MP 1'b1
492			`define UPR_DUP 1'b1
493			`define UPR_PCUP 1'b0
494			`define UPR_PMP 1'b1
495			`define UPR_PICP 1'b1
496			`define UPR_TTP 1'b1
497			`define UPR_RES1 13'h0000
498			`define UPR_CUP 8'h00
499
500			`// CPUCFGR fields`
501			`define CPUCFGR_NSGF_BITS 3:0
502			`define CPUCFGR_HGF_BITS 4
503			`define CPUCFGR_OB32S_BITS 5
504			`define CPUCFGR_OB64S_BITS 6
505			`define CPUCFGR_OF32S_BITS 7
506			`define CPUCFGR_OF64S_BITS 8
507			`define CPUCFGR_OV64S_BITS 9
508			`define CPUCFGR_RES1_BITS 31:10
509
510			`// CPUCFGR values`
511			`define CPUCFGR_NSGF 4'h0
512			`define CPUCFGR_HGF 1'b0
513			`define CPUCFGR_OB32S 1'b1
514			`define CPUCFGR_OB64S 1'b0
515			`define CPUCFGR_OF32S 1'b0
516			`define CPUCFGR_OF64S 1'b0
517			`define CPUCFGR_OV64S 1'b0
518			`define CPUCFGR_RES1 22'h000000
519
520			`// DMMUCFGR fields`
521			`define DMMUCFGR_NTW_BITS 1:0
522			`define DMMUCFGR_NTS_BITS 4:2
523			`define DMMUCFGR_NAE_BITS 7:5
524			`define DMMUCFGR_CRI_BITS 8
525			`define DMMUCFGR_PRI_BITS 9
526			`define DMMUCFGR_TEIRI_BITS 10
527			`define DMMUCFGR_HTR_BITS 11
528			`define DMMUCFGR_RES1_BITS 31:12
529
530			`// DMMUCFGR values`
531			`define DMMUCFGR_NTW 2'h0
532			`define DMMUCFGR_NTS 3'h5
533			`define DMMUCFGR_NAE 3'h0
534			`define DMMUCFGR_CRI 1'b0
535			`define DMMUCFGR_PRI 1'b0
536			`define DMMUCFGR_TEIRI 1'b1
537			`define DMMUCFGR_HTR 1'b0
538			`define DMMUCFGR_RES1 20'h00000
539
540			`// IMMUCFGR fields`
541			`define IMMUCFGR_NTW_BITS 1:0
542			`define IMMUCFGR_NTS_BITS 4:2
543			`define IMMUCFGR_NAE_BITS 7:5
544			`define IMMUCFGR_CRI_BITS 8
545			`define IMMUCFGR_PRI_BITS 9
546			`define IMMUCFGR_TEIRI_BITS 10
547			`define IMMUCFGR_HTR_BITS 11
548			`define IMMUCFGR_RES1_BITS 31:12
549
550			`// IMMUCFGR values`
551			`define IMMUCFGR_NTW 2'h0
552			`define IMMUCFGR_NTS 3'h5
553			`define IMMUCFGR_NAE 3'h0
554			`define IMMUCFGR_CRI 1'b0
555			`define IMMUCFGR_PRI 1'b0
556			`define IMMUCFGR_TEIRI 1'b1
557			`define IMMUCFGR_HTR 1'b0
558			`define IMMUCFGR_RES1 20'h00000
559
560			`// DCCFGR fields`
561			`define DCCFGR_NCW_BITS 2:0
562			`define DCCFGR_NCS_BITS 6:3
563			`define DCCFGR_CBS_BITS 7
564			`define DCCFGR_CWS_BITS 8
565			`define DCCFGR_CCRI_BITS 9
566			`define DCCFGR_CBIRI_BITS 10
567			`define DCCFGR_CBPRI_BITS 11
568			`define DCCFGR_CBLRI_BITS 12
569			`define DCCFGR_CBFRI_BITS 13
570			`define DCCFGR_CBWBRI_BITS 14
571			`define DCCFGR_RES1_BITS 31:15
572
573			`// DCCFGR values`
574			`define DCCFGR_NCW 3'h0
575			`define DCCFGR_NCS 4'h5
576			`define DCCFGR_CBS 1'b0
577			`define DCCFGR_CWS 1'b0
578			`define DCCFGR_CCRI 1'b1
579			`define DCCFGR_CBIRI 1'b1
580			`define DCCFGR_CBPRI 1'b0
581			`define DCCFGR_CBLRI 1'b0
582			`define DCCFGR_CBFRI 1'b0
583			`define DCCFGR_CBWBRI 1'b1
584			`define DCCFGR_RES1 17'h00000
585
586			`// ICCFGR fields`
587			`define ICCFGR_NCW_BITS 2:0
588			`define ICCFGR_NCS_BITS 6:3
589			`define ICCFGR_CBS_BITS 7
590			`define ICCFGR_CWS_BITS 8
591			`define ICCFGR_CCRI_BITS 9
592			`define ICCFGR_CBIRI_BITS 10
593			`define ICCFGR_CBPRI_BITS 11
594			`define ICCFGR_CBLRI_BITS 12
595			`define ICCFGR_CBFRI_BITS 13
596			`define ICCFGR_CBWBRI_BITS 14
597			`define ICCFGR_RES1_BITS 31:15
598
599			`// ICCFGR values`
600			`define ICCFGR_NCW 3'h0
601			`define ICCFGR_NCS 4'h5
602			`define ICCFGR_CBS 1'b0
603			`define ICCFGR_CWS 1'b0
604			`define ICCFGR_CCRI 1'b1
605			`define ICCFGR_CBIRI 1'b1
606			`define ICCFGR_CBPRI 1'b0
607			`define ICCFGR_CBLRI 1'b0
608			`define ICCFGR_CBFRI 1'b0
609			`define ICCFGR_CBWBRI 1'b1
610			`define ICCFGR_RES1 17'h00000
611
612			`// DCFGR fields`
613			`define DCFGR_NDP_BITS 2:0
614			`define DCFGR_WPCI_BITS 3
615			`define DCFGR_RES1_BITS 31:4
616
617			`// DCFGR values`
618			`define DCFGR_NDP 3'h0
619			`define DCFGR_WPCI 1'b0
620			`define DCFGR_RES1 28'h0000000
621
622
623			`// Instruction opcode groups (basic)`
624			`define OR32_J 6'b000000
625			`define OR32_JAL 6'b000001
626			`define OR32_BNF 6'b000011
627			`define OR32_BF 6'b000100
628			`define OR32_NOP 6'b000101
629			`define OR32_MOVHI 6'b000110
630			`define OR32_MFSPR 6'b000111
631			`define OR32_XSYNC 6'b001000
632			`define OR32_RFE 6'b001001
633
634			`define OR32_MTSPR 6'b010000
635			`define OR32_JR 6'b010001
636			`define OR32_JALR 6'b010010
637
638			`define OR32_LWZ 6'b100001
639			`define OR32_LBZ 6'b100011
640			`define OR32_LBS 6'b100100
641			`define OR32_LHZ 6'b100101
642			`define OR32_LHS 6'b100110
643			`define OR32_ADDI 6'b100111
644			`define OR32_ADDIC 6'b101000
645			`define OR32_ANDI 6'b101001
646			`define OR32_ORI 6'b101010
647			`define OR32_XORI 6'b101011
648			`define OR32_MULI 6'b101100
649			`define OR32_MACI 6'b101101
650			`define OR32_SH_ROTI 6'b101110
651			`define OR32_SFXXI 6'b101111
652
653			`define OR32_SW 6'b110101
654			`define OR32_SB 6'b110110
655			`define OR32_SH 6'b110111
656			`define OR32_ALU 6'b111000
657			`define OR32_SFXX 6'b111001
658