OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [mp3_stable/] [mp3/] [rtl/] [verilog/] [or1200.xcv/] [dtlb.v] - Blame information for rev 266

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 266 lampret
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's Data TLB                                           ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6
////  http://www.opencores.org/cores/or1k/                        ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  Instantiation of DTLB.                                      ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - make it smaller and faster                               ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
// CVS Revision History
45
//
46
// $Log: not supported by cvs2svn $
47
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
48
// no message
49
//
50
//
51
 
52
// synopsys translate_off
53
`include "timescale.v"
54
// synopsys translate_on
55
`include "defines.v"
56
 
57
//
58
// Data TLB
59
//
60
 
61
module dtlb(
62
        // Rst and clk
63
        clk, rst,
64
 
65
        // I/F for translation
66
        tlb_en, vaddr, hit, ppn, uwe, ure, swe, sre,
67
 
68
        // SPR access
69
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
70
);
71
 
72
parameter dw = `OPERAND_WIDTH;
73
parameter aw = `OPERAND_WIDTH;
74
 
75
//
76
// I/O
77
//
78
 
79
//
80
// Clock and reset
81
//
82
input                           clk;
83
input                           rst;
84
 
85
//
86
// I/F for translation
87
//
88
input                           tlb_en;
89
input   [aw-1:0]         vaddr;
90
output                          hit;
91
output  [31:13]                 ppn;
92
output                          uwe;
93
output                          ure;
94
output                          swe;
95
output                          sre;
96
 
97
//
98
// SPR access
99
//
100
input                           spr_cs;
101
input                           spr_write;
102
input   [31:0]                   spr_addr;
103
input   [31:0]                   spr_dat_i;
104
output  [31:0]                   spr_dat_o;
105
 
106
//
107
// Internal wires and regs
108
//
109
wire    [31:19]                 vpn;
110
wire                            v;
111
wire    [5:0]                    tlb_index;
112
wire                            tlb_mr_en;
113
wire                            tlb_mr_we;
114
wire    [13:0]                   tlb_mr_ram_in;
115
wire    [13:0]                   tlb_mr_ram_out;
116
wire                            tlb_tr_en;
117
wire                            tlb_tr_we;
118
wire    [22:0]                   tlb_tr_ram_in;
119
wire    [22:0]                   tlb_tr_ram_out;
120
 
121
//
122
// Implemented bits inside match and translate registers
123
//
124
// dtlbwYmrX: vpn 31-19  v 0
125
// dtlbwYtrX: ppn 31-13  uwe 9  ure 8  swe 7  sre 6
126
//
127
// dtlb memory width:
128
// 19 bits for ppn
129
// 13 bits for vpn
130
// 1 bit for valid
131
// 4 bits for protection
132
 
133
//
134
// Enable for Match registers
135
//
136
assign tlb_mr_en = tlb_en | (spr_cs & !spr_addr[9]);
137
 
138
//
139
// Write enable for Match registers
140
//
141
assign tlb_mr_we = spr_cs & spr_write & !spr_addr[9];
142
 
143
//
144
// Enable for Translate registers
145
//
146
assign tlb_tr_en = tlb_en | (spr_cs & spr_addr[9]);
147
 
148
//
149
// Write enable for Translate registers
150
//
151
assign tlb_tr_we = spr_cs & spr_write & spr_addr[9];
152
 
153
//
154
// Output to SPRS unit
155
//
156
assign spr_dat_o = (spr_cs & !spr_write & !spr_addr[9]) ?
157
                        {vpn, {18{1'b1}}, v} :
158
                (spr_cs & !spr_write & spr_addr[9]) ?
159
                        {ppn, 3'b000, uwe, ure, swe, sre, {6{1'b1}}} :
160
                        32'h00000000;
161
 
162
//
163
// Assign outputs from Match registers
164
//
165
assign {vpn, v} = tlb_mr_ram_out;
166
 
167
//
168
// Assign to Match registers inputs
169
//
170
assign tlb_mr_ram_in = {spr_dat_i[31:19], spr_dat_i[0]};
171
 
172
//
173
// Assign outputs from Translate registers
174
//
175
assign {ppn, uwe, ure, swe, sre} = tlb_tr_ram_out;
176
 
177
//
178
// Assign to Translate registers inputs
179
//
180
assign tlb_tr_ram_in = {spr_dat_i[31:13], spr_dat_i[9:6]};
181
 
182
//
183
// Generate hit
184
//
185
assign hit = (vpn == vaddr[31:19]) & v;
186
 
187
//
188
// TLB index is normally vaddr[18:13]. If it is SPR access then index is
189
// spr_addr[5:0].
190
//
191
assign tlb_index = spr_cs ? spr_addr[5:0] : vaddr[18:13];
192
 
193
//
194
// Instantiation of DTLB Match Registers
195
//
196
generic_spram_64x14 dtlb_mr_ram(
197
        .clk(clk),
198
        .rst(rst),
199
        .ce(tlb_mr_en),
200
        .we(tlb_mr_we),
201
        .oe(1'b1),
202
        .addr(tlb_index),
203
        .di(tlb_mr_ram_in),
204
        .do(tlb_mr_ram_out)
205
);
206
 
207
//
208
// Instantiation of DTLB Translate Registers
209
//
210
generic_spram_64x23 dtlb_tr_ram(
211
        .clk(clk),
212
        .rst(rst),
213
        .ce(tlb_tr_en),
214
        .we(tlb_tr_we),
215
        .oe(1'b1),
216
        .addr(tlb_index),
217
        .di(tlb_tr_ram_in),
218
        .do(tlb_tr_ram_out)
219
);
220
 
221
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.