URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [mp3_stable/] [mp3/] [rtl/] [verilog/] [or1200.xcv/] [du.v] - Blame information for rev 1765

Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Debug Unit                                         ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Basic OR1200 debug unit.                                    ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
//
// Debug unit
//
 
module du(
        // RISC Internal Interface
        clk, rst,
        dclsu_lsuop, icfetch_op, ex_freeze, branch_op,
        du_stall, du_addr, du_dat_i, du_dat_o, du_read, du_write, du_except,
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
 
        // External Debug Interface
        dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,
        dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o
);
 
parameter dw = `OPERAND_WIDTH;
parameter aw = `OPERAND_WIDTH;
 
//
// I/O
//
 
//
// RISC Internal Interface
//
input                           clk;            // Clock
input                           rst;            // Reset
input   [`LSUOP_WIDTH-1:0]       dclsu_lsuop;    // LSU status
input   [`FETCHOP_WIDTH-1:0]     icfetch_op;     // IFETCH unit status
input                           ex_freeze;      // EX stage freeze
input   [`BRANCHOP_WIDTH-1:0]    branch_op;      // Branch op
output                          du_stall;       // Debug Unit Stall
output  [aw-1:0]         du_addr;        // Debug Unit Address
input   [dw-1:0]         du_dat_i;       // Debug Unit Data In
output  [dw-1:0]         du_dat_o;       // Debug Unit Data Out
output                          du_read;        // Debug Unit Read Enable
output                          du_write;       // Debug Unit Write Enable
input   [`EXCEPT_WIDTH-1:0]      du_except;      // Exception started
input                           spr_cs;         // SPR Chip Select
input                           spr_write;      // SPR Read/Write
input   [aw-1:0]         spr_addr;       // SPR Address
input   [dw-1:0]         spr_dat_i;      // SPR Data Input
output  [dw-1:0]         spr_dat_o;      // SPR Data Output
 
//
// External Debug Interface
//
input                           dbg_stall_i;    // External Stall Input
input   [dw-1:0]         dbg_dat_i;      // External Data Input
input   [aw-1:0]         dbg_adr_i;      // External Address Input
input   [2:0]                    dbg_op_i;       // External Operation Select Input
input                           dbg_ewt_i;      // External Watchpoint Trigger Input
output  [3:0]                    dbg_lss_o;      // External Load/Store Unit Status
output  [1:0]                    dbg_is_o;       // External Insn Fetch Status
output  [10:0]                   dbg_wp_o;       // Watchpoints Outputs
output                          dbg_bp_o;       // Breakpoint Output
output  [dw-1:0]         dbg_dat_o;      // External Data Output
 
 
//
// Some connections go directly from the CPU through DU to Debug I/F
//
assign dbg_lss_o = dclsu_lsuop;
assign dbg_is_o = icfetch_op;
assign dbg_wp_o = 11'b000_0000_0000;
assign dbg_dat_o = du_dat_i;
 
//
// Some connections go directly from Debug I/F through DU to the CPU
//
assign du_stall = dbg_stall_i;
assign du_addr = dbg_adr_i;
assign du_dat_o = dbg_dat_i;
assign du_read = (dbg_op_i == `DU_OP_READSPR);
assign du_write = (dbg_op_i == `DU_OP_WRITESPR);
 
`ifdef DU_IMPLEMENTED
 
//
// Debug Mode Register 1 (only ST and BT implemented)
//
`ifdef DU_DMR1
reg     [23:22]                 dmr1;           // DMR1 implemented (ST & BT)
`else
wire    [23:22]                 dmr1;           // DMR1 not implemented
`endif
 
//
// Debug Mode Register 2 (not implemented)
//
`ifdef DU_DMR2
wire    [31:0]                   dmr2;           // DMR not implemented
`endif
 
//
// Debug Stop Register
//
`ifdef DU_DSR
reg     [13:0]                   dsr;            // DSR implemented
`else
wire    [13:0]                   dsr;            // DSR not implemented
`endif
 
//
// Debug Reason Register
//
`ifdef DU_DRR
reg     [13:0]                   drr;            // DRR implemented
reg     [13:0]                   except_unmasked;
`else
wire    [13:0]                   drr;            // DRR not implemented
`endif
 
//
// Internal wires
//
wire    [13:0]                   except_masked;
wire                            dmr1_sel;       // DMR1 select
wire                            dsr_sel;        // DSR select
wire                            drr_sel;        // DRR select
reg                             dbg_bp_r;
`ifdef DU_READREGS
reg     [31:0]                   spr_dat_o;
`endif
 
//
// DU registers address decoder
//
`ifdef DU_DMR1
assign dmr1_sel = (spr_cs && (spr_addr[`SPROFS_BITS] == `DU_OFS_DMR1));
`endif
`ifdef DU_DSR
assign dsr_sel = (spr_cs && (spr_addr[`SPROFS_BITS] == `DU_OFS_DSR));
`endif
`ifdef DU_DRR
assign drr_sel = (spr_cs && (spr_addr[`SPROFS_BITS] == `DU_OFS_DRR));
`endif
 
//
// Decode started exception
//
always @(du_except)
        case (du_except)
                4'he: except_unmasked = 14'b10_0000_0000_0000;
                4'hd: except_unmasked = 14'b01_0000_0000_0000;
                4'hc: except_unmasked = 14'b00_1000_0000_0000;
                4'hb: except_unmasked = 14'b00_0100_0000_0000;
                4'ha: except_unmasked = 14'b00_0010_0000_0000;
                4'h9: except_unmasked = 14'b00_0001_0000_0000;
                4'h8: except_unmasked = 14'b00_0000_1000_0000;
                4'h7: except_unmasked = 14'b00_0000_0100_0000;
                4'h6: except_unmasked = 14'b00_0000_0010_0000;
                4'h5: except_unmasked = 14'b00_0000_0001_0000;
                4'h4: except_unmasked = 14'b00_0000_0000_1000;
                4'h3: except_unmasked = 14'b00_0000_0000_0100;
                4'h2: except_unmasked = 14'b00_0000_0000_0010;
                4'h1: except_unmasked = 14'b00_0000_0000_0001;
                default: except_unmasked = 14'b00_0000_0000_0000;
        endcase
 
//
// Get only 'stop' exceptions
//
assign except_masked = dsr & except_unmasked;
 
//
// dbg_bp_o is registered
//
assign dbg_bp_o = dbg_bp_r;
 
//
// Breakpoint activation register
//
always @(posedge clk or posedge rst)
        if (rst)
                dbg_bp_r <= #1 1'b0;
        else
                dbg_bp_r <= |except_masked
`ifdef DU_DMR1_ST
                        | ~ex_freeze & dmr1[`DU_DMR1_ST]
`endif
`ifdef DU_DMR1_BT
                        | ~ex_freeze & (branch_op != `BRANCHOP_NOP) & dmr1[`DU_DMR1_BT]
`endif
                        ;
 
//
// Write to DMR1
//
`ifdef DU_DMR1
always @(posedge clk or posedge rst)
        if (rst)
                dmr1 <= 2'b00;
        else if (dmr1_sel && spr_write)
                dmr1 <= #1 spr_dat_i[23:22];
`else
assign dmr1 = 2'b00;
`endif
 
//
// DMR2 bits tied to zero
//
`ifdef DU_DMR2
assign dmr2 = 32'h0000_0000;
`endif
 
//
// Write to DSR
//
`ifdef DU_DSR
always @(posedge clk or posedge rst)
        if (rst)
                dsr <= 14'b0;
        else if (dsr_sel && spr_write)
                dsr <= #1 spr_dat_i[13:0];
`else
assign dsr = 14'b0;
`endif
 
//
// Write to DRR
//
`ifdef DU_DRR
always @(posedge clk or posedge rst)
        if (rst)
                drr <= 14'b0;
        else if (drr_sel && spr_write)
                drr <= #1 spr_dat_i[13:0];
        else
                drr <= #1 drr | except_masked;
`else
assign drr = 14'b0;
`endif
 
//
// Read DU registers
//
`ifdef DU_READREGS
always @(spr_addr or dsr or drr)
        case (spr_addr[`SPROFS_BITS])
`ifdef DU_DMR1
                `DU_OFS_DMR1:
                        spr_dat_o = {8'b0, dmr1, 22'b0};
`endif
`ifdef DU_DMR2
                `DU_OFS_DMR2:
                        spr_dat_o = dmr2;
`endif
`ifdef DU_DSR
                `DU_OFS_DSR:
                        spr_dat_o = {18'b0, dsr};
`endif
`ifdef DU_DRR
                `DU_OFS_DRR:
                        spr_dat_o = {18'b0, drr};
`endif
                default:
                        spr_dat_o = 32'h0000_0000;
        endcase
`endif
 
`else
 
//
// When DU is not implemented, drive all outputs as would when DU is disabled
//
assign dbg_bp_o = 1'b0;
 
//
// Read DU registers
//
`ifdef DU_READREGS
assign spr_dat_o = 32'h0000_0000;
`ifdef DU_UNUSED_ZERO
`endif
`endif
 
`endif
 
endmodule

Browse

Tools

Subversion Repositories or1k

[/] [or1k/] [branches/] [mp3_stable/] [mp3/] [rtl/] [verilog/] [or1200.xcv/] [du.v] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	266	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Debug Unit ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Basic OR1200 debug unit. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`//`
48
49			`// synopsys translate_off`
50			`include "timescale.v"
51			`// synopsys translate_on`
52			`include "defines.v"
53
54			`//`
55			`// Debug unit`
56			`//`
57
58			`module du(`
59			`// RISC Internal Interface`
60			`clk, rst,`
61			`dclsu_lsuop, icfetch_op, ex_freeze, branch_op,`
62			`du_stall, du_addr, du_dat_i, du_dat_o, du_read, du_write, du_except,`
63			`spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,`
64
65			`// External Debug Interface`
66			`dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,`
67			`dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o`
68			`);`
69
70			parameter dw = `OPERAND_WIDTH;
71			parameter aw = `OPERAND_WIDTH;
72
73			`//`
74			`// I/O`
75			`//`
76
77			`//`
78			`// RISC Internal Interface`
79			`//`
80			`input clk; // Clock`
81			`input rst; // Reset`
82			input [`LSUOP_WIDTH-1:0] dclsu_lsuop; // LSU status
83			input [`FETCHOP_WIDTH-1:0] icfetch_op; // IFETCH unit status
84			`input ex_freeze; // EX stage freeze`
85			input [`BRANCHOP_WIDTH-1:0] branch_op; // Branch op
86			`output du_stall; // Debug Unit Stall`
87			`output [aw-1:0] du_addr; // Debug Unit Address`
88			`input [dw-1:0] du_dat_i; // Debug Unit Data In`
89			`output [dw-1:0] du_dat_o; // Debug Unit Data Out`
90			`output du_read; // Debug Unit Read Enable`
91			`output du_write; // Debug Unit Write Enable`
92			input [`EXCEPT_WIDTH-1:0] du_except; // Exception started
93			`input spr_cs; // SPR Chip Select`
94			`input spr_write; // SPR Read/Write`
95			`input [aw-1:0] spr_addr; // SPR Address`
96			`input [dw-1:0] spr_dat_i; // SPR Data Input`
97			`output [dw-1:0] spr_dat_o; // SPR Data Output`
98
99			`//`
100			`// External Debug Interface`
101			`//`
102			`input dbg_stall_i; // External Stall Input`
103			`input [dw-1:0] dbg_dat_i; // External Data Input`
104			`input [aw-1:0] dbg_adr_i; // External Address Input`
105			`input [2:0] dbg_op_i; // External Operation Select Input`
106			`input dbg_ewt_i; // External Watchpoint Trigger Input`
107			`output [3:0] dbg_lss_o; // External Load/Store Unit Status`
108			`output [1:0] dbg_is_o; // External Insn Fetch Status`
109			`output [10:0] dbg_wp_o; // Watchpoints Outputs`
110			`output dbg_bp_o; // Breakpoint Output`
111			`output [dw-1:0] dbg_dat_o; // External Data Output`
112
113
114			`//`
115			`// Some connections go directly from the CPU through DU to Debug I/F`
116			`//`
117			`assign dbg_lss_o = dclsu_lsuop;`
118			`assign dbg_is_o = icfetch_op;`
119			`assign dbg_wp_o = 11'b000_0000_0000;`
120			`assign dbg_dat_o = du_dat_i;`
121
122			`//`
123			`// Some connections go directly from Debug I/F through DU to the CPU`
124			`//`
125			`assign du_stall = dbg_stall_i;`
126			`assign du_addr = dbg_adr_i;`
127			`assign du_dat_o = dbg_dat_i;`
128			assign du_read = (dbg_op_i == `DU_OP_READSPR);
129			assign du_write = (dbg_op_i == `DU_OP_WRITESPR);
130
131			`ifdef DU_IMPLEMENTED
132
133			`//`
134			`// Debug Mode Register 1 (only ST and BT implemented)`
135			`//`
136			`ifdef DU_DMR1
137			`reg [23:22] dmr1; // DMR1 implemented (ST & BT)`
138			`else
139			`wire [23:22] dmr1; // DMR1 not implemented`
140			`endif
141
142			`//`
143			`// Debug Mode Register 2 (not implemented)`
144			`//`
145			`ifdef DU_DMR2
146			`wire [31:0] dmr2; // DMR not implemented`
147			`endif
148
149			`//`
150			`// Debug Stop Register`
151			`//`
152			`ifdef DU_DSR
153			`reg [13:0] dsr; // DSR implemented`
154			`else
155			`wire [13:0] dsr; // DSR not implemented`
156			`endif
157
158			`//`
159			`// Debug Reason Register`
160			`//`
161			`ifdef DU_DRR
162			`reg [13:0] drr; // DRR implemented`
163			`reg [13:0] except_unmasked;`
164			`else
165			`wire [13:0] drr; // DRR not implemented`
166			`endif
167
168			`//`
169			`// Internal wires`
170			`//`
171			`wire [13:0] except_masked;`
172			`wire dmr1_sel; // DMR1 select`
173			`wire dsr_sel; // DSR select`
174			`wire drr_sel; // DRR select`
175			`reg dbg_bp_r;`
176			`ifdef DU_READREGS
177			`reg [31:0] spr_dat_o;`
178			`endif
179
180			`//`
181			`// DU registers address decoder`
182			`//`
183			`ifdef DU_DMR1
184			assign dmr1_sel = (spr_cs && (spr_addr[`SPROFS_BITS] == `DU_OFS_DMR1));
185			`endif
186			`ifdef DU_DSR
187			assign dsr_sel = (spr_cs && (spr_addr[`SPROFS_BITS] == `DU_OFS_DSR));
188			`endif
189			`ifdef DU_DRR
190			assign drr_sel = (spr_cs && (spr_addr[`SPROFS_BITS] == `DU_OFS_DRR));
191			`endif
192
193			`//`
194			`// Decode started exception`
195			`//`
196			`always @(du_except)`
197			`case (du_except)`
198			`4'he: except_unmasked = 14'b10_0000_0000_0000;`
199			`4'hd: except_unmasked = 14'b01_0000_0000_0000;`
200			`4'hc: except_unmasked = 14'b00_1000_0000_0000;`
201			`4'hb: except_unmasked = 14'b00_0100_0000_0000;`
202			`4'ha: except_unmasked = 14'b00_0010_0000_0000;`
203			`4'h9: except_unmasked = 14'b00_0001_0000_0000;`
204			`4'h8: except_unmasked = 14'b00_0000_1000_0000;`
205			`4'h7: except_unmasked = 14'b00_0000_0100_0000;`
206			`4'h6: except_unmasked = 14'b00_0000_0010_0000;`
207			`4'h5: except_unmasked = 14'b00_0000_0001_0000;`
208			`4'h4: except_unmasked = 14'b00_0000_0000_1000;`
209			`4'h3: except_unmasked = 14'b00_0000_0000_0100;`
210			`4'h2: except_unmasked = 14'b00_0000_0000_0010;`
211			`4'h1: except_unmasked = 14'b00_0000_0000_0001;`
212			`default: except_unmasked = 14'b00_0000_0000_0000;`
213			`endcase`
214
215			`//`
216			`// Get only 'stop' exceptions`
217			`//`
218			`assign except_masked = dsr & except_unmasked;`
219
220			`//`
221			`// dbg_bp_o is registered`
222			`//`
223			`assign dbg_bp_o = dbg_bp_r;`
224
225			`//`
226			`// Breakpoint activation register`
227			`//`
228			`always @(posedge clk or posedge rst)`
229			`if (rst)`
230			`dbg_bp_r <= #1 1'b0;`
231			`else`
232			`dbg_bp_r <= \|except_masked`
233			`ifdef DU_DMR1_ST
234			\| ~ex_freeze & dmr1[`DU_DMR1_ST]
235			`endif
236			`ifdef DU_DMR1_BT
237			\| ~ex_freeze & (branch_op != `BRANCHOP_NOP) & dmr1[`DU_DMR1_BT]
238			`endif
239			`;`
240
241			`//`
242			`// Write to DMR1`
243			`//`
244			`ifdef DU_DMR1
245			`always @(posedge clk or posedge rst)`
246			`if (rst)`
247			`dmr1 <= 2'b00;`
248			`else if (dmr1_sel && spr_write)`
249			`dmr1 <= #1 spr_dat_i[23:22];`
250			`else
251			`assign dmr1 = 2'b00;`
252			`endif
253
254			`//`
255			`// DMR2 bits tied to zero`
256			`//`
257			`ifdef DU_DMR2
258			`assign dmr2 = 32'h0000_0000;`
259			`endif
260
261			`//`
262			`// Write to DSR`
263			`//`
264			`ifdef DU_DSR
265			`always @(posedge clk or posedge rst)`
266			`if (rst)`
267			`dsr <= 14'b0;`
268			`else if (dsr_sel && spr_write)`
269			`dsr <= #1 spr_dat_i[13:0];`
270			`else
271			`assign dsr = 14'b0;`
272			`endif
273
274			`//`
275			`// Write to DRR`
276			`//`
277			`ifdef DU_DRR
278			`always @(posedge clk or posedge rst)`
279			`if (rst)`
280			`drr <= 14'b0;`
281			`else if (drr_sel && spr_write)`
282			`drr <= #1 spr_dat_i[13:0];`
283			`else`
284			`drr <= #1 drr \| except_masked;`
285			`else
286			`assign drr = 14'b0;`
287			`endif
288
289			`//`
290			`// Read DU registers`
291			`//`
292			`ifdef DU_READREGS
293			`always @(spr_addr or dsr or drr)`
294			case (spr_addr[`SPROFS_BITS])
295			`ifdef DU_DMR1
296			`DU_OFS_DMR1:
297			`spr_dat_o = {8'b0, dmr1, 22'b0};`
298			`endif
299			`ifdef DU_DMR2
300			`DU_OFS_DMR2:
301			`spr_dat_o = dmr2;`
302			`endif
303			`ifdef DU_DSR
304			`DU_OFS_DSR:
305			`spr_dat_o = {18'b0, dsr};`
306			`endif
307			`ifdef DU_DRR
308			`DU_OFS_DRR:
309			`spr_dat_o = {18'b0, drr};`
310			`endif
311			`default:`
312			`spr_dat_o = 32'h0000_0000;`
313			`endcase`
314			`endif
315
316			`else
317
318			`//`
319			`// When DU is not implemented, drive all outputs as would when DU is disabled`
320			`//`
321			`assign dbg_bp_o = 1'b0;`
322
323			`//`
324			`// Read DU registers`
325			`//`
326			`ifdef DU_READREGS
327			`assign spr_dat_o = 32'h0000_0000;`
328			`ifdef DU_UNUSED_ZERO
329			`endif
330			`endif
331
332			`endif
333
334			`endmodule`